JP2002032270A - Main storage controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a main storage device to enable correction a failure of one chip of a storage element with the number of redundant bits smaller than the number of originally required redundant bits to correct the failure one chip of the storage element. SOLUTION: Correction of a data error is enabled even when one chip of an SDRAM is failed by performing mask control by a mask control circuit 109 of a man storage part 100, making respective paired SDRAM chips 140-141, 142-143, 144-145, 146-147, 148-149 take charge of pieces of data on halves and using an error correctable ECC with data width which is half of the data width of one chip the SDRAM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device used in a computer system and the like, and more particularly to a main storage control system for correcting a data error due to a failure in the storage device.

[0002]

2. Description of the Related Art A main storage device using a large amount of storage elements such as DRAMs has been conventionally capable of correcting data even if one storage element chip fails in order to ensure high reliability as a device. Redundant bit addition method (ECC: Error Checkin
g and Correcting). FIG. 1 is a configuration diagram of a conventional memory controller and storage elements. A main storage device includes a memory controller 10, storage elements 20 to 49, and a data bus 15. In a conventional structure, for example, a memory controller 10 and an 8-bit storage element 20 per chip are used.
To 29 are connected by a data bus 15 to form a main storage device with ten DRAMs, thereby enabling a redundant bit addition method that can be corrected. In this case, the data is 64 bits,
The redundant bits are 16 bits. With this number of redundant bits, an 8-bit burst (block, continuous) error can be corrected. That is, even if a failure occurs in one memory element chip, correct data can be obtained. As a result, it is possible to greatly improve the reliability of the storage device. The relationship between the number of data bits, the number of correction burst bits, and the number of redundant bits is, for example, 8 bits for 64 bits of data.
A 16-bit redundant bit is required to correct a burst (block, continuous) error of bits, and 32 to correct a 16-bit burst error for 64 bits of data.
Bit redundancy is required.

[0003]

However, with the increase in the capacity of the main storage device, for example, when the main storage device is configured as shown in FIG. To correct a chip failure, that is, a 16-bit burst error, 32 redundant bits are required.
The data bus connecting the memory controller and the storage elements requires 64 bits of data and redundant bits
32 bits is 96 bits. As described above, in order to correct a fault in one chip, the number of redundant bits required increases as a large-capacity storage element is used. .

The present invention has been made to solve such a conventional problem, and requires one memory element chip with a smaller number of redundant bits than originally required for correcting a failure of one memory element chip. It is an object of the present invention to provide a main storage device capable of correcting a failure in the main storage.

[0005]

According to the present invention, there is provided a main storage unit comprising a plurality of storage elements having a mask control line for input / output data in units of n bits, and a control unit for controlling the main storage unit. In the main storage device including the main storage control unit, the main storage control unit has a unit that controls a mask control line of each storage element of the main storage unit, and a plurality of different storage elements are stored in units of n bits. Is achieved by accessing.

Further, the object is to provide a main storage unit comprising a plurality of storage elements having a mask control line for input / output data in units of n bits, and a main storage control unit for controlling the main storage unit. In the main storage device, the main storage control unit includes:
This is achieved by means for adding a redundant code to data input by write access and controlling a mask control line of a plurality of different storage elements, and writing the redundant code-added data to a plurality of different storage elements in n-bit units. You.

Further, the object is to form a main storage section comprising a plurality of storage elements having a mask control line for input / output data in units of n bits, and a main storage control section for controlling the main storage section. In the main storage device, the main storage control unit includes:
This is achieved by controlling the mask control lines of a plurality of different storage elements by a read access, and reading redundant-coded data from the plurality of different storage elements in units of n bits.

The above object is also achieved by a main storage section comprising a plurality of storage elements having a mask control line for input / output data in units of n bits, and a main storage control section for controlling the main storage section. In the main storage device, the main storage control unit includes:
This is achieved by reading the data with the redundant code from the main storage unit by read access and correcting the data error when a bit error of n bits or less occurs in the target data.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a main storage device according to the present invention will be described below in detail with reference to the drawings.

In this embodiment, an SDRAM capable of inputting and outputting 16 bits per chip is used as a storage element. First, data input / output and data mask control of the SDRAM will be described.

FIG. 2A shows a masking operation of write data. 50 is an SDRAM chip, 51 is write data, 52 is a data bus, 53 is data written to the SDRAM chip, and 54 to 55 are SDRAM chips. This is a mask control signal. SDR
The AM chip 50 is a storage element capable of inputting data with a 16-bit width, and inputs data via data pins DQ <0-15>. The mask control signal 54 is input to the DQMU pin of the SDRAM chip 50, and when the value is '0', the upper 8 bits of the 16 bits input to DQ <0-15> are input to the SDRAM chip 50 as they are,
When the value is '1', the upper 16 bits input to DQ <0-15>
8 bits are masked and input to the SDRAM chip 50. That is, it is possible to select whether or not to write the upper 8 bits DQ <0-7> of the data input to DQ <0-15> to the SDRAM chip 50 by the mask control signal 54. Mask control signal 55
Is input to the DQML pin of the SDRAM chip 50 and when the value is '0'
The lower 8 bits of the 16 bits input to DQ <0-15> are directly input to the SDRAM chip 50, and when the value is '1', DQ <0-15>
Mask the lower 8 bits of the 16 bits input to
Input to DRAM chip 50. That is, the mask control signal 55
The lower 8 bits DQ <8 of the data input to DQ <0-15>
−15> can be selected to be written to the SDRAM chip 50 or not. In FIG. 2A, since the value '1' is input to the mask control line 54 and the value '0' is input to the mask control line 55, the upper 8 bits of the 16 bits of the write data 51 are masked. The upper 8 of the write data 51
The data 53 with the bits masked is written.

FIG. 2B is a diagram for explaining the masking operation of the read data. 60 is an SDRAM chip, 61 is read data, 62 is a data bus, 63 is data written to an SDRAM chip, and 64 to 65. Is a mask control signal of the SDRAM. The SDRAM chip 60 is a storage element capable of outputting data in a 16-bit width, and outputs data via data pins DQ <0-15>. The mask control signal 64 is the DQM of the SDRAM chip 60.
The upper 8 bits of the 16-bit data 63 that is input to the U pin and written when the value is '0' is output to DQ <0-7> as it is, and when the value is '1', the 16 bits written Data 63
Mask the upper 8 bits of DQ <0-7> and do not output to DQ <0-7>. That is, it is possible to select whether or not to output the upper 8 bits DQ <0-7> of the data to be output to DQ <0-15> to the data bus 62 by the mask control signal 64. Mask control signal 65
Is input to the DQML pin of the SDRAM chip 60, and when the value is '0', the lower 8 bits of the 16-bit data 63 written are output as is to DQ <8−15>, and when the value is '1', the data is written. Mask the lower 8 bits of the 16-bit data 63
8−15> is not output. That is, the lower 8 bits DQ <8-15> of the data output to DQ <0-15> by the mask control signal 65
Is output to the data bus 62. In FIG. 2B, since the value “0” is input to the mask control line 64 and the value “1” is input to the mask control line 65, the lower 8 bits of the 16-bit data 63 written in the SDRAM chip are Since the bits are masked and output on DQ <0-15>, SDR
Data 61 obtained by masking the lower 8 bits of data 63 written in AM chip 50 is output.

In this embodiment, a main storage device is constructed by using SDRAM as a storage element. FIG. 3 is a block diagram showing the configuration of the main storage device. 100 is a main storage control unit, 130 is a main storage unit, 120 is a data bus, and 128 to 129 are mask control lines. The main memory control unit 100 includes a write data register 101,
Read data register 102, write address register 106, read address register 107, selector 108, E
CC generation circuit 102, error correction circuit 104, ECC check circuit 10
5. It is composed of a mask control circuit 109. Main memory 130
Is composed of SDRAM chips 140 to 149. The main memory control unit 100 and the main memory unit 130 include a data bus 120, a mask control line 1
Connected at 28-129. The ECC generation circuit 102 receives 8-byte data from the write data register 101, adds 16-bit redundant bits to the data, and sends the data to the data bus 120. The ECC check circuit 105 receives 8 bytes of data and 16 redundant bits from the data bus 120, and detects a data error up to an 8-bit burst. When the ECC check circuit 105 detects a data error, the error correction circuit 104 corrects the 8 bits in which the data error has occurred, and stores the corrected data in the read data register. The selector 108 sets the write address 106 at the time of write access.
At the time of read access, the read address 107 is selected. The mask control circuit 109 checks a predetermined bit of the address output from the selector 108, and if it is '0', the mask control circuit 109
'0' is output to 128, '1' is output to the mask control line 129, and '1' is output to the mask control line 128 when a predetermined bit of the address output from the selector 108 is '1'. , Mask control line 12
Outputs '0' to 9. As described above, the mask control circuit 109
The mask control lines 128 to 129 are controlled so as to be in correspondence with the address for accessing the main storage unit 130. The data bus 120 has a total of 80 bits including 8 bytes of data and 16 bits of redundant bits. For data input / output between the main memory control unit 100 and the main memory unit 130, bits <0-15> are sent to the SDRAM chips 148 to 149 via the data bus 125, and bits <16-
31> is performed on the SDRAM chips 146 to 147 via the data bus 124, and the bits <32-47> are
Bits <48-63> are performed on the SDRAM chips 142-143 via the data bus 122, and bits <64-79> are performed on the SDRAM chips via the data bus 121. 140-141. The mask control line 128 is S
It is connected to the DQML pins of the DRAM chips 140, 142, 144, 146, 148, and connected to the DQMU pins of the SDRAM chips 141, 143, 145, 147, 149. The mask control line 129 is connected to the SDRAM chips 140, 1
Connected to DQMU pins of 42, 144, 146, 148, SDRAM chip
Connected to DQML pins 141, 143, 145, 147, 149. Hereinafter, the operations of the main storage control unit 100 and the main storage unit 130 at the time of data writing and data reading, respectively, will be described.

First, the data write operation will be described with reference to FIGS. In FIG. 4, 200 is 8-byte write data stored in the write data register 101, 202 is 10-byte redundant bit-added write data to which 16 bits are added by the ECC circuit 102, and 203 to 207 are respectively 16-bit data transmitted to the data buses 121-125 corresponds to the data, and 220-229 correspond to the SDRAM chips 140-149, respectively.
40 corresponds to the mask control line 128, and 241 corresponds to the mask control line 129. Data writing is performed as follows. Write data register 101 of main memory control unit 100
Is set to the write data 200, and the write address is set to the write address register 106. The ECC generation circuit 102 adds 16 redundant bits to the write data 200 to generate write data 202 with redundant bits. The write data 202 with redundant bits is divided into data 203 to 207 every 16 bits, and the data 203 is an SDRAM chip.
The data 204 is input to the SDRAM chips 222 to 223.
, The data 205 is input to the SDRAM chips 224 to 225, the data 206 is input to the SDRAM chips 226 to 227, and the data 207 is input to the SDRAM chips 228 to 229.

In the SDRAM chip 220, “0” is input to the DQML pin by the mask control line 240, and the DQML is
Since “1” is input to the MU pin, the upper 8 bits of the 16-bit data 203 are not written, and the lower 8 bits are written. In the SDRAM chip 221, '0' is input to the DQMU pin by the mask control line 240, '1' is input to the DQML pin by the mask control line 241, and the lower 8 bits of the 16-bit data 203
No bits are written and the upper 8 bits are written. SDR
The AM chip 222 sets the DQML pin to '0' by the mask control line 240.
Is input to the DQMU pin by the mask control line 241, and the upper 8 bits of the 16-bit data 204 are not written but the lower 8 bits are written. SDRAM chip 22
For 3, the mask control line 240 inputs '0' to the DQMU pin, the mask control line 241 inputs '1' to the DQML pin, and the lower 8 bits of the 16-bit data 204 are not written and the upper 8 bits Is written. In the SDRAM chip 224, '0' is input to the DQML pin by the mask control line 240, and '1' is input to the DQMU pin by the mask control line 241.The upper 8 bits of the 16-bit data 205 are not written but lower Eight bits are written. The SDRAM chip 225 has a mask control line
'0' is input to the DQMU pin by 240 and the mask control line 241
As a result, '1' is input to the DQML pin, and the lower 8 bits of the 16-bit data 205 are not written, but the upper 8 bits are written. In the SDRAM chip 226, '0' is input to the DQML pin by the mask control line 240, and DQML is input by the mask control line 241.
Since “1” is input to the MU pin, the upper 8 bits of the 16-bit data 206 are not written, and the lower 8 bits are written. In the SDRAM chip 227, '0' is input to the DQMU pin by the mask control line 240, '1' is input to the DQML pin by the mask control line 241, and the lower 8 bits of the 16-bit data 206
No bits are written and the upper 8 bits are written. SDR
AM chip 228 outputs '0' to DQML pin by mask control line 240.
Is input to the DQMU pin via the mask control line 241, and the upper 8 bits of the 16-bit data 207 are not written but the lower 8 bits are written. SDRAM chip 22
In 9, '0' is input to the DQMU pin by the mask control line 240 and '1' is input to the DQML pin by the mask control line 241, and the lower 8 bits of the 16-bit data 207 are not written and the upper 8 bits are not written. Is written. Mask control lines 240 to 241
Is inverted, the relationship of the eight bits written to each of the SDRAM chips 220 to 229 is reversed. In this way, the SDRAM chips 220 to 221 form a pair and half-input 16-bit data 203, and the SDRAM chips 222 to 223 form a pair and half-input 16-bit data 204. Form a pair at 225 and input half of 16-bit data 205 at a time, and form a pair at SDRAM chips 226-227.
Bit data 206 is input in half, and the SDRAM chip 228
By forming pairs in ~ 229 and inputting 16-bit data 207 by half, 5 16-bit data is converted into 10 SDRAM
Write to chips 220-229.

Next, the data read operation will be described with reference to FIG.
This will be described with reference to FIG. In FIG. 5, 300 to 309 are SDRA
Compatible with M chips 140-149, 350-359 are 16-bit data stored in SDRAM chips 300-309, 330-3
Reference numeral 34 denotes 1 sent from the main storage unit 130 to the data buses 121 to 125.
Each corresponds to 6-bit data, 341 is EC
Eight-byte error-free read data corrected by the C check circuit 105 and the error correction circuit 104, 340 is 10-byte read data with redundant bits input from the data bus 120, and 320 is corresponding to the mask control line 128. Yes, 321
Corresponds to the mask control line 129. Reading of data is performed as follows. The SDRAM chips 300 to 301 output 16-bit data 330, the SDRAM chips 302 to 303 output 16-bit data 331, the SDRAM chips 304 to 305 output 16-bit data 332, and the SDRAM chips 306 to 307. Outputs 16-bit data 333, and the SDRAM chips 308 to 309 output 16-bit data 334. The data 203 to 207 are input to the main memory control unit 100 via the data bus 120 and received as read data 340 with redundant bits. The ECC check circuit 105 checks the read data 340 with redundant bits,
If there is no error, the 8-byte read data excluding the redundant bits is sent to the read data register 103. If there is an error, the data error is corrected by the error correction circuit 104, and then the 8-byte read data is read into the read data register 1.
Send to 03.

In the SDRAM chip 300, “1” is input to the DQML pin by the mask control line 320, and the DQ
'0' is input to the MU pin, the lower 8 bits of 16-bit data 350 are not output, only the upper 8 bits are output, and SD
The RAM chip 301 sets the DQMU pin to '1' by the mask control line 320.
Is input to the DQML pin by the mask control line 321, and only the lower 8 bits are output without outputting the upper 8 bits of the 16-bit data 351.
The 16-bit data 330 with the bits combined is the data bus 121
Is output to In the SDRAM chip 302, “1” is input to the DQML pin by the mask control line 320, and
When '0' is input to the DQMU pin, 16-bit data 352
Output only the upper 8 bits without outputting the lower 8 bits of
The SDRAM chip 303 is connected to the DQMU pin by the mask control line 320.
1 is input, and '0' is input to the DQML pin by the mask control line 321.Only the lower 8 bits are output without outputting the upper 8 bits of the 16-bit data 353. The combined 16-bit data 331 is the data bus
Output to 122. The SDRAM chip 304 has a mask control line 320
As a result, '1' is input to the DQML pin, '0' is input to the DQMU pin by the mask control line 321, and 16-bit data 3
The lower 8 bits of 54 are not output but only the upper 8 bits are output.In the SDRAM chip 305, '1' is input to the DQMU pin by the mask control line 320, and '0' is input to the DQML pin by the mask control line 321. The top 8 of 16-bit data 355
Since only the lower 8 bits are output without outputting the bit,
16-bit data 332 obtained by combining the respective 8 bits is output to the data bus 123. In the SDRAM chip 306, '1' is input to the DQML pin by the mask control line 320, '0' is input to the DQMU pin by the mask control line 321, and the lower 8 bits of the 16-bit data 356 are not output. The SDRAM chip 307 outputs '1' to the DQMU pin via the mask control line 320, and outputs the DQ signal via the mask control line 321.
Since '0' is input to the ML pin and only the lower 8 bits are output without outputting the upper 8 bits of the 16-bit data 357, the 16-bit data 333 combining the respective 8 bits is output.
Is output to the data bus 124. In the SDRAM chip 308, '1' is input to the DQML pin by the mask control line 320, '0' is input to the DQMU pin by the mask control line 321, and the lower 8 bits of the 16-bit data 358 are not output. Only the upper 8 bits are output to the SDRAM chip 309 and the mask control line 320
'1' is input to the DQMU pin, '0' is input to the DQML pin by the mask control line 321, and 16-bit data 3
Since only the lower 8 bits are output without outputting the upper 8 bits of 59, 16-bit data 334 including the respective 8 bits is output to the data bus 125. Mask control line 320
When ~ 321 is inverted, each SDRAM chip 300 ~ 3
The relationship of the 8 bits read from 09 is reversed. In this way, the SDRAM chips 300 to 301 form a pair to output 16-bit data 330 by half, and the SDRAM chips 302 to 303 form a pair to output 16-bit data 331 by half.
16 bits of data 33 in pairs with DRAM chips 304 to 305
2 is output in half, SDRAM chips 306 to 307 form a pair, and 16-bit data 333 is output in half, SDRAM chips
A pair is formed at 308 to 309 to output half of the 16-bit data 334, and 10 bytes of read data with redundant bits are read from the five 16-bit data. As mentioned above,
By writing and reading 16-bit data by performing mask control and sharing the two SDRAM chips, the actual data input / output to / from each SDRAM chip is in units of 8 bits. Therefore, in this embodiment using the ECC capable of correcting the data error of the 8-bit burst, even if one SDRAM chip fails, it is possible to correct the data error. In this embodiment, input / output in 16-bit width is possible
Although the SDRAM is used, it is also possible to use a DRAM capable of outputting half of the upper bits of data by CASU and half of the lower bits of data by CASL. Also, 16-bit input / output S that can be accessed in 8-bit units
Expanding the configuration that uses two DRAMs as a set, sets up multiple m-bit input / output storage elements that can be accessed in n-bit units, and shares m-bit data, enabling data error correction for n-bit bursts. It is also possible to use a possible ECC to correct a fault in a single memory element chip. Also, the number of redundant bits for performing error detection is smaller than the number of redundant bits for performing error correction. It can also be reduced.

[0018]

As described above, according to the present invention,
With a smaller number of redundant bits than the number of redundant bits originally required to correct a failure in one storage element chip,
It is possible to correct a chip failure.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional main memory configuration.

FIG. 2 is a diagram showing a masking operation of write and read data.

FIG. 3 is a diagram showing a configuration of a main storage device according to the embodiment of the present invention.

FIG. 4 is a diagram showing a data writing operation.

FIG. 5 is a diagram illustrating a data read operation.

[Explanation of symbols]

10 ... Memory controller, 20-49, 50, 60, 140-149,
220-229, 300-309: SDRAM chip, 100: Main memory control unit, 102: ECC generation circuit, 104: Error correction circuit, 105: ECC
Check circuit, 109: mask control circuit, 130: main storage unit.

Claims (4)

[Claims] 1. A main storage device comprising a plurality of storage elements having a mask control line for input / output data in units of n bits and a main storage control unit for controlling the main storage unit. , The main storage control unit has means for controlling a mask control line of each storage element of the main storage unit,
A main storage device, wherein data is input / output to / from the main storage unit by accessing a plurality of different storage elements in units of n bits. 2. The main memory control unit includes means for adding a redundant code to data input in a write access;
Means for controlling the mask control lines of a plurality of different storage elements, and outputting the data to the main storage unit by writing the redundant code-added data to the plurality of different storage elements in n-bit units. The main storage device according to claim 1. 3. The main memory control unit controls a mask control line of a plurality of different storage elements in a read access,
2. The main storage device according to claim 1, further comprising means for inputting data from the main storage unit by reading data with redundancy code from a plurality of different storage elements in n-bit units. 4. A main storage control unit comprising: means for reading data with a redundancy code from the main storage unit in a read access and for correcting a data error when a bit error of n bits or less occurs in target data. 2. The main storage device according to claim 1, wherein: