JP2002032144A5 - - Google Patents

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Publication number
JP2002032144A5
JP2002032144A5 JP2001129127A JP2001129127A JP2002032144A5 JP 2002032144 A5 JP2002032144 A5 JP 2002032144A5 JP 2001129127 A JP2001129127 A JP 2001129127A JP 2001129127 A JP2001129127 A JP 2001129127A JP 2002032144 A5 JP2002032144 A5 JP 2002032144A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2001129127A
Other versions
JP2002032144A (ja
JP4430836B2 (ja
Filing date
Publication date
Priority claimed from US09/562,043 external-priority patent/US6625559B1/en
Application filed filed Critical
Publication of JP2002032144A publication Critical patent/JP2002032144A/ja
Publication of JP2002032144A5 publication Critical patent/JP2002032144A5/ja
Application granted granted Critical
Publication of JP4430836B2 publication Critical patent/JP4430836B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2001129127A 2000-05-01 2001-04-26 クロックの停止中に位相ロック・ループ・フィードバックのロックを維持するためのシステム及び方法 Expired - Fee Related JP4430836B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/562,043 US6625559B1 (en) 2000-05-01 2000-05-01 System and method for maintaining lock of a phase locked loop feedback during clock halt
US09/562043 2000-05-01

Publications (3)

Publication Number Publication Date
JP2002032144A JP2002032144A (ja) 2002-01-31
JP2002032144A5 true JP2002032144A5 (ja) 2007-03-08
JP4430836B2 JP4430836B2 (ja) 2010-03-10

Family

ID=24244548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001129127A Expired - Fee Related JP4430836B2 (ja) 2000-05-01 2001-04-26 クロックの停止中に位相ロック・ループ・フィードバックのロックを維持するためのシステム及び方法

Country Status (4)

Country Link
US (1) US6625559B1 (ja)
EP (1) EP1152536B1 (ja)
JP (1) JP4430836B2 (ja)
DE (1) DE60101117T2 (ja)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6920572B2 (en) * 2000-11-15 2005-07-19 Texas Instruments Incorporated Unanimous voting for disabling of shared component clocking in a multicore DSP device
US6751743B1 (en) * 2000-12-22 2004-06-15 Cisco Technology, Inc. Method and apparatus for selecting a first clock and second clock for first and second devices respectively from an up-converted clock and an aligned clock for synchronization
US6810486B2 (en) * 2001-03-28 2004-10-26 Intel Corporation Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree
US6934898B1 (en) * 2001-11-30 2005-08-23 Koninklijke Philips Electronics N.V. Test circuit topology reconfiguration and utilization techniques
US6647081B2 (en) * 2001-12-12 2003-11-11 Emulex Corporation Phase-locked loop (PLL) circuit for selectively correcting clock skew in different modes
JP2007193751A (ja) * 2006-01-23 2007-08-02 Nec Electronics Corp 半導体装置およびデータ入出力システム
KR100791002B1 (ko) 2006-11-15 2008-01-03 삼성전자주식회사 락킹 범위를 극대화시키며 번-인 테스트할 수 있는 위상동기 회로 및 그 번-인 테스트 방법
US7856562B2 (en) * 2007-05-02 2010-12-21 Advanced Micro Devices, Inc. Selective deactivation of processor cores in multiple processor core systems
US20080313478A1 (en) * 2007-06-15 2008-12-18 Wong Kar Leong Mechanism to gate clock trunk and shut down clock source
JP5416279B2 (ja) * 2010-07-07 2014-02-12 株式会社アドバンテスト 試験装置および試験方法
US8994458B2 (en) 2011-11-08 2015-03-31 Qualcomm Incorporated Oscillator based frequency locked loop
US20180311139A1 (en) 2017-04-28 2018-11-01 L'oreal Hair-treatment compositions comprising a polyurethane latex polymer and cationic compound
CN116521613B (zh) * 2023-07-04 2023-08-25 南京启见半导体科技有限公司 超低延迟的时钟域切换数据传输系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4876446A (en) 1987-02-06 1989-10-24 Matsushita Electric Works, Ltd. Optical sensor with optical interconnection board
US5349587A (en) * 1992-03-26 1994-09-20 Northern Telecom Limited Multiple clock rate test apparatus for testing digital systems
US5517147A (en) 1994-11-17 1996-05-14 Unisys Corporation Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits
US5864564A (en) 1995-11-17 1999-01-26 Sun Microsystems, Inc. Control circuit for deterministic stopping of an integrated circuit internal clock
US5900757A (en) 1996-05-01 1999-05-04 Sun Microsystems, Inc. Clock stopping schemes for data buffer
CA2226061C (en) * 1997-12-31 2002-05-28 Logicvision, Inc. Method and apparatus for controlling power level during bist

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