JP2002031819A - Liquid crystal device, manufacturing method therefor, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal device with a high contrast ratio and a high aperture ratio by controlling deterioration in picture quality caused by disclination in a vertical alignment liquid crystal device. SOLUTION: In the liquid crystal device of this invention, a liquid crystal of a vertical alignment mode is held between a pair of substrates, and a TFT array substrate which is one of the pair of substrates is provided with a plurality of scanning lines 5 and data lines 4, TFTs 3 arranged correspondingly to the scanning lines 5 and the data lines 4, an interlayer insulating film arranged on the TFTs 3, pixel contact holes 14 formed in the interlayer insulating film, and pixel electrodes 2 electrically connected with a drain area 11 via the pixel contact holes 14. The pixel contact holes 14 are extended along the scanning lines 5 and capacitance lines 7 from the data lines 4 connected with the TFTs 3 up to the vicinity of the data lines 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device, a method of manufacturing the same, and an electronic apparatus, and more particularly to a structure of a liquid crystal device of a vertical alignment mode.

[0002]

2. Description of the Related Art An alignment mode of a liquid crystal device includes a horizontal alignment mode in which liquid crystal molecules are aligned in parallel with a substrate surface in a state where no voltage is applied, and a vertical alignment mode in which liquid crystal molecules are vertically aligned. Conventionally, the horizontal alignment mode has been the mainstream in terms of reliability and the like, but since the vertical alignment mode has some excellent characteristics, a vertical alignment type liquid crystal device has recently attracted attention.

For example, in the vertical alignment mode, a state in which liquid crystal molecules are arranged perpendicular to the substrate surface (no optical retardation as viewed from the normal direction) is used as a black display, so that the quality of the black display is low. Good and high contrast can be obtained. In addition, vertical alignment LCD with excellent front contrast
In this case, the viewing angle range in which a certain contrast is obtained is wider than that of a TN (Twisted Nematic) liquid crystal in a horizontal alignment mode. Furthermore, if a multi-domain technique for dividing the alignment state of the liquid crystal in the pixel into multiples is adopted, an extremely wide viewing angle can be obtained. In the vertical alignment type liquid crystal device, the response speed and the alignment control are more closely related to each other than the other liquid crystal display modes, and the obtained response speed differs greatly depending on the alignment state. , The response speed is greatly improved.

[0004]

While the vertical alignment type liquid crystal device has such advantages, it has the following problems. Generally, the vertical alignment mode has a characteristic that the alignment regulating force is weaker than the horizontal alignment mode. (The above-mentioned characteristic also causes the strong dependence of the response speed in the vertical alignment type liquid crystal device on the alignment state. it seems to do). Since the alignment control force is weak, the liquid crystal during voltage application easily transitions to various alignment directions easily, and an unstable domain structure is easily formed. Especially when the pretilt angle is small, the liquid crystal molecules all fall in a uniform direction from the standing state unless a horizontal electric field acts on the liquid crystal. For example, in the case of the dot inversion drive, the liquid crystal molecules fall from the outer peripheral portion of each side of the rectangular pixel toward the center thereof, and in the case of the line inversion drive, the liquid crystal molecules are electrically connected between the adjacent pixel electrodes. It tends to fall from the side with the polarity difference toward the center.

As a result of the liquid crystal molecules falling from the outer periphery to the center of each side of the pixel, a domain boundary is formed along a diagonal line of the rectangular pixel, and this portion is a region having a low transmittance, that is, a so-called disk. It becomes a ligation line. In other words, two diagonal disclination lines are formed at the center of the pixel. However, in the vertical alignment type liquid crystal device, the alignment control force is originally weak, and an unstable domain structure is easily formed. The above-described phenomenon that the disclination line at the center of the pixel fluctuates may occur due to a slight disturbance in the processing, a variation in the voltage application state at each time, or the like. If the disclination line is not so large, it does not cause a big problem as long as it always occurs at the same place, but the movement of the disclination line is recognized as flickering of the image to the user's eyes. There was a problem in point.

Further, when the area of the disclination line is large, there is a problem that the contrast of the screen is greatly reduced. Hitherto, various methods have been proposed to avoid image quality deterioration due to disclination.However, a method of hiding the area where disclination occurs by using a light shielding layer or the like reduces the aperture ratio and reduces the screen area. Brightness decreases. Therefore, it is desired to provide a means for suppressing a decrease in image quality due to disclination while securing a certain aperture ratio.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to suppress a decrease in image quality due to disclination in a vertical alignment type liquid crystal device, and achieve a high contrast ratio and a high aperture ratio. It is an object to provide a liquid crystal device.

[0008]

In order to achieve the above object, a liquid crystal device according to the present invention comprises a vertical alignment mode liquid crystal sandwiched between a pair of substrates. A plurality of scanning lines; a data line intersecting the plurality of scanning lines; a switching element arranged corresponding to the scanning line and the data line; an interlayer insulating film provided on a drain region of the switching element; A pixel contact hole formed in the insulating film; and a pixel electrode electrically connected to the drain region through the pixel contact hole. The pixel contact hole is connected to the switching element along the scan line. It is characterized in that it extends from a data line to the vicinity of a data line adjacent to the data line.

As described above, in the vertical alignment mode, the alignment regulating force of the liquid crystal is weak. Therefore, the liquid crystal tends to easily take various alignment directions depending on, for example, the unevenness of the alignment film and the direction of application of the electric field. By the way, looking at the configuration of the pixel in the liquid crystal device, the center of the pixel is relatively flat because only the pixel electrode and the interlayer insulating film are stacked, but the peripheral portion is provided with various wirings such as scanning lines and data lines. It is raised like a bank because it is formed. The pixel contact hole has a deeply concave shape so that the upper pixel electrode is electrically connected to the drain region of the lower switching element. In other words, in the case of a conventional general liquid crystal device, the pixel contact hole is usually designed to have a rectangular shape sufficiently smaller than the size of the pixel region, so that the pixel electrode in the pixel contact hole portion and, consequently, the alignment film are formed. It has an extremely locally depressed shape (in a device actually manufactured, the pixel contact hole is not a square but a circular conical shape). Therefore, the liquid crystal molecules standing in the vertical direction fall in various directions around the circular pixel contact hole when an electric field is applied, so that a domain structure in which the liquid crystal molecules are oriented in various directions is formed. Had a disclination.

As described above, the present inventor has paid attention to the fact that disclination occurs in the conventional vertical alignment type liquid crystal device due to the shape of the pixel contact hole. Therefore, the shape of the pixel contact hole is changed to an elongated shape extending from the vicinity of the data line connected to the switching element of the pixel to the vicinity of the adjacent data line along the scanning line. With such a shape, the alignment film in the pixel contact hole portion is elongated and recessed along one side of the pixel, so that the liquid crystal molecules fall down at the edge portion extending in the longitudinal direction of the pixel contact hole. Ruled. As a result, most of the liquid crystal molecules existing in the vicinity of the pixel contact hole tend to fall from one side on the side where the pixel contact hole is formed toward the center of a flat pixel. However, it is difficult to form domain structures oriented in various directions, and it is possible to suppress the occurrence of disclination. As a result, the image quality and the contrast ratio can be improved, and the aperture ratio can be improved by reducing the size of the light-shielding layer that hides unnecessary disclination.

In another liquid crystal device of the present invention, liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, and one of the pair of substrates intersects a plurality of scanning lines and a plurality of scanning lines. A data line, a switching element arranged corresponding to the scanning line and the data line, an interlayer insulating film provided on a drain region of the switching element, a pixel contact hole formed in the interlayer insulating film, and a pixel contact. A pixel electrode electrically connected to the drain region through the hole; and a storage capacitor. The storage capacitor includes one electrode extending from the drain region, and a gate insulating film provided on one electrode. And the other electrode formed of the same film as the scanning line, and the other electrode is arranged along the scanning line and closer to the center of the pixel electrode than the scanning line,
The region where the pixel contact hole is formed is located closer to the center of the pixel electrode than one of the electrodes, and the pixel contact hole extends along the scan line between the data line connected to the switching element and the data line. It is characterized by extending to the vicinity of an adjacent data line.

[0012] In another liquid crystal device according to the present invention, one electrode extending from the drain region of the switching element includes:
It has a storage capacitance which is arranged on one of the electrodes via a gate insulating film and which is composed of a scanning line and the other electrode (capacity line) of the same film. In this configuration, the scanning line, the other electrode of the storage capacitor, and the drain region where the pixel contact hole is formed are arranged in this order from the peripheral side to the central side of the pixel. Therefore, it is possible to realize a structure in which the peripheral portion of the pixel is high and the portion of the pixel contact hole is elongated and depressed along the scanning line. Ligation can be suppressed.

In another liquid crystal device of the present invention, liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, and one of the pair of substrates intersects a plurality of scanning lines and a plurality of scanning lines. A data line, a switching element corresponding to the scanning line and the data line, a first interlayer insulating film provided at least on a drain region of the switching element, and a conductive layer provided on the first interlayer insulating film. Barrier layer, a second interlayer insulating film provided on the barrier layer, a pixel electrode disposed on the second interlayer insulating film, and a pixel contact for electrically connecting the pixel electrode and the barrier layer And a drain contact hole for electrically connecting the barrier layer and the drain region, wherein the pixel contact hole is adjacent to the data line connected to the switching element along the scanning line and the data line. Characterized by comprising extends to the vicinity of that data line.

In the above-described liquid crystal device, the pixel electrode is directly connected to the drain region of the switching element. On the other hand, in the other liquid crystal device of the present invention, the pixel electrode and the drain region of the switching element are connected to the first interlayer. They are electrically connected via a barrier layer provided on the insulating film. With this structure, the depression in the pixel contact hole portion becomes shallower than the structure in which the pixel electrode is directly connected to the drain region due to the barrier layer interposed in the middle of the stacked structure, but it is still formed in the other portion of the pixel electrode. It is certain that the portion of the pixel contact hole is depressed in comparison. Therefore, also in this configuration, the pixel contact hole extends along the scanning line to the vicinity of the data line adjacent to the data line connected to the switching element. Can be suppressed.

In another liquid crystal device of the present invention, liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, and one of the pair of substrates intersects a plurality of scanning lines and a plurality of scanning lines. A data line, a switching element arranged corresponding to the scan line and the data line, a gate insulating film provided on one electrode of a drain region and a storage capacitor of the switching element, and provided on the gate insulating film. The other electrode of the gate electrode and the storage capacitor, a first interlayer insulating film provided on the gate electrode and the other electrode, a barrier layer provided on the first interlayer insulating film, and a barrier layer provided on the first interlayer insulating film. The second
An interlayer insulating film, a pixel electrode provided on the second interlayer insulating film, a pixel contact hole for electrically connecting the pixel electrode to the barrier layer, and an electrical connection between the barrier layer and the drain region. And a drain contact hole for the other electrode and the barrier layer, along the scanning line,
The pixel contact hole is disposed closer to the center of the pixel electrode than the scanning line, and the pixel contact hole extends along the scanning line to a vicinity of a data line connected to the switching element and a data line adjacent to the data line. It is characterized by becoming.

According to another aspect of the present invention, there is provided a liquid crystal device in which a barrier layer is interposed between a pixel electrode and a drain region. And the other electrode (capacitance line). In this configuration, the other electrode and the barrier layer are arranged along the scanning line on the center side of the pixel electrode with respect to the scanning line, the peripheral portion of the pixel is higher, and the portion of the pixel contact hole extends along the scanning line. An elongated concave structure can be realized. With this structure, disclination can be suppressed by controlling how the liquid crystal molecules fall near the pixel contact hole.

In the liquid crystal device of the present invention, the periphery of the pixel electrode is connected to the data line connected to the switching element of one pixel, the data line adjacent to the data line, and the switching element of the pixel. It is desirable to arrange the scanning line so as to overlap the scanning line adjacent to the scanning line in plan view.

As described above, the area where the wiring such as the data line and the scanning line is formed is higher than the central portion of the pixel electrode. As shown in FIG.
Of the four sides 2b, 2c, 2d, and 2e that form the periphery of the remaining three sides 2c, 2d, and 2e excluding one side 2b
Is formed on the peripheral portion of the pixel electrode 2 corresponding to
a is formed, and this portion is replaced with another portion (pixel electrode 2).
(Side 2b side and the center).

FIG. 23 shows equipotential lines when an electric field is applied between the pixel electrode 2 having such a shape and the common electrode 29 of the counter substrate 19. As shown in FIG.
The equipotential line is inclined at the peripheral portion having the convex portion 2a. In the case of the liquid crystal in the vertical alignment mode, when the equipotential lines are inclined at the peripheral edge of the pixel electrode 2, the liquid crystal molecules which tend to fall from the outside to the inside of the pixel at the peripheral edge of the pixel electrode 2. The power of is relaxed. On the other hand, only the portion along the side 2b of the pixel electrode is not formed with the convex portion 2a, so that the liquid crystal molecules fall over the other portion along the non-inclined equipotential lines over other portions. To try. As a result, first, the liquid crystal molecules in the peripheral portion along the side 2b start to be preferentially oriented, and the liquid crystal molecules in the other portions are subsequently oriented. Therefore, compared to the conventional pixel electrode having no convex portion. The alignment directions of the liquid crystals are easily aligned.

In addition, in the liquid crystal device of the present invention, since the elongated pixel contact holes extending along the scanning lines between the data lines are provided, as described above, the alignment control by the shape of the pixel contact holes is performed. The liquid crystal molecules in the vicinity of the pixel contact hole are combined with the liquid crystal molecules near the pixel contact hole on one side of the pixel without the convex portion, in combination with the effect and the alignment control effect provided by the convex portions on the three peripheral edges of the pixel electrode. Therefore, the tendency to fall toward the side opposite to this side becomes stronger, and disclination can be suppressed more reliably.

In another liquid crystal device of the present invention, liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, and one of the pair of substrates intersects a plurality of scanning lines and a plurality of scanning lines. A data line, a switching element corresponding to the scanning line and the data line, a first interlayer insulating film provided on a drain region of the switching element, and a barrier layer provided on the first interlayer insulating film And a second layer provided on the barrier layer.
An interlayer insulating film, a pixel electrode provided on the second interlayer insulating film, a pixel contact hole for electrically connecting the pixel electrode to the barrier layer, and an electrical connection between the barrier layer and the drain region. The pixel contact hole extends along the scanning line to the vicinity of the data line connected to the switching element and the data line adjacent to the data line. Each of the pixel electrodes has a rectangular shape, and the periphery of each of the three sides of the pixel electrode includes a data line connected to the switching element, a data line adjacent to the data line, and a scanning line adjacent to the scanning line connected to the switching element. Are arranged so as to overlap with each other when viewed two-dimensionally, the periphery of the remaining one side of the pixel electrode is arranged on the pixel contact hole, and the periphery of the three sides of the pixel electrode is Characterized in that it protrudes from the peripheral edge of the sides.

As described above, the other liquid crystal device of the present invention has an alignment control effect by the shape of the pixel contact hole and an alignment control by the three peripheral edges of the pixel electrode protruding from the remaining one side. Together with the effect, the tendency of the liquid crystal molecules in the vicinity of the pixel contact hole to fall from the peripheral side to the central side of the pixel becomes stronger, and disclination can be suppressed more reliably.

In the liquid crystal device according to the present invention, it is desirable that the taper angle of the pixel contact hole is set to be substantially the same as the desired pretilt angle of the liquid crystal.

With respect to the cross-sectional shape of the pixel contact hole, if the pixel contact hole is formed by using a highly anisotropic etching method such as dry etching, the inner wall of the hole will have a shape which is almost perpendicular to the substrate surface. When an isotropic etching method such as wet etching is used, the inner wall of the hole has a tapered shape opened upward. Normally, even in the liquid crystal in the vertical alignment mode, the liquid crystal molecules are not completely erected perpendicularly to the substrate surface, but are pretilted at a predetermined angle as in the horizontal alignment mode. Therefore, in the present invention, if the taper angle of the pixel contact hole (the angle of the inner wall surface of the hole with respect to the plane perpendicular to the substrate surface) is set to be substantially the same as the pretilt angle of the liquid crystal, the angle along the inner wall angle of the hole will increase. Thus, liquid crystal molecules can be aligned, and a desired pretilt angle can be obtained.

As described above, the periphery of the pixel is raised in a bank-like shape due to the formation of the scanning lines and the data lines, but by itself, all four sides of the periphery of the pixel are at the center. As a result, it is impossible to form a convex portion protruding only on three sides of the pixel peripheral portion as shown in FIG. Therefore, it is necessary to flatten only one side of the peripheral portion of the pixel together with the central portion of the pixel, or conversely, to depress the central portion of the pixel. The following three means can be considered for that.

The first means is a method in which a depression is formed in the substrate corresponding to the position of the pixel contact hole.
By forming a depression in advance on the substrate itself, wiring and the like laminated thereon can be embedded in the depression,
A structure as shown in FIG. 22 in which only one side of the pixel peripheral portion is flattened can be realized. By arranging the pixel contact holes at the positions of the depressions, it is possible to form the elongated groove-shaped pixel contact holes on the flat surface.

The second means is that the switching element is electrically connected to the data line via a source contact hole formed in the interlayer insulating film or the second interlayer insulating film, Is a method in which a second conductive layer made of is provided above the scanning line. In that case, it is desirable to previously planarize the surface of the interlayer insulating film or the second interlayer insulating film. That is, in this method, instead of embedding a wiring portion as in the first means, a data line and a conductive layer are formed using a film constituting a data line, and a portion serving as a bank is formed. That is, two parallel portions of the convex portion at the pixel peripheral portion can be formed by the data line, and the remaining one convex portion can be formed by the conductive layer provided on the scanning line. Therefore, it is preferable that the surface of the interlayer insulating film or the second interlayer insulating film is once flattened before forming the data line, since the data line and the conductive layer portion surely protrude from the flat surface.

The third means is to provide a light-shielding film in a region corresponding to the switching element on the substrate, provide a base insulating film on the light-shielding film, and arrange the switching element on the base insulating film. In this method, a depression is provided in the base insulating film so as to be thin in a region corresponding to the position of the pixel contact hole. Also in this case, similarly to the first means, a wiring or the like can be embedded in the depression provided in the base insulating film, and a structure as shown in FIG. 22 in which only one side of the pixel peripheral portion is flattened is realized. Can be.

Further, when the third means is adopted, another effect can be obtained in addition to the above-mentioned original effect.
That is, the underlying insulating film in the region where the pixel contact hole is formed is thinner, and this portion is also the region where the drain region of the switching element is arranged. Therefore, in this region, the light-shielding film and the drain region face each other via the thin base insulating film. In addition, if the light-shielding film located below the switching element is set in a floating state in terms of potential, the characteristics of the switching element are adversely affected. Therefore, the light-shielding film is usually fixed at a constant potential. Therefore, in this configuration, the light-shielding film and the drain region which face each other with the thin base insulating film interposed therebetween form a pair of electrodes, and a storage capacitor is formed in this portion. As a result, in addition to the original storage capacity, the storage capacity can be obtained in this portion, so that the occupation area of the entire storage capacity can be reduced.

According to the method of manufacturing a liquid crystal device of the present invention, a step of forming a depression on the surface of a substrate in accordance with the position of a pixel contact hole to be formed later, and a step of forming a semiconductor layer forming a part of a switching element on the substrate are performed. Forming, forming a gate insulating film covering the semiconductor layer, forming a plurality of scanning lines on the gate insulating film, and forming a source region and a drain region of the switching element in the semiconductor layer Forming a first interlayer insulating film covering the scanning lines and the switching elements; forming a plurality of data lines on the first interlayer insulating film; and forming a plurality of data lines on the first interlayer insulating film. Forming a second interlayer insulating film covering the plurality of data lines; and providing the switching element along a scanning line at a position corresponding to a drain region of the switching element. Forming a pixel contact hole extending to the vicinity of a data line connected to the data line and a data line adjacent to the data line, and electrically connected to a drain region of the switching element via the pixel contact hole. Forming a pixel electrode.

The method for manufacturing a liquid crystal device according to the present invention is a method for realizing the first of the three means for forming a U-shaped convex portion as shown in FIG. 22 on the pixel electrode. It is. According to this method, a U-shaped convex portion corresponding to three sides of the pixel electrode and an elongated groove-shaped pixel contact hole corresponding to the remaining one side can be formed, and disclination occurs. , A liquid crystal device with less noise can be provided.

According to another method of manufacturing a liquid crystal device of the present invention, a step of forming a depression on a surface of a substrate in accordance with a position of a pixel contact hole to be formed later, and a step of forming a semiconductor forming a part of a switching element on the substrate Forming a layer, forming a gate insulating film covering the semiconductor layer, forming a plurality of scanning lines on the gate insulating film, and forming a source region and a drain region of the switching element in the semiconductor layer. Forming a first interlayer insulating film covering the scanning line and the switching element; and forming the drain through the first interlayer insulating film at a position corresponding to a drain region of the switching element. Forming a drain contact hole reaching the region; and forming a drain contact hole on the first interlayer insulating film through the drain contact hole. A step of forming a barrier layer that is electrically connected, a step of forming a lower-layer-side second interlayer insulating film covering the barrier layer on the first interlayer insulating film, and a step of forming a lower-layer second interlayer insulating film on the lower-layer second interlayer insulating film. Forming a plurality of data lines, forming an upper second interlayer insulating film covering the plurality of data lines on the lower second interlayer insulating film, and a position corresponding to a drain region of the switching element Forming a pixel line along the scanning line and a pixel contact hole extending to the vicinity of a data line connected to the switching element and a data line adjacent to the data line; and forming the pixel contact hole through the pixel contact hole. Forming a pixel electrode electrically connected to the barrier layer.

The method of manufacturing a liquid crystal device according to the present invention is also a method for realizing the first means. In particular, the method of manufacturing a liquid crystal device having a barrier layer interposed between a drain region of a switching element and a pixel electrode is provided. It is a manufacturing method. Also in this method, a liquid crystal device with less disclination can be provided.

According to another method of manufacturing a liquid crystal device of the present invention, a step of forming a semiconductor layer forming a part of a switching element on a substrate; a step of forming a gate insulating film covering the semiconductor layer; Forming a plurality of scanning lines on a film; forming source and drain regions of the switching element in the semiconductor layer; and forming a first interlayer insulating film covering the scanning line and the switching element. Forming a plurality of data lines on the first interlayer insulating film and forming a conductive layer along the scanning lines; and forming the plurality of data lines and the conductive layer on the first interlayer insulating film. Forming a covering second interlayer insulating film; and forming a data line connected to the switching element along the scanning line at a position corresponding to a drain region of the switching element. Forming a pixel contact hole extending to the vicinity of the data line adjacent to the data line; and forming a pixel electrode electrically connected to the drain region of the switching element via the pixel contact hole. It is characterized by having.

According to another method for manufacturing a liquid crystal device of the present invention,
This is a method for realizing the second means among the three means for forming the U-shaped convex portion shown in FIG. 22 on the pixel electrode. According to this method, a U-shaped convex portion corresponding to three sides of the pixel electrode and an elongated groove-shaped pixel contact hole corresponding to the remaining one side can be formed, and disclination occurs. , A liquid crystal device with less noise can be provided.

According to another method of manufacturing a liquid crystal device of the present invention, a step of forming a semiconductor layer forming a part of a switching element on a substrate; a step of forming a gate insulating film covering the semiconductor layer; Forming a plurality of scanning lines on a film; forming source and drain regions of the switching element in the semiconductor layer; and forming a first interlayer insulating film covering the scanning line and the switching element. Forming a drain contact hole reaching the drain region through the first interlayer insulating film at a position corresponding to the drain region of the switching element; and forming the drain contact hole on the first interlayer insulating film. Forming a barrier layer electrically connected to the drain region through the first interlayer insulating film; and covering the barrier layer on the first interlayer insulating film. Forming a layer side second interlayer insulating film, forming a plurality of data lines on the lower layer side second interlayer insulating film, and forming a conductive layer along the scanning lines; Forming an upper-layer-side second interlayer insulating film covering the plurality of data lines and the conductive layer on the interlayer insulating film; and performing the switching along the scanning line at a position corresponding to a drain region of the switching element. Forming a data line connected to the element and a pixel contact hole extending to the vicinity of the data line adjacent to the data line; and a pixel electrode electrically connected to the barrier layer via the pixel contact hole. And a step of forming

The method of manufacturing a liquid crystal device according to the present invention is also a method for realizing the second means. In particular, the method of manufacturing a liquid crystal device having a conductive layer interposed between a drain region of a switching element and a pixel electrode is provided. It is a manufacturing method. Also in this method, a liquid crystal device with less disclination can be provided.

In the method of manufacturing a liquid crystal device according to the present invention, after the surface of the first interlayer insulating film or the lower second interlayer insulating film is flattened, the flattened first interlayer insulating film or the lower layer side is removed. It is desirable to form a conductive layer on the second interlayer insulating film. With this configuration, it is possible to form a shape in which the data line and the second conductive layer portion protrude from the flat surface without fail.

According to another method of manufacturing a liquid crystal device of the present invention, a step of forming a light shielding film in a partial region on a substrate on which a switching element is to be formed later, and a base insulating film covering the light shielding film on the substrate Forming a thin film of the underlying insulating film in a region where a pixel contact hole is to be formed later; forming a semiconductor layer forming a part of a switching element on the underlying insulating film; Forming a gate insulating film covering the semiconductor device, forming a plurality of scanning lines on the gate insulating film, and forming a source region and a drain region of the switching element in the semiconductor layer;
Forming a first interlayer insulating film covering the scanning lines and the switching elements; forming a plurality of data lines on the first interlayer insulating film; and forming the plurality of data lines on the first interlayer insulating film. Forming a second interlayer insulating film covering the line, and, at a position corresponding to the drain region of the switching element, a data line connected to the switching element and data adjacent to the data line along the scanning line. Forming a pixel contact hole extending to the vicinity of the line; and forming a pixel electrode electrically connected to the drain region of the switching element through the pixel contact hole. .

According to another method for manufacturing a liquid crystal device of the present invention,
This is a method for realizing the third means among the three means for forming the convex portion having the U-shape in plan view shown in FIG. 22 on the pixel electrode. According to this method, a U-shaped convex portion corresponding to three sides of the pixel electrode and an elongated groove-shaped pixel contact hole corresponding to the remaining one side can be formed, and disclination occurs. , A liquid crystal device with less noise can be provided.

According to another method of manufacturing a liquid crystal device of the present invention, a step of forming a light shielding film in a partial region on a substrate on which a switching element is to be formed later, and a base insulating film covering the light shielding film on the substrate Forming a thin film of the underlying insulating film in a region where a pixel contact hole is to be formed later; forming a semiconductor layer forming a part of a switching element on the underlying insulating film; Forming a gate insulating film covering the semiconductor device, forming a plurality of scanning lines on the gate insulating film, and forming a source region and a drain region of the switching element in the semiconductor layer;
Forming a first interlayer insulating film covering the scanning line and the switching element; and forming a drain contact hole reaching the drain region through the first interlayer insulating film at a position corresponding to a drain region of the switching element. Forming, forming a barrier layer electrically connected to the drain region via the drain contact hole on the first interlayer insulating film, and forming the barrier layer on the first interlayer insulating film. Forming a lower second interlayer insulating film to cover, forming a plurality of data lines on the lower second interlayer insulating film, forming the plurality of data lines on the lower second interlayer insulating film; Forming an upper-layer-side second interlayer insulating film to cover, and connecting to the switching element along the scanning line at a position corresponding to a drain region of the switching element. Forming a pixel contact hole extending to the vicinity of a data line and a data line adjacent to the data line, and forming a pixel electrode electrically connected to the barrier layer through the pixel contact hole. And characterized in that:

The method of manufacturing a liquid crystal device according to the present invention is also a method for realizing the third means. In particular, the method of manufacturing a liquid crystal device having a barrier layer interposed between a drain region of a switching element and a pixel electrode is described. It is a manufacturing method. Also in this method, a liquid crystal device with less disclination can be provided.

An electronic apparatus according to the present invention includes the liquid crystal device according to the present invention. The electronic device of the present invention includes the liquid crystal device of the present invention,
There is little degradation in image quality due to disclination,
An image display unit having a high contrast ratio and a high aperture ratio can be realized.

[0044]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A liquid crystal device according to a first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of a liquid crystal device. FIG. 2 shows a TF forming one of a pair of substrates constituting a liquid crystal device.
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on a T array substrate,
FIG. 3 is a sectional view taken along line AA ′ of FIG. Note that the equivalent circuit diagram of FIG. 1 is common to all the liquid crystal devices in the following embodiments. In all the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

As shown in FIG. 1, in the liquid crystal device of the present embodiment, a plurality of pixels 1 formed in a matrix forming an image display area include a pixel electrode 2 and the pixel electrode 2.
Thin Film Transi
stor, hereinafter abbreviated as TFT, switching element) 3
Are formed in a matrix, and a data line 4 for supplying an image signal is electrically connected to a source region of the TFT 3. The image signal S1 to be written to the data line 4,
S2,..., Sn may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 4 for each group. Further, the scanning line 5 is electrically connected to the gate of the TFT 3, and the scanning signals G1 and G are pulsed to the scanning line 5 at a predetermined timing.
, Gm are applied line-sequentially in this order. The pixel electrode 2 is electrically connected to the drain region of the TFT 3 and has a switching element TF
By closing the switch for a certain period of time T3,
The image signals S1, S2,..., S supplied from the data lines 4
n is written at a predetermined timing.

The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrode 2 are exchanged with a common electrode (to be described later) formed on a counter substrate (to be described later) for a certain period of time. Will be retained. Here, in order to prevent the held image signal from leaking, a storage capacitor 6 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 2 and the common electrode. For example, the voltage of the pixel electrode 2 is held by the storage capacitor 6 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and a liquid crystal device having a high contrast ratio can be realized. In the present embodiment, a capacitance line 7 which is a wiring for forming the storage capacitance 6 is used.
Is provided. Instead of providing the capacitor line 7, a storage capacitor may be formed between the pixel electrode 2 and the preceding scanning line 5.

FIG. 2 is a plan view showing a pattern layout of a TFT array substrate which is one of the substrates constituting the liquid crystal device of the present embodiment. As shown in this figure, the TFT
Indium tin oxide (Indium Tin O)
A plurality of pixel electrodes 2 (contours are indicated by dotted lines) made of a transparent conductive film such as xide (hereinafter abbreviated as ITO) are arranged in a matrix, and along the sides of the pixel electrodes 2 extending in the vertical direction on the paper surface. A data line 4 (contour is shown by a solid line) is provided, and a scanning line 5 and a capacitor line 7 (both are shown by a solid line) are provided along a side extending in the lateral direction of the paper.

In this embodiment, the semiconductor layer 9 made of a polysilicon film (the outline is shown by a broken line) is
In FIG. 2, the lower side of the scanning line 5 is disposed on the source region 10 of the TFT 3, the upper side thereof is the drain region 11, and the lower side of the scanning line 5 is the channel region 12 (right side). It is a part with a downward diagonal line). Note that in the TFT 3 of the present embodiment, the scanning line 5 functions as a gate electrode as it is. The semiconductor layer 9 has one end on the drain region 11 side in the direction of the data line 4 of the pixel 1 adjacent to the pixel 1 (right direction on the paper) and the direction along the data line 4 of the pixel 1 (upward in the paper). The branch extends.

On the source region 10 of the semiconductor layer 9, a source contact hole 13 for electrically connecting the data line 4 and the source region 10 is formed. On the other hand, on the drain region 11 of the semiconductor layer 9, a pixel contact hole 14 (hatched portion in FIG. 2) for electrically connecting the pixel electrode 2 and the drain region 11 is formed. The shape and the formation position of the pixel contact hole 14 are one feature of the present invention. The data line connected to the TFT 3 of the pixel 1 is located at a position closer to the center of the pixel 1 than the capacitance line 7 of the pixel 1. 4 is formed so as to extend along the scanning line 5 and the capacitance line 7 from the vicinity of the adjacent data line 4 to the vicinity of the adjacent data line 4.

Further, as shown in FIG. 2, the peripheral portion of the pixel electrode 2 at least partially overlaps the wiring such as the data line 4, the scanning line 5, and the capacitance line 7 in plan. That is, the side extending in the horizontal direction on the paper above the pixel electrode 2 overlaps the scanning line 5 of the adjacent pixel 1, the side extending in the vertical direction on the left of the pixel electrode 2 overlaps the data line 4 of the own pixel 1, The side extending in the vertical direction on the right side of the pixel electrode 2 is adjacent to the pixel 1
And the side extending below the pixel electrode 2 in the horizontal direction of the drawing overlaps with the capacitance line 7 of the pixel 1 itself.
Therefore, in the case of the present embodiment, as shown in FIG.
The center of the pixel electrode 2 is a flat light-transmitting region, and the periphery of the pixel electrode 2 in a rectangular shape in plan view along the four sides is a convex portion 2a that runs on each of the wirings and protrudes in a bank shape. I have.
However, since the above-described pixel contact hole 14 is formed near the pixel center of the capacitance line 7 along the lower side of the pixel electrode 2, this portion has a deeply concave shape.

The capacitance line 7 extends along the scanning line 5 so as to penetrate the pixels 1 arranged in the horizontal direction on the paper, and the branched part 7a extends along the data line 4 in the vertical direction on the paper. Therefore, the semiconductor layer 9 and the capacitor line 7 which extend long along the data line 4 and the scanning line 5 and are overlapped in a plane.
Form a storage capacitor 6.

As shown in FIG. 3, the liquid crystal device according to the present embodiment has a pair of substrates 16 and 17, one of which is a TFT array substrate 18 and the other is disposed to face the other. And an opposing substrate 19 serving as a substrate. A liquid crystal 20 is sandwiched between the substrates 18 and 19. Substrate 1
Reference numerals 6 and 17 are made of, for example, a transparent substrate such as glass or quartz, or a silicon substrate.

As shown in FIG. 3, the TFT array substrate 18
A first light-shielding layer 21 made of a metal film of, for example, chromium is provided thereon corresponding to the position where the TFT 3 is formed, and a base insulating film 22 made of a silicon oxide film or the like is provided thereon. The first light-shielding layer 21 is for preventing return light of incident light to the liquid crystal device from being incident on the TFT 3, and the underlying insulating film 22 is for electrically connecting the first light-shielding layer 21 and the semiconductor layer 9 of the TFT 3. This is for preventing a short circuit. And
On the base insulating film 22, a TFT 3 for controlling switching of each pixel electrode 2 is provided. Specifically, a semiconductor layer 9 made of, for example, a polysilicon film having a thickness of about 50 nm is provided on the base insulating film 22, and a gate insulating film 23 having a thickness of about 10 to 150 nm is formed so as to cover the semiconductor layer 9. Have been.

The TFT 3 includes, for example, a scanning line 5 including a gate electrode made of a polysilicon film, a channel region 12 of a semiconductor layer 9 in which a channel is formed by an electric field from the scanning line 5, and the scanning line 5 and the semiconductor layer 9. A gate insulating film 23 to be insulated, a data line 4 made of a metal such as aluminum, and a high-concentration source region 10a forming a source region 10 of the semiconductor layer 9
And high-concentration drain region 11 forming drain region 11
a. Further, the TFT 3 according to the present embodiment has L
A DD (Lightly Doped Drain) structure is adopted, and the high concentration regions 10 of the source region 10 and the drain region 11 are formed.
a, 11a and the channel region 12
b, 11b are formed.

A storage capacitor electrode 24 (one electrode) integral with the drain region 11 of the TFT 3 is disposed on the base insulating film 22, and a scanning line is disposed on the storage capacitor electrode 24 via the gate insulating film 23. Capacitance line 7 formed of the same film as 5
(The other electrode). Then, a first interlayer insulating film 25 is formed so as to cover the TFT 3 and the storage capacitor 6.
5, a first interlayer insulating film 25 and a gate insulating film 23
Through the source contact hole 13 penetrating the TFT
A data line 4 electrically connected to the third source region 10 is formed.

Then, a second interlayer insulating film 26 is formed on the first interlayer insulating film 25 so as to cover the data lines 4. On the second interlayer insulating film 26, the second interlayer insulating film 26 and the first interlayer insulating film 26 are formed. The pixel electrode 2 is formed which is electrically connected to the drain region 11 of the TFT 3 through the pixel contact hole 14 having a depth penetrating the insulating film 25 and the gate insulating film 23. Further, an alignment film 27 is formed on the entire upper surface of the TFT array substrate 18. The alignment film 27 is, for example, an organic thin film to which a vertical alignment mode can be applied, such as a polyimide thin film.
1210 (trade name, manufactured by Merck Japan Ltd.) or the like can be used, and the alignment film may be subjected to a rubbing treatment.

On the other hand, the opposite substrate 19 side
A second light-shielding layer 28 made of, for example, a metal film of chromium or the like, a resin black resist, or the like is formed at a position where the first light-shielding layer 21 is formed on the TFT array substrate 18. The second light shielding layer 28 is for preventing light incident on the liquid crystal device from being incident on the TFT 3. Then, on the entire surface of the substrate 17, a common electrode 29 and an alignment film 30 made of a transparent conductive film such as ITO similar to the pixel electrode 2 are sequentially formed. This alignment film 30 may be made of the same material as that of the TFT array substrate 19.

In the present embodiment, the liquid crystal molecules 20 of the liquid crystal 20 stand with their major axes perpendicular to the substrates 16 and 17 in a state where no electric field is applied.
When an electric field is applied between the common electrodes 29, the substrate 1
A liquid crystal of a vertical alignment mode of a type which is oriented so as to be parallel to 6, 17 is selected. However, when a pretilt angle is introduced into the liquid crystal, the liquid crystal is not completely vertically aligned with the substrate but is oriented with a certain inclination with respect to a line (normal) perpendicular to the substrate surface. Examples of such a vertical alignment mode liquid crystal include a nematic liquid crystal having a negative dielectric anisotropy, a cholesteric liquid crystal, and the like.

In the liquid crystal device of the present embodiment, TF
As shown in FIG. 2, the shape of the pixel contact hole 14 in the T array substrate 18 is changed to the scanning line 5 and the capacitor line 7.
Along the line from the vicinity of the data line 4 of the pixel 1 to the vicinity of the adjacent data line 4,
The alignment film 27 in the portion of the pixel contact hole 14 is
Is elongated along one side. As a result, most of the liquid crystal molecules existing in the vicinity of the pixel contact hole 14 tend to fall from one side on which the pixel contact hole 14 is formed toward the center of the substantially flat pixel 1. However, it is difficult to form domain structures oriented in various directions, and it is possible to suppress the occurrence of disclination as compared with the related art. As a result, the image quality and the contrast ratio can be improved, and the aperture ratio can be improved by reducing the size of the light-shielding layer that hides unnecessary disclination.

The liquid crystal device of the present embodiment is suitable when 1H inversion driving is used as a driving method. The 1H inversion is a driving method in which a voltage of opposite polarity is applied to each adjacent scanning line 5. When this driving method is adopted, an electric field is generated in the horizontal direction between the adjacent scanning lines 5. In the liquid crystal device of the present embodiment, the liquid crystal molecules tend to fall from one side to the center of the pixel where the pixel contact hole 14 is formed along the electric field, so that the domain structure is less likely to be formed. Thus, occurrence of disclination can be suppressed.

Further, the configuration of the present embodiment has an advantage that the manufacturing process does not need to be changed from the conventional one because only the position and the shape of the pixel contact hole 14 are changed.

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described.
The liquid crystal device according to the embodiment will be described with reference to FIGS. FIG. 5 shows a TFT of the liquid crystal device of the present embodiment.
FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on the array substrate, and FIG. 6 is a sectional view taken along line BB ′ of FIG.

As shown in FIGS. 5 and 6, the structure of the TFT array substrate 18 of the present embodiment is basically the same as that of the TFT array substrate 18 of the first embodiment shown in FIGS. Similar. Therefore, in FIGS. 5 and 6, the same reference numerals are given to the same components as those in FIGS. 2 and 3, and detailed description of those portions will be omitted. The difference between the TFT array substrate 18 of the present embodiment and the TFT array substrate 18 of the first embodiment is that the TFT array substrate 18 of the first embodiment is different from the TFT array substrate 18 of the first embodiment.
In this embodiment, the drain region and the pixel electrode are electrically connected via another conductive layer (barrier layer), while the drain region is directly connected to the pixel electrode. Accordingly, the configuration of the contact hole is also different.

That is, as shown in FIG. 5, a portion of the semiconductor layer 9 of the TFT 3 which overlaps the drain region 11 in a plane and also overlaps the capacitor line 7 is provided with a conductive barrier layer 32 (a conductive layer, (A portion indicated by oblique lines). The barrier layer 32 is formed on the drain region 11 of the TFT 3.
And a pixel electrode 2 are electrically connected to each other, and serve as a relay layer. Due to the presence of the barrier layer 32, the deep pixel contact hole 1 as shown in the first embodiment (FIG. 3) is formed.
This eliminates the need to form the semiconductor layer 9, thereby avoiding problems such as penetration of the semiconductor layer 9 due to etching when forming the deep pixel contact hole 14.

A drain contact hole 33 for electrically connecting the drain region 11 of the TFT 3 and the barrier layer 32 is formed at the center of the peripheral portion along the lower side of the pixel electrode 2 in FIG. The drain contact hole 33 is disposed between the scanning line 5 and the capacitance line 7.
A portion of the capacitance line 7 is cut out so as not to short-circuit with the drain line 2, and a drain contact hole 33 is arranged in the cutout 7 b. The pixel contact hole 34 is provided so as to overlap the drain region 11, the capacitor line 7, and the barrier layer 32 extending in the horizontal direction of the paper in a plan view. Also in the case of the present embodiment, the pixel contact hole 34
Extend in the direction along the scanning line 5 and the capacitance line 7 and extend long to the vicinity of two data lines 4 adjacent to each other.

In the present embodiment, as in the first embodiment, as shown in FIG. 4, the center of the pixel electrode 2 is a flat light transmitting area, and the periphery along the four sides of the pixel electrode 2 The portion is a bank-shaped high convex portion 2a, and the portion of the pixel contact hole 34 along the lower side of the pixel electrode 2 has a concave shape.

The sectional structure shown in FIG. 6 is almost the same as that of the first embodiment shown in FIG. The difference is that a first interlayer insulating film 25 is formed so as to cover the TFT 3 and the storage capacitor 6, and the first interlayer insulating film 25 is formed on the first interlayer insulating film 25.
And a barrier layer 32 electrically connected to the drain region 11 of the TFT 3 through a drain contact hole 33 penetrating the gate insulating film 23. Further, a lower second interlayer insulating film 26a is formed on the first interlayer insulating film 25 so as to cover the barrier layer 32, and the lower second interlayer insulating film 26a is formed on the lower second interlayer insulating film 26a.
The data line 4 electrically connected to the source region 10 of the TFT 3 is formed through the source contact hole 13 penetrating the first interlayer insulating film 25 and the gate insulating film 23.

Then, an upper second interlayer insulating film 26b is formed on the lower second interlayer insulating film 26a so as to cover the data lines 4, and an upper second interlayer insulating film 26b is formed on the upper second interlayer insulating film 26b. Interlayer insulating film 26b and lower second interlayer insulating film 26
The pixel electrode 2 is formed which is electrically connected to the barrier layer 32 through the pixel contact hole 34 penetrating a. In the second embodiment, the pixel contact hole 34 can be provided in a region where the barrier layer 32 does not overlap with the data line. Therefore, the width of the pixel contact hole 34 is larger than that of the first embodiment. The taper angle of the pixel contact hole 34 is set substantially equal to the desired pretilt angle of the liquid crystal. Thereby, the convex portion 2a having a high bank-like shape can be efficiently formed without reducing the light transmission area.
And the pixel contact hole 34 can be advantageously formed.

Next, a method of manufacturing the liquid crystal device according to the present embodiment, in particular, a method of manufacturing a TFT array substrate will be described with reference to FIGS. FIGS. 7 to 13 are process diagrams showing each layer on the TFT array substrate 31 side in each process corresponding to the BB ′ cross section of FIG. 5 as in FIG.

First, as shown in step (1) of FIG. 7, a substrate 16 such as a quartz substrate, hard glass, or silicon substrate is prepared. Then, Ti, Cr, W, T
a, a metal such as Mo, or a metal alloy film such as a metal silicide,
A film thickness of about 100 to 500 nm by sputtering,
Preferably, it is formed as a light-shielding film 36 having a thickness of about 200 nm. Note that an anti-reflection film such as a polysilicon film may be formed on the light-shielding film 36 to reduce surface reflection.

Next, as shown in step (2), a resist mask (not shown) corresponding to the pattern of the first light shielding layer 21 is formed on the formed light shielding film 36 by photolithography.
The first light-shielding layer 21 is formed by etching the light-shielding film 36 via a resist mask.

Next, as shown in step (3), a silicate glass film such as NSG, PSG, BSG, BPSG or the like, or silicon nitride is formed on the first light shielding layer 21 by, for example, normal pressure or low pressure CVD. A base insulating film 22 made of a film, a silicon oxide film, or the like is formed. The thickness of the base insulating film 22 is, for example, about 500 to 2000 nm.
In the case where the return light from the rear surface of the TFT array substrate 31 does not matter, the first light shielding layer 21 does not need to be formed.

Next, as shown in step (4), an amorphous silicon film is formed on the base insulating film 22 by a low pressure CVD method or the like. Then, in a nitrogen atmosphere, about 600 to 7
By performing a heat treatment at 00 ° C. for about 1 to 10 hours,
The polysilicon film 37 is solid-phase grown to a thickness of about 50 to 200 nm. As a method for solid phase growth, R
Heat treatment using TA (Rapid Thermal Anneal) may be used, or excimer laser or the like may be used. Note that a polysilicon film may be directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Alternatively, decompression CV
A polysilicon film may be formed by implanting silicon ions into the polysilicon film deposited by the method D or the like to make it amorphous once, and then recrystallizing it by heat treatment or the like.

Next, as shown in step (5), the polysilicon layer 37 is patterned by a photolithography step and an etching step to form a semiconductor layer 9 having a predetermined pattern. At this time, the storage capacitor electrode 24 integral with the semiconductor layer 9 is simultaneously formed in the same pattern.

Next, as shown in step (6) of FIG.
By thermally oxidizing the semiconductor layer 9 constituting T3 at a temperature of about 900 to 1300 ° C., a relatively thin thermally oxidized silicon film 38 of about 30 nm is formed. Further, as shown in step (7). Then, an insulating film 39 made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively thin film thickness of about 50 nm by a low pressure CVD method or the like to form the gate insulating film 23 of the TFT 3 having a multilayer structure. . As a result, the thickness of the gate insulating film 23 is about 10 to 150 n.
m.

Next, as shown in step (8), the storage capacitor electrode 2 is formed by a photolithography step and an etching step.
A resist mask 40 is formed on the semiconductor layer 9 except for the portion that becomes 4.
Is formed, for example, phosphorus (P) ions are introduced at a dose of about 3
The resistance of the storage capacitor electrode 24 may be reduced by doping at × 10 ¹² / cm ² . In that case, after ion implantation, the resist mask 40 is removed.

Next, as shown in step (9), low pressure CVD
A polysilicon film 41 is deposited by a method or the like, and phosphorus (P) is thermally diffused to make the polysilicon film 41 conductive.
Alternatively, P ions may be introduced simultaneously with the formation of the polysilicon film. The thickness of the polysilicon film 41 is about 100 to
Deposit at 500 nm, preferably about 300 nm.

Next, as shown in step (10) of FIG. 9, the polysilicon film 41 is patterned by a photolithography step using a resist mask (not shown), an etching step, etc. And the capacitance line 7 is formed. The scanning lines 5 and the capacitance lines 7 may be formed of a metal alloy film such as a refractory metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like.

Next, as shown in step (11), the TFT 3
Is an n-channel TFT having an LDD structure,
First, in order to form a low-concentration source region 10b and a low-concentration drain region 11b in the semiconductor layer 9, an impurity of a group V element such as P is doped at a low concentration using a gate electrode that is a part of the scanning line 5 as a mask ( for example, P ions 1 × ^{10 1 3}
に て 3 × 10 ¹³ / cm ^{2 at} a dose).
As a result, the semiconductor layer 9 below the scanning line 5 becomes the channel region 12.
Becomes

Next, as shown in step (12), the TFT 3
After forming a resist mask 42 wider than the scanning line 5 on the scanning line 5 in order to form the high concentration source region 10a and the high concentration drain region 11a, (For example, P ions are doped at a dose of 1 × 10 ^{15 to} 3 × 10 ¹⁵ / cm ² ). It is to be noted that, for example, a TFT having an offset structure may be used without doping a low-concentration impurity.
A self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like, using a gate electrode that is a part of the scanning line 5 as a mask.

Next, as shown in step (13) of FIG.
After removing the resist mask 42, a high-temperature silicon oxide film (HTO film) is formed on the scanning lines 5, the capacitance lines 7, and the gate insulating film 23 by a low pressure CVD method, a plasma CVD method, or the like.
And a first interlayer insulating film 25 made of a silicon nitride film.
It is deposited to a relatively thin film thickness of about 200 nm. However,
The first interlayer insulating film 25 may be composed of a multilayer film,
The first interlayer insulating film can be formed by various known techniques generally used to form a gate insulating film of a TFT.

Next, as shown in step (14), a drain contact hole 33 for electrically connecting a barrier layer 32 to be formed later and the high-concentration drain region 11a is formed.
It is formed by dry etching such as reactive ion etching and reactive ion beam etching. Since such dry etching has high directivity, a contact hole having a small diameter can be formed. Alternatively, wet etching which is advantageous for preventing the contact hole from penetrating through the semiconductor layer may be used together. This wet etching is also effective from the viewpoint of providing a taper for better electrical connection to the contact hole.

Next, as shown in a step (15), Ti, C is formed on the entire surface of the high-concentration drain region 11a viewed through the first interlayer insulating film 25 and the drain contact hole 33.
A metal such as r, W, Ta, Mo, or a metal alloy film such as a metal silicide is deposited by sputtering, and 50 to 500
A conductive film 43 having a thickness of about nm is formed. Note that an anti-reflection film such as a polysilicon film may be formed on the conductive film 43 to reduce surface reflection, and may be composed of two or more layers. Further, as the conductive film 43, a polysilicon film or the like may be used for stress relaxation, or two or more conductive films 43 may be formed using a polysilicon film and a metal alloy film.

Next, as shown in step (16) of FIG.
A resist mask (not shown) corresponding to the pattern of the barrier layer 32 is formed on the formed conductive film 43 by photolithography, and the conductive film 43 is formed via the resist mask.
The barrier layer 32 is formed by performing the above etching.

Next, as shown in step (17), a lower second interlayer insulating film 26a is formed to cover the first interlayer insulating film 25 and the barrier layer 32 by, for example, normal pressure or low pressure CVD. I do. The thickness of the lower second interlayer insulating film 26a is preferably about 500 to 1500 nm. If the thickness of the lower-layer-side second interlayer insulating film 26a is 500 nm or more, the parasitic capacitance between the data line 4 and the scanning line 5 does not matter much.

Next, as shown in step (18), a heat treatment at about 1000 ° C. is performed for about 20 minutes to activate the high-concentration source region 10a and the high-concentration drain region 11a. A hole 13 is opened. Also, a contact hole for connecting the scanning line 5 and the capacitor line 7 to a wiring (not shown) in the peripheral region of the substrate can be formed in the lower second interlayer insulating film 26a by the same process as the source contact hole 13. .

Next, as shown in step (19) of FIG.
A low-resistance metal such as Al or a metal silicide, such as Al, which is light-shielding by sputtering or the like as a metal film 44 on the lower-layer-side second interlayer insulating film 26a, and has a thickness of about 100 to 1000 nm, preferably about 500 nm. Deposited on

Next, as shown in a step (20), a metal film 44 is formed by a photolithography step, an etching step, or the like.
Is patterned to form the data lines 4.

Next, as shown in step (21), an upper second interlayer insulating film 26b is formed so as to cover the data lines 4 by using, for example, normal pressure or reduced pressure CVD or plasma CVD. The thickness of the upper-layer second interlayer insulating film 26b is preferably about 500 to 1500 nm.

Next, as shown in step (22) of FIG.
A pixel contact hole 34 for penetrating the upper second interlayer insulating film 26b and the lower second interlayer insulating film 26a to electrically connect the pixel electrode 2 to be formed next and the barrier layer 32 is formed by reactive ion It is formed by dry etching such as etching and reactive ion beam etching. Here, wet etching is used together to make the shape of the contact hole tapered.

Next, as shown in a step (23), an IT layer is formed on the upper second interlayer insulating film 26b by sputtering or the like.
A transparent conductive film 45 such as an O film is deposited to a thickness of about 50 to 200 nm, and as shown in a step (24), a transparent conductive film 4 is formed by a photolithography step, an etching step, or the like.
5 is patterned to form a pixel electrode 2. When the liquid crystal device is used for a reflection type liquid crystal device, Al
The pixel electrode may be formed from an opaque material having a high reflectivity such as. Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 2, a rubbing process is performed in a predetermined direction so as to have a predetermined pretilt angle, and the like, thereby forming an alignment film 27. Through the above steps, the TFT array substrate 18 is completed.

On the other hand, although a process diagram is not shown for the counter substrate, a substrate 17 such as a glass substrate is first prepared.
The second light-shielding layer 28 is formed through a photolithography step and an etching step after sputtering metal chromium, for example. The second light shielding layer 28 is made of Cr, Ni,
In addition to a metal material such as Al, it may be formed from a material such as resin black in which carbon or Ti is dispersed in a photoresist. Next, the common electrode 29 is formed by depositing a transparent conductive film such as ITO to a thickness of about 50 to 200 nm on the entire surface of the counter substrate 19 by sputtering or the like. Further, an alignment film 30 is formed on the entire surface of the common electrode 29.

Finally, the T on which each layer is formed as described above
The FT array substrate 18 and the counter substrate 19 are arranged to face each other, and are bonded to each other with a sealing material to produce an empty cell. Next, when the liquid crystal 20 is sealed in the empty cell, the liquid crystal device of the present embodiment is completed.

As a comparative example, as shown in FIG. 24, when a pixel contact hole 47 is formed small at almost the center between adjacent data lines 4, only this portion has a locally concave shape. Molecules fall in various directions around the position of the pixel contact hole 47 when an electric field is applied, so that disclination occurs particularly near the center of the peripheral portion along the lower side of the pixel electrode 2.

On the other hand, in the liquid crystal device of the present embodiment, the pixel contact hole 34 for electrically connecting the pixel electrode 2 and the barrier layer 32 is connected to the adjacent data line 4.
The shape extends along the scanning line 5 between them. As a result, it is possible to suppress the occurrence of disclination, and it is possible to obtain the same effects as those of the first embodiment in that the image quality, the contrast ratio, and the aperture ratio can be improved.

Also, in the case of the first embodiment, as shown in FIG. 2, the pixel electrode 2 is directly connected to the drain region 11 of the TFT 3 at the pixel contact hole 14, so that the pixel contact hole The pattern 14 and the pattern of the capacitor line 7 cannot be overlapped in a plane. Therefore, the pattern of the pixel contact hole 14 is limited by the pattern of the capacitor line 7 and the pattern of the pixel contact hole 1 is limited.
When the area of the pixel contact hole 14 is increased, the area of the storage capacitor 6 is correspondingly reduced, so that the area of the pixel contact hole 14 cannot be increased unnecessarily.

On the other hand, in the case of this embodiment, FIG.
Since the pixel contact hole 34 connects the pixel electrode 2 and the barrier layer 32, the pattern of the pixel contact hole 34 and the barrier layer 3
2 and the pattern of the capacitor line 7 located below the capacitor line 2 can be superimposed two-dimensionally. Therefore, the area of the pixel contact hole 34 can be sufficiently increased without reducing the area of the storage capacitor 6. Thereby, the influence of the pixel contact hole 34 on the alignment control of the liquid crystal can be increased.

[Third Embodiment] Hereinafter, a third embodiment of the present invention will be described.
The liquid crystal device according to the embodiment will be described with reference to FIG. FIG. 14 is a diagram showing a cross-sectional structure of the liquid crystal device of the present embodiment, and is a cross-sectional view corresponding to a cross section taken along line BB ′ of FIG. Since the planar pattern configuration of the liquid crystal device of this embodiment is exactly the same as that of FIG. 5 of the second embodiment, only a cross-sectional view corresponding to FIG. 6 of the second embodiment will be presented here. . 14, the same reference numerals are given to the same components as those in FIG. 6, and the detailed description will be omitted.

In the first and second embodiments, the pixel electrode 2
The peripheral portions along all four sides of the above-mentioned shape protruded in a bank shape in a rectangular shape in plan view. On the other hand, in the third to fifth embodiments described below, only the peripheral portion along the lower side of the pixel electrode 2 in FIG. 5 is flattened to the same level as the central portion of the pixel electrode 2. Alternatively, a configuration in which the peripheral edge along the remaining three sides is protruded in a U-shaped bank shape as shown in FIG.

In the case of the liquid crystal device of this embodiment, the laminated structure itself is exactly the same as the structure shown in FIG. 6, but as shown in FIG.
A depression 16a is formed at a position corresponding to No. 4, and each layer is stacked thereon. The depth of the recess 16a is set substantially equal to the sum of the thicknesses of the three layers of the semiconductor layer 9, the capacitor line 7, and the barrier layer 32. Therefore, the storage capacitor electrode 24, the capacitor line 7, a part of the barrier layer 32, and the like are in a state of being buried in the recess 16a, and the peripheral edge of the lower side of the pixel electrode 2 in FIG. Pixel electrode 2
Is flattened with respect to the center portion of the pixel contact hole, and the pixel contact hole 34 is recessed thereon.

When manufacturing the liquid crystal device having the above structure,
First, in a first step, a resist mask having an opening corresponding to the pixel contact hole 34 is formed on the surface of the substrate 16, and the depression 16 a having a predetermined depth may be formed using a technique such as wet etching. Subsequent steps are the second
It may be exactly the same as the embodiment.

In the liquid crystal device of the present embodiment, only the periphery along one side of one pixel electrode 2 is flattened to the same level as the center of the pixel electrode 2 so that the remaining three
A peripheral portion along the side can be projected in a bank shape in a U-shape in plan view. Therefore, as described above, the alignment control effect due to the provision of the U-shaped projections on the three sides of the peripheral portion of the pixel electrode 2 and the pixel contact hole extending along the scanning line 5 between the data lines 4 The liquid crystal molecules in the vicinity of the pixel contact hole are combined with one side of the side of the pixel electrode 2 where there is no convex portion (the lower side of the pixel electrode in FIG. 5). The tendency to fall together from the side (side) to the side opposite to this side is further increased, and disclination can be suppressed more reliably.

[Fourth Embodiment] Hereinafter, a fourth embodiment of the present invention will be described.
The liquid crystal device according to the embodiment will be described with reference to FIGS. 15 and 16 are diagrams showing a cross-sectional structure of the liquid crystal device of the present embodiment, and FIG.
16 is a cross-sectional view corresponding to the cross section taken along the line B-B ', and FIG.
FIG. 3 is a cross-sectional view corresponding to the cross section (only the TFT array substrate side is shown). 15 and 16, the same reference numerals are given to the same components as those in FIG. 6, and the detailed description will be omitted.

In the liquid crystal device of the present embodiment, FIG.
As in the third embodiment shown in FIG.
6a is not formed, and the surface of the substrate 16 is flat. The second embodiment differs from the second embodiment shown in FIG. 6 in that, as shown in FIG.
Is formed thick and its surface is flattened, and the data line 4 is formed on the flattened lower second interlayer insulating film 26a.

FIG. 16 is a sectional view taken along the line CC ′ in FIG.
FIG. 3 is a cross-sectional view of the lower edge of the pixel electrode 2 cut in a direction perpendicular to the edge. Lower second interlayer insulating film 26
The configuration itself of the pixel contact hole 34 is the same as that of FIG. 6 except that the surface of a is flattened.
A conductive layer 4 formed of the same film as the data line 4 is formed in a region above the scanning line 5 on the lower-layer side second interlayer insulating film 26a.
9 are provided.

In manufacturing the liquid crystal device of the present embodiment, steps up to the formation of the barrier layer 32 are performed in the same manner as the manufacturing process described in the second embodiment. The insulating film 26a is formed to a thickness sufficiently larger than the thickness in the second embodiment. Thereafter, the surface of the lower second interlayer insulating film 26a is planarized by using a known planarization technique such as an etch-back method or a chemical mechanical polishing (CMP) method. Then, a source contact hole 13 reaching the source region 10 of the TFT 3 through the lower second interlayer insulating film 26a is opened, and a metal film made of a low-resistance metal such as Al or a metal silicide is formed on the entire surface. Thereafter, the data line 4 is formed by patterning the metal film using photolithography, etching, or the like, and at the same time, the metal film is left in a region above the scanning line 5,
The conductive layer 49 is used. Here, as a pattern of the photomask used in the photolithography step, in addition to the pattern of the data line 4, a pattern for leaving the metal film in a region above the scanning line 5 may be formed.

FIG. 17 schematically shows the shape of one pixel of the TFT array substrate at this time. As shown in this figure, data lines 4 extending in parallel with each other and conductive portions extending in a direction orthogonal to data lines 4 between these data lines 4 on lower-side second interlayer insulating film 26a having a flat surface. Layer 4
9 are provided. The conductive layer 49 is formed on the data line 4
The data lines 4 are formed apart from each other so as not to short-circuit each other. In addition, the code | symbol 34 in FIG.
A pixel contact hole formed after the formation of the interlayer insulating film 26a is shown.

The subsequent steps are performed on the upper second interlayer insulating film 26.
Subsequent to the formation of b, the formation of the pixel contact hole 34, and the formation of the pixel electrode 2, the process is the same as the manufacturing process described in the second embodiment.

In the third embodiment, a part of the wiring is
By embedding in the recesses 16a formed in FIG. 6, only the peripheral portion along one side of the pixel electrode 2 is flattened, and the peripheral portions along the remaining three sides are projected in a U-shaped bank shape in plan view. Was. On the other hand, in the present embodiment, the lower layer side second
At the stage after the formation of the interlayer insulating film 26a, the surface of the substrate 16 is once flattened, and the bank portions along the three sides of the pixel electrode 2 are projected using a metal film for forming the data lines 4. Therefore, according to the present embodiment, FIG.
It is possible to reliably form the pixel electrode 2 having a convex portion having a U-shape in a peripheral portion as shown in FIG.

As a result, the alignment control effect due to the provision of the U-shaped convex portions on the three sides of the peripheral portion of the pixel electrode 2 and the pixel contact hole 34 extending along the scanning line 5 between the data lines 4 are formed. With the orientation control effect provided by the provision, disclination can be more reliably suppressed, and an effect similar to that of the third embodiment, in which the contrast ratio can be improved, can be obtained.

In the present embodiment, the metal film forming the data line 4 is used to form the bank portions along the three sides of the pixel electrode. In forming this portion, the data line 4 must be formed. A completely different film may be used without being limited to the constituent metal film. However, it is not preferable that the bank portion is formed by using another film which is not substantially necessary for the liquid crystal device, because the number of steps in the manufacturing process increases and the laminated structure becomes complicated. From this point, in the method according to the present embodiment, since the bank portion is formed by using a film originally required as a liquid crystal device, the pixel electrode peripheral portion can be formed without changing the conventional manufacturing process.
There is an advantage that a convex portion having a U-shape in plan view can be formed on the side.

[Fifth Embodiment] Hereinafter, a fifth embodiment of the present invention will be described.
The liquid crystal device according to the embodiment will be described with reference to FIG. FIG. 18 is a diagram showing a cross-sectional structure of the liquid crystal device of the present embodiment, and is a cross-sectional view corresponding to a cross section taken along line BB ′ of FIG. Since the planar pattern configuration of the liquid crystal device of this embodiment is exactly the same as that of FIG. 5 of the second embodiment, only a cross-sectional view corresponding to FIG. 6 of the second embodiment will be presented here. . 18, the same reference numerals are given to the same components as those in FIG. 6, and the detailed description will be omitted.

In the case of the liquid crystal device of the present embodiment, similarly to the third embodiment shown in FIG. 14, the laminated structure itself is exactly the same as the structure shown in FIG. 6, but as shown in FIG. The recess 22a is formed such that the position of the base insulating film 22 corresponding to the pixel contact hole 34 is thinner than other portions.
Is formed, and each layer is laminated thereon. In addition, the depth of the recess 22 a is
It is set substantially equal to the sum of the film thicknesses of the capacitance line 7 and the barrier layer 32. Therefore, the storage capacitor electrode 24,
The capacitance line 7, the barrier layer 32, and the like are embedded in the depression 22 a, and the periphery of the lower side of the pixel electrode 2 in FIG. And the pixel contact hole 34 is depressed thereon.

When manufacturing the liquid crystal device having the above structure,
The initial steps up to the formation of the base insulating film 22 are performed in the same manner as in the manufacturing process described in the second embodiment, but the thickness of the base insulating film 22 is set so as to allow for the reduction. Then, a resist mask having an opening at a portion corresponding to the pixel contact hole 34 is formed on the surface of the base insulating film 22, and the depression 22a having a predetermined depth may be formed by using a method such as wet etching. Subsequent steps may be exactly the same as in the second embodiment.

In the liquid crystal device of the present embodiment, similarly to the third embodiment, a part of the wiring is buried in the depression 22a of the base insulating film 22, and only the peripheral portion along one side of the pixel electrode 2 is flattened. Thus, the peripheral portions along the remaining three sides can be projected in a U-shaped bank shape in plan view. Thus, an alignment control effect due to the provision of the U-shaped convex portions on the three sides of the peripheral portion of the pixel electrode 2 and a pixel contact hole 34 extending along the scanning line 5 between the data lines 4 are provided. With the alignment control effect of the third embodiment, the same effect as in the third and fourth embodiments, in which disclination can be suppressed more reliably and the contrast ratio can be improved, can be obtained.

Also, in the case of the present embodiment, in particular, the first light-shielding layer 21 and the storage capacitor electrode 24 are interposed between the thinned base insulating film 22 in the thinned portion of the base insulating film 22 in the region where the pixel contact hole 34 is formed. And the first light shielding layer 21
Is fixed to a constant potential, a storage capacitor in which the first light-shielding layer 21 and the storage capacitor electrode 24 form a pair of electrodes is formed. As a result, in addition to the original storage capacity, the storage capacity can be obtained in this portion, so that the occupation area of the entire storage capacity can be reduced. For example, if a contact hole for electrically connecting the first light-shielding layer 21 and the capacitor line 7 is formed in the overlapping portion, the first light-shielding layer 21 together with the capacitor line 7 can be fixed at a constant potential.

[Electronic Apparatus] An example of an electronic apparatus including the liquid crystal device of the above embodiment will be described. FIG. 19 is a perspective view showing an example of a mobile phone. In FIG. 19, reference numeral 1000 denotes a mobile phone main body, and reference numeral 1001 denotes an image display unit using the above-described liquid crystal device.

FIG. 20 is a perspective view showing an example of a wristwatch-type electronic device. 20, reference numeral 1100 denotes a watch main body, and reference numeral 1101 denotes an image display unit using the above-described liquid crystal device.

FIG. 21 is a perspective view showing an example of a portable information processing device such as a word processor or a personal computer. In FIG. 21, reference numeral 1200 denotes an information processing device, reference numeral 1202 denotes an input unit such as a keyboard, reference numeral 1204 denotes an information processing device main body, and reference numeral 1206 denotes an image display unit using the above-described liquid crystal device.

Since the electronic devices shown in FIGS. 19 to 21 are provided with the image display unit using the liquid crystal device of the above embodiment, the deterioration of the image quality due to the disclination is small, the high contrast ratio and the high An electronic device having an image display portion with an aperture ratio can be realized.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the constituent materials of each layer, the pattern shape, the film thickness, specific numerical values such as various processing conditions during the manufacturing process, etc. described in the above embodiment are not limited to the above examples, and can be appropriately changed. Of course. Further, in the third to fifth embodiments, an example has been described in which the peripheral portion along one side of the pixel electrode is flattened together with the central portion of the pixel electrode. The peripheral portion along the side may be recessed from the central portion of the pixel electrode.

Further, in the third to fifth embodiments, examples have been shown in which the configuration specific to each embodiment is applied based on the liquid crystal device of the second embodiment having a barrier layer. Instead of the configuration, a configuration specific to each embodiment can be applied to the liquid crystal device of the first embodiment having no barrier layer. Although the description of the manufacturing method is omitted in the first embodiment, the subsequent steps can be performed in the same manner as in the manufacturing method illustrated in the second embodiment except for the steps around the barrier layer formation. it can.

[0123]

As described above in detail, according to the present invention, by providing the pixel contact hole extending along the scanning line between the adjacent data lines, the liquid crystal molecules are formed in the pixel contact hole. Since one side of the formed side tends to fall toward the center of the pixel, it is difficult to form a domain structure in which liquid crystal molecules are oriented in various directions as in the related art, and it is possible to suppress the occurrence of disclination. it can. As a result, the image quality and the contrast ratio can be improved, and the aperture ratio can be improved by reducing the size of the light shielding layer that hides unnecessary disclination.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a liquid crystal device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a plurality of pixel groups of a TFT array substrate constituting the liquid crystal device.

FIG. 3 is a sectional view taken along the line A-A 'of FIG.

FIG. 4 is a schematic diagram showing a state of unevenness of a pixel electrode in one pixel of the liquid crystal device.

FIG. 5 is a plan view illustrating a plurality of pixel groups of a TFT array substrate that constitutes a liquid crystal device according to a second embodiment of the present invention.

FIG. 6 is a sectional view taken along line B-B 'of FIG.

FIG. 7 is a process sectional view showing the manufacturing process of the liquid crystal device in order.

FIG. 8 is a continuation of the same process sectional view.

FIG. 9 is a continuation of the same process sectional view.

FIG. 10 is a continuation of the same process sectional view.

FIG. 11 is a continuation of the process cross-sectional view.

FIG. 12 is a continuation of the process cross-sectional view.

FIG. 13 is a continuation of the same process sectional view.

14 is a diagram illustrating a configuration of a liquid crystal device according to a third embodiment of the present invention, and is a cross-sectional view corresponding to line BB ′ of FIG.

FIG. 15 is a diagram illustrating a configuration of a liquid crystal device according to a fourth embodiment of the present invention, and is a cross-sectional view corresponding to line BB ′ of FIG.

16 is a view showing the configuration of the liquid crystal device, and is a cross-sectional view corresponding to the line CC ′ of FIG. 5;

FIG. 17 is a view schematically showing a state after forming a data line in a manufacturing process of the liquid crystal device.

FIG. 18 is a diagram showing a configuration of a liquid crystal device according to a fifth embodiment of the present invention, and is a cross-sectional view corresponding to line BB ′ of FIG.

FIG. 19 illustrates an example of an electronic apparatus including the liquid crystal device of the present invention.

FIG. 20 is a diagram illustrating another example of the electronic device.

FIG. 21 is a diagram showing still another example of the electronic apparatus.

FIG. 22 is a perspective view schematically showing a pixel electrode in the liquid crystal device of the present invention.

FIG. 23 is an explanatory diagram showing equipotential lines generated by a pixel electrode.

FIG. 24 is a plan view showing a configuration of a TFT array substrate of a liquid crystal device previously proposed by the present applicant as a measure against disclination.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pixel 2 Pixel electrode 2a (the periphery of pixel electrode) 3 Thin film transistor (switching element, TFT) 4 Data line 5 Scan line 6 Storage capacity 7 Capacity line 9 Semiconductor layer 10 Source region 11 Drain region 12 Channel region 13 Source contact Hole 14, 34 Pixel contact hole 16 Substrate 16a Depression (of substrate) 18 TFT array substrate 19 Counter substrate 20 Liquid crystal 21 First light-shielding layer 22 Base insulating film 22a Depression (of base insulating film) 23 Gate insulating film 24 Storage capacitor electrode 25 First interlayer insulating film 26 Second interlayer insulating film 26a Lower second interlayer insulating film 26b Upper second interlayer insulating film 32 Barrier layer 33 Drain contact hole 49 Conductive layer (second conductive layer)

Claims (19)

[Claims] 1. A vertical alignment mode liquid crystal is sandwiched between a pair of substrates, and one of the pair of substrates has a plurality of scanning lines, a data line intersecting the plurality of scanning lines,
A switching element disposed corresponding to the scanning line and the data line; an interlayer insulating film provided at least on a drain region of the switching element; a pixel contact hole formed in the interlayer insulating film; A pixel electrode electrically connected to the drain region via a contact hole, wherein the pixel contact hole comprises:
A liquid crystal device extending from a data line connected to the switching element to a vicinity of a data line adjacent to the data line along the scanning line. 2. A liquid crystal in a vertical alignment mode is interposed between a pair of substrates. One of the pair of substrates has a plurality of scanning lines, a data line intersecting the plurality of scanning lines,
A switching element disposed corresponding to the scanning line and the data line; an interlayer insulating film provided at least on a drain region of the switching element; a pixel contact hole formed in the interlayer insulating film; A pixel electrode electrically connected to the drain region through a contact hole, and a storage capacitor added to the pixel electrode, wherein the storage capacitor has one electrode extending from the drain region; And the other electrode is disposed on the one electrode with a gate insulating film interposed therebetween and is formed of the same film as the scanning line, and the other electrode is disposed along the scanning line more than the scanning line. Wherein the drain region is disposed closer to the center of the pixel electrode than the one electrode; and Lumpur, along said scan line, a liquid crystal device characterized by comprising extends to the vicinity of the data lines adjacent to the connected data line and the data line to the switching element. 3. A vertical alignment mode liquid crystal is sandwiched between a pair of substrates. One of the pair of substrates has a plurality of scanning lines, a data line intersecting the plurality of scanning lines,
A switching element disposed corresponding to the scanning line and the data line; a first interlayer insulating film provided at least on a drain region of the switching element; and a conductive element provided on the first interlayer insulating film. A barrier layer, a second interlayer insulating film provided on the barrier layer, a pixel electrode provided on the second interlayer insulating film, and an electrical connection between the pixel electrode and the barrier layer. A pixel contact hole, and a drain contact hole for electrically connecting the barrier layer and the drain region. The pixel contact hole is connected to the switching element along the scanning line. A liquid crystal device extending to a vicinity of a data line and a data line adjacent to the data line. 4. A liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, and one of the pair of substrates has a plurality of scanning lines, a data line intersecting the plurality of scanning lines,
A switching element arranged corresponding to the scanning line and the data line; a gate insulating film provided on one of a drain region and a storage capacitor electrode of the switching element; and a gate insulating film provided on the gate insulating film. A gate electrode and the other electrode of the storage capacitor; a first interlayer insulating film provided on the gate electrode and the other electrode; a barrier layer provided on the first interlayer insulating film; A second interlayer insulating film provided on the layer, a pixel electrode provided on the second interlayer insulating film, a pixel contact hole for electrically connecting the pixel electrode and the barrier layer, A drain contact hole for electrically connecting the barrier layer and the drain region, wherein the other electrode and the barrier layer are arranged along the scan line and more than the scan line. The pixel contact hole is arranged on the center side of the pixel electrode, and extends along the scanning line to a vicinity of a data line connected to the switching element and a data line adjacent to the data line. A liquid crystal device, comprising: 5. A peripheral portion of the pixel electrode includes a data line connected to the switching element, a data line adjacent to the data line, and a scanning line adjacent to a scanning line connected to the switching element. The liquid crystal device according to any one of claims 1 to 4, wherein the liquid crystal device is arranged so as to overlap in a plan view. 6. A liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, wherein one of the pair of substrates has a plurality of scanning lines, a data line intersecting the plurality of scanning lines,
A switching element arranged corresponding to the scanning line and the data line, a first interlayer insulating film provided at least on a drain region of the switching element, and a barrier layer provided on the first interlayer insulating film A second interlayer insulating film provided on the barrier layer; a pixel electrode provided on the second interlayer insulating film; and a pixel contact for electrically connecting the pixel electrode and the barrier layer. A hole, and a drain contact hole for electrically connecting the barrier layer and the drain region. The pixel contact hole includes a data line connected to the switching element along the scanning line. The pixel electrode extends in the vicinity of a data line adjacent to the data line, and the pixel electrode has a rectangular shape. A data line connected to an element, a data line adjacent to the data line, and a scan line adjacent to a scan line connected to the switching element, which are arranged so as to overlap in plan view, and the pixel Liquid crystal characterized in that a peripheral edge of one remaining side of the electrode is disposed on the pixel contact hole, and a peripheral edge of three sides of the pixel electrode protrudes from the peripheral edge of the remaining one side. apparatus. 7. The liquid crystal device according to claim 1, wherein a taper angle of the pixel contact hole is set to be substantially equal to a desired pretilt angle of the liquid crystal. 8. The liquid crystal device according to claim 1, wherein the substrate is formed with a depression corresponding to a position of the pixel contact hole. 9. The switching element is electrically connected to the data line via a source contact hole formed in the interlayer insulating film or the second interlayer insulating film. 9. The liquid crystal device according to claim 1, wherein a conductive layer is provided on the scanning line. 10. The liquid crystal device according to claim 9, wherein the surface of the interlayer insulating film or the second interlayer insulating film is flattened. 11. A light-shielding film is provided in a region corresponding to the switching element on the substrate, a base insulating film is provided on the light-shielding film, and the switching element is disposed on the base insulating film. The liquid crystal device according to claim 1, wherein the insulating film has a depression so as to be thin in a region corresponding to a position of the pixel contact hole. 12. A method for manufacturing a liquid crystal device in which liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, wherein a step of forming a depression on the surface of the substrate in accordance with the position of a pixel contact hole to be formed later. Forming a semiconductor layer forming a part of a switching element on the substrate, forming a gate insulating film covering the semiconductor layer, and forming a plurality of scanning lines on the gate insulating film; Forming a source region and a drain region of the switching element in the semiconductor layer, forming a first interlayer insulating film covering the scanning line and the switching element, and forming a plurality of the first interlayer insulating film on the first interlayer insulating film. Forming a data line; forming a second interlayer insulating film covering the plurality of data lines on the first interlayer insulating film; Forming a pixel contact hole at a position along the scanning line and near a data line connected to the switching element and a data line adjacent to the data line; and Forming a pixel electrode electrically connected to the drain region of the switching element. 13. A method of manufacturing a liquid crystal device in which a liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, wherein a step of forming a depression on a surface of the substrate in accordance with a position of a pixel contact hole to be formed later. Forming a semiconductor layer forming a part of a switching element on the substrate, forming a gate insulating film covering the semiconductor layer, and forming a plurality of scanning lines on the gate insulating film; Forming a source region and a drain region of the switching element in the semiconductor layer; forming a first interlayer insulating film covering the scanning line and the switching element; and forming a first interlayer insulating film on the drain region of the switching element. Forming a drain contact hole at a position through the first interlayer insulating film and reaching the drain region;
Forming a barrier layer electrically connected to the drain region through the drain contact hole on the first interlayer insulating film; and forming a lower second interlayer covering the barrier layer on the first interlayer insulating film. Forming an insulating film, forming a plurality of data lines on the lower second interlayer insulating film, and forming an upper second interlayer covering the plurality of data lines on the lower second interlayer insulating film; Forming an insulating film, extending along a scan line to a position corresponding to a drain region of the switching element to a vicinity of a data line connected to the switching element and a data line adjacent to the data line; Forming a pixel electrode that is electrically connected to the barrier layer via the pixel contact hole. Method. 14. A method for manufacturing a liquid crystal device in which a vertical alignment mode liquid crystal is sandwiched between a pair of substrates, comprising: forming a semiconductor layer forming a part of a switching element on a substrate; Forming a gate insulating film covering the gate insulating film, forming a plurality of scanning lines on the gate insulating film, forming a source region and a drain region of the switching element in the semiconductor layer; Forming a first interlayer insulating film covering the switching element, forming a plurality of data lines on the first interlayer insulating film and forming a conductive layer along the scan line; Forming a second interlayer insulating film covering the plurality of data lines and the conductive layer on the insulating film; and forming a second interlayer insulating film along the scanning line at a position corresponding to a drain region of the switching element. Forming a data line connected to the switching element and a pixel contact hole extending to the vicinity of a data line adjacent to the data line; and electrically connecting a drain region of the switching element via the pixel contact hole. Forming a pixel electrode to be connected to the liquid crystal device. 15. A method for manufacturing a liquid crystal device in which a liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, comprising: forming a semiconductor layer forming a part of a switching element on a substrate; Forming a gate insulating film covering the gate insulating film, forming a plurality of scanning lines on the gate insulating film, forming a source region and a drain region of the switching element in the semiconductor layer; Forming a first interlayer insulating film covering the switching element; and forming a drain contact hole reaching the drain region through the first interlayer insulating film at a position corresponding to the drain region of the switching element. Forming a barrier layer on the first interlayer insulating film, the barrier layer being electrically connected to the drain region via the drain contact hole; Forming a lower second interlayer insulating film covering the barrier layer on the first interlayer insulating film; forming a plurality of data lines on the lower second interlayer insulating film; Forming a conductive layer along the lower layer, forming an upper second interlayer insulating film covering the plurality of data lines and the conductive layer on the lower second interlayer insulating film, Forming, at a position corresponding to a drain region, a pixel contact hole extending to a vicinity of a data line connected to the switching element and a data line adjacent to the data line along the scanning line; and Forming a pixel electrode electrically connected to the barrier layer via a contact hole. 16. After a surface of the first interlayer insulating film or the lower second interlayer insulating film is flattened, a conductive layer is formed on the flattened first interlayer insulating film or the lower second interlayer insulating film. 16. The method of claim 14, wherein
3. The method for manufacturing a liquid crystal device according to item 1. 17. A method for manufacturing a liquid crystal device in which liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, wherein a light shielding film is formed in a partial region on a substrate on which a switching element is to be formed later. Forming a base insulating film covering the light-shielding film on the substrate; thinning the base insulating film in a region where a pixel contact hole is to be formed later; and forming a switching element on the base insulating film. Forming a semiconductor layer forming a portion, forming a gate insulating film covering the semiconductor layer, forming a plurality of scanning lines on the gate insulating film, and forming a source of the switching element on the semiconductor layer. Forming a region and a drain region; forming a first interlayer insulating film covering the scanning lines and the switching elements; and forming a plurality of data lines on the first interlayer insulating film. Forming a second interlayer insulating film covering the plurality of data lines on the first interlayer insulating film; and forming the switching element along the scanning line at a position corresponding to a drain region of the switching element. Forming a data line connected to the element and a pixel contact hole extending to the vicinity of the data line adjacent to the data line; and electrically connecting to the drain region of the switching element via the pixel contact hole. Forming a pixel electrode. 18. A method for manufacturing a liquid crystal device in which liquid crystal in a vertical alignment mode is sandwiched between a pair of substrates, wherein a step of forming a light shielding film in a partial region on a substrate on which a switching element is to be formed later Forming a base insulating film covering the light-shielding film on the substrate; thinning the base insulating film in a region where a pixel contact hole is to be formed later; and forming a switching element on the base insulating film. Forming a semiconductor layer forming a portion, forming a gate insulating film covering the semiconductor layer, forming a plurality of scanning lines on the gate insulating film, and forming a source of the switching element on the semiconductor layer. Forming a region and a drain region, forming a first interlayer insulating film covering the scanning line and the switching element, and corresponding to a drain region of the switching element. Forming a drain contact hole penetrating through the first interlayer insulating film to reach the drain region, and electrically connecting to the drain region via the drain contact hole on the first interlayer insulating film. Forming a lower-layer-side second interlayer insulating film covering the barrier layer on the first interlayer insulating film; and forming a plurality of data lines on the lower-layer second interlayer insulating film. Forming, forming an upper second interlayer insulating film covering the plurality of data lines on the lower second interlayer insulating film, and forming the scanning line at a position corresponding to a drain region of the switching element. Forming a pixel contact hole extending to the vicinity of a data line connected to the switching element and a data line adjacent to the data line along the pixel contact hole; Forming a pixel electrode that is electrically connected to the barrier layer via a liquid crystal device. 19. An electronic apparatus comprising the liquid crystal device according to claim 1. Description: