JP2002023148A - Electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent such problems that in a conventional liquid crystal panel using a metal film as a light shielding mask for a color filter, parasitic capacitance is generated in the metal film with other lines and this easily causes delay in signals and that when an organic film containing a black pigment is used as a light shielding mask for a color filter, the number of production processes increases. SOLUTION: A film of two color layers laminated (a laminated film of a red color layer 13 and a blue color layer 12 or a laminated film of a red color layer 13 and a green color layer 11) is formed as a light shielding part on a counter substrate without using a light shielding mask (black matrix) in such a manner that the laminated film overlaps TFTs on a device substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. TFTs are widely applied to electronic devices such as ICs and electro-optical devices, and their development is particularly urgent as switching elements for liquid crystal display devices.

In order to obtain a high-quality image in a liquid crystal display device, an active matrix type liquid crystal display device in which pixel electrodes are arranged in a matrix and a TFT is used as a switching element connected to each of the pixel electrodes has attracted attention. ing.

Active matrix type liquid crystal display devices are roughly classified into two types, a transmission type and a reflection type.

[0006] In particular, a reflective liquid crystal display device has an advantage that it consumes less power because it does not use a backlight, as compared with a transmissive liquid crystal display device. The demand as a direct-view display is increasing.

[0007] The reflection type liquid crystal display device utilizes the optical modulation of liquid crystal to reflect incident light on the pixel electrode and output the same to the outside of the device, and to reflect the incident light to the outside of the device. Is selected, the display of light and dark is performed, and an image is displayed by combining them. Generally, a pixel electrode in a reflective liquid crystal display device is
It is made of a metal material having high light reflectance such as aluminum and is electrically connected to a switching element such as a thin film transistor (hereinafter, referred to as a TFT).

In a liquid crystal display device, a TFT using amorphous silicon or polysilicon as a semiconductor is used.
Are arranged in a matrix, and a liquid crystal material is disposed between an element substrate on which pixel electrodes, source lines, and gate lines connected to each TFT are formed, respectively, and an opposing substrate having an opposing electrode disposed opposite thereto. Is pinched. A color filter for color display is attached to the opposite substrate. Then, a polarizing plate is arranged as an optical shutter on each of the element substrate and the counter substrate, and a color image is displayed.

This color filter is composed of R (red), G
(Green) and B (blue) coloring layers, and a light-shielding mask that covers only the gaps between pixels.
Extracts green and blue light. The light-shielding mask is generally formed of a metal film (such as chromium) or an organic film containing a black pigment. This color filter is formed at a position corresponding to a pixel, and can thereby change the color of light extracted for each pixel. Note that the position corresponding to the pixel indicates a position that matches the pixel electrode.

[0010]

In a conventional liquid crystal display panel using a metal film as a light-shielding mask of a color filter, there has been a problem that a parasitic capacitance is formed with other wirings and signal delay is likely to occur. Further, when an organic film containing a black pigment is used as a light-shielding mask of a color filter, there has been a problem that the number of manufacturing steps increases.

[0011]

The present invention is characterized by a pixel structure that shields light between a TFT and a pixel without using a light-shielding mask (black matrix). As one of means for shielding light, a film in which two colored layers are laminated as a light shielding portion on a counter substrate (a laminated film of a red colored layer and a blue colored layer, or a red colored layer and a green colored layer Is formed so as to overlap the TFT of the element substrate.

In the present specification, the “red colored layer” is a layer that absorbs a part of light applied to the colored layer and extracts red light. Similarly, the “blue colored layer” absorbs a part of the light applied to the colored layer and extracts blue light, and the “green colored layer” is used to irradiate the colored layer. It absorbs a part of the emitted light and extracts green light.

The invention disclosed in this specification comprises a first light-shielding portion composed of a first colored layer and a second colored layer,
An electro-optical device, comprising: a second light-shielding portion including a stack of the first coloring layer and a third coloring layer.

In another aspect of the invention, a TFT and a first
A first light-shielding portion composed of a laminate of a first colored layer and a second colored layer, and a second light-shielding portion composed of a laminate of the first colored layer and a third colored layer. The electro-optical device is characterized in that the light-shielding portion and the second light-shielding portion are formed so as to overlap at least with a channel forming region of the TFT.

In another aspect of the present invention, a plurality of pixel electrodes, a first light-shielding portion composed of a laminate of a first colored layer and a second colored layer, the first colored layer and a third A second light-shielding portion formed of a stack of colored layers, wherein the first light-shielding portion and the second light-shielding portion overlap between any pixel electrode and a pixel electrode adjacent to the pixel electrode. An electro-optical device characterized by being formed by:

Further, in each of the above structures, the amount of reflected light of the first light-shielding portion and the amount of reflected light of the second light-shielding portion are different from each other.

Further, in each of the above structures, the first colored layer is red. Further, the second colored layer is blue. Further, the third colored layer is green.

Further, in each of the above structures, the third coloring layer is characterized in that it has a stripe shape.

In each of the above structures, the first light-shielding portion and the second light-shielding portion are provided on a counter substrate.

In each of the above structures, in the electro-optical device, the pixel electrode has a film containing Al or Ag as a main component;
Alternatively, the present invention is characterized in that the liquid crystal display device is a reflection type liquid crystal display device made of a laminated film thereof.

[0021]

Embodiments of the present invention will be described below.

FIG. 1 shows the configuration of the present invention. Here, a reflective liquid crystal display device will be described as an example.

FIG. 1A shows three colored layers 11 to 11 as appropriate.
13, the first light-shielding portion 15, the second light-shielding portion 1
6 and an example in which pixel openings 17 to 19 are configured. Generally, the colored layer is formed using a color resist made of an organic photosensitive material in which a pigment is dispersed.

First light-shielding part 15 and second light-shielding part 16
Are formed so as to shield the gap between the pixels from light. Therefore,
The incident light is absorbed by the first light-shielding portion 15 and the second light-shielding portion 16 and is recognized as substantially black by the observer. Further, the first light-shielding portion 15 and the second light-shielding portion 16 are formed so as to overlap with pixel TFTs (not shown here) of the element substrate, and serve to protect the pixel TFTs from external light.

The first light shielding portion 15 is formed by laminating a green coloring layer 11 and a red coloring layer 13. The red coloring layer 13 is patterned in a lattice shape. The green colored layer 11 is patterned in the same shape (striped shape) as that of the related art.

The second light-shielding portion 16 is formed by laminating a blue coloring layer 12 and a red coloring layer 13. In addition,
The blue coloring layer 12 is patterned so as to partially overlap the adjacent red coloring layer 13.

FIG. 1B shows the first light-shielding portion and the second light-shielding portion in FIG.
1 ') shows a cross-sectional structure cut. As shown in FIG. 1B, a coloring layer 13 is laminated so as to cover the coloring layers 11 and 12 on the counter substrate 10, and further, a flattening film 14 is formed.
Covers the colored layer 13.

The green coloring layer 11 and the red coloring layer 1
3 (first light-shielding portion 15), blue colored layer 12
(A second light-shielding portion 16) of a red film and a red colored layer 13;
The reflectance of each of the stacked films of the green colored layer and the blue colored layer was measured under certain measurement conditions (white light source (D65), reflective electrode (Al), viewing angle 2 °, objective lens 5 times). Table 1 shows the measurement results.

[0029]

[Table 1]

FIG. 3 is a graph of Table 1.

As shown in Table 1 and FIG. 3, R + B +
Al (corresponding to the second light shielding portion 16) is 400 to 450 nm
In the wavelength range of about 35%, and sufficiently functions as a light shielding mask. In addition, R + G + Al (first light shielding unit 1)
5) has a reflectance of about 50% near 570 nm, but sufficiently functions as a light-shielding mask.

FIG. 24 shows a non-single-crystal silicon film 55 nm in thickness.
The relationship between the absorptance and the wavelength for irradiation was shown. As shown in FIG. 24, the non-single-crystal silicon film forming the active layer of the TFT tends to absorb light in the wavelength region of 500 nm. In the wavelength region of 500 nm, the first light-shielding portion 15 and the second light-shielding portion 16 can suppress the reflectance to 10% or less as shown in Table 1 and FIG. Degradation can be suppressed.

When three colored layers are stacked, the light-shielding property is improved. However, since the three layers are stacked, the unevenness is increased, so that the flatness of the substrate is lost and the liquid crystal layer is disturbed. But,
As long as two colored layers are overlapped as in the present invention, the level does not substantially affect the liquid crystal layer on the flatness of the substrate.

As described above, the present invention is characterized in that a light-shielding mask is formed by a laminated film (R + B or R + G) composed of two colored layers. As a result, the step of forming a black matrix can be omitted, and the number of steps is reduced.

However, the cross-sectional view shown in FIG. 1B is an example, and is not particularly limited. For example, FIGS.
The structure shown in FIG. FIG. 2A shows an example in which a colored layer (R) 23 is first formed, and then a colored layer (B) 22 and a colored layer (G) 21 are laminated. FIG. G) After forming 31, a colored layer (R) 33 is formed, and then a colored layer (B) 32 is laminated,
FIG. 2C shows an example in which a colored layer (B) 42 is first formed, a colored layer (R) 43 is formed, and then a colored layer (G) 41 is laminated.

FIG. 4 shows the positional relationship between the wiring, the pixel electrode, and the coloring layer between the pixel electrodes. FIG. 4A shows a structure in which the colored layer (B) 58 and the colored layer (R) 5 are provided above the source wiring 50 so as to shield light between the pixel electrode 51 and the pixel electrode 52.
9 shows an example in which the end surfaces of the contact lines 9 and 9 are in contact with each other and the contact surface is present on the source wiring. Note that, in FIG.
3 and 55 are alignment films, 54 is liquid crystal, 56 is a counter substrate, 57
Is a flattening film.

The structure shown in FIGS. 4 (B) and 4 (C) is not limited to the example shown in FIG. 4 (A). Good.
FIG. 4B shows a colored layer (B) 68 above the source wiring 60 so as to shield light between the pixel electrode 61 and the pixel electrode 62.
This is an example in which the colored layer (R) 69 is formed so as to partially overlap the end of the colored layer (R). FIG. 4C shows that the source wiring 70 is shielded from light between the pixel electrode 71 and the pixel electrode 72.
This is an example in which the colored layer (B) 78 and the colored layer (R) 79 are formed so as not to be in contact with each other above.

The light that has passed through the pixel openings 17 to 19 is colored into corresponding colors by the single colored layers 11 to 13 and is recognized by the observer. FIG. 1 (C)
Indicates that a pixel opening in FIG.
2 ') shows a cross-sectional structure cut. As shown in FIG. 1C, a single-layered colored layer 11 to 13
Are sequentially formed, and further, these colored layers 11 to
13 is formed.

At the pixel opening, as in the conventional case shown in FIG. 25, the blue colored layer has a reflectance exceeding 90% at around 450 nm. The green colored layer is 53
It shows a reflectance of more than 90% near 0 nm. The red colored layer has a reflectance of more than 90% at 600 to 800 nm.

Here, since this is an example of a reflection type liquid crystal display device, light incident on the pixel openings 17 to 19 passes through the single colored layers 11 to 13, respectively, and then passes through the liquid crystal layer to form the pixel electrodes. And again, a liquid crystal layer, a single colored layer 11 to 11
13, the light of each color is extracted and perceived by the observer.

For the coloring layers 11 to 13, an oblique mosaic arrangement, a triangular mosaic arrangement, an RGBG four-pixel arrangement, an RGBW four-pixel arrangement, or the like can be used, including the simplest stripe pattern.

The arrangement of the colored layer of the present invention may be applied to a self-luminous display device using a white light emitting element.

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0044]

[Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to an example of manufacturing a counter substrate used in an active matrix type liquid crystal display device. FIG. 1 is a diagram schematically showing a counter substrate provided with a colored layer formed according to the present invention.

First, a glass substrate made of barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass is prepared as the opposing substrate 10 having a light-transmitting property. Other,
A light-transmitting substrate such as a quartz substrate or a plastic substrate can also be used.

Next, an organic photosensitive material (CGY-S705C: CO
LOR MOSAIC) is applied, and the organic photosensitive material is patterned into a stripe shape by photolithography as shown in FIG. 1A to form a green colored layer (G) 11 at a predetermined position. Here, patterning was performed with a width of 42 μm.

Next, an organic photosensitive material (CV
B-S706C: COLOR MO manufactured by Fuji Film Ohrin
SAIC) is applied, and the organic photosensitive material is patterned into the shape shown in FIG. 1A by photolithography to form a blue colored layer (B) 12. The blue colored layer (B) 12 and the green colored layer (G) 11 are formed so as not to overlap with each other.

Next, an organic photosensitive material (CR
Y-S778: COLOR MOSA manufactured by Fuji Film Olin
IC) is applied, and the organic photosensitive material is patterned in a lattice shape by photolithography as shown in FIG. 1A to form a red colored layer (R) 13. FIG.
As shown in FIG. 1B and FIG. 1A, the red colored layer (R) 13 partially overlaps the green colored layer (G) 11 to form a first light-shielding portion 15. On the other hand, as shown in FIG. 1C, a region of the green coloring layer (G) 11 that does not overlap with the red coloring layer (R) 13 is a green pixel opening 1.
It becomes 7. Note that the first light-shielding portion 15 is formed so as to overlap with a channel formation region of the TFT when the first light-shielding portion 15 is attached to an element substrate provided with the TFT.

As shown in FIGS. 1B and 1A, the red colored layer (R) 13 is formed of a blue colored layer (B).
The second light-shielding portion 16 partially overlaps the second light-shielding portion 12. on the other hand,
As shown in FIG. 1C, a region of the blue coloring layer (B) 12 that does not overlap with the red coloring layer (R) 13 is a blue pixel opening 18. In the present embodiment, the size of the pixel opening 18 was 126 μm × 42 μm. Note that the second light-shielding portion 16 is also formed so as to overlap a channel formation region of the TFT when the second light-shielding portion 16 is bonded to an element substrate provided with the TFT.

In the red coloring layer (R) 13, a region which does not overlap with the green coloring layer (G) 11 and does not overlap with the blue coloring layer (B) 12 is a red pixel opening 19. Becomes

In this way, the pixel openings 17 to 19, the first light-shielding portion 15, and the second light-shielding portion 16 can be formed by three times of photolithography.

Next, a flattening film 14 covering each coloring layer is formed. Since a level difference of about 1 to 1.5 μm is generated between a region where the coloring layer is a single layer and a region where the coloring layer overlaps two layers, the flattening film 14 needs to have a thickness of 1 μm or more, preferably 2 μm. And As the flattening film 14, a light-transmitting organic material, for example, an organic resin material such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) can be used.
However, if flatness does not matter, there is no need to provide this flattening film.

In this embodiment, the colored layers 11 to 13 are formed by applying an organic photosensitive material and patterning it into a desired shape by a photolithography method. However, it is needless to say that the present invention is not limited to the above manufacturing method. No.

Thereafter, although not shown, a counter electrode made of a transparent conductive film is formed on the flattening film, an alignment film for aligning the liquid crystal is further formed thereon, and a rubbing treatment is performed if necessary. Apply.

Using the counter substrate thus obtained, an active matrix liquid crystal display device is manufactured.

[Embodiment 2] In Embodiment 1, an example was shown in which a green coloring layer (G) 11, a blue coloring layer (B) 12, and a red coloring layer (R) 13 were sequentially formed. In the embodiment, an example in which each colored layer is formed in a different order from the embodiment 1 will be described below. Except for the order in which the colored layers are formed, the process is the same as that of the first embodiment, and only different points will be described.

As a first example, the structure shown in FIG. FIG. 2A shows an example in which a colored layer (R) 23 is first formed, and then a colored layer (B) 22 and a colored layer (G) 21 are stacked. Note that FIG. 2A corresponds to a cross-sectional structure view taken along a dashed line A1-A1 ′ in FIG.

As a second example, a structure shown in FIG. 2B may be employed. FIG. 2 (B) shows the colored layer (G) first.
This is an example in which a colored layer (R) 33 is formed after the formation of the colored layer 31 and then a colored layer (B) 32 is laminated. Note that FIG.
(B) corresponds to a cross-sectional structure diagram cut along a chain line A1-A1 'in FIG.

As a third example, a structure shown in FIG. 2C may be adopted. FIG. 2 (C) shows the colored layer (B) first.
This is an example in which a colored layer (R) 43 is formed after forming the colored layer 42 and then a colored layer (G) 41 is laminated. Note that FIG.
(C) corresponds to a cross-sectional structure diagram cut along a chain line A1-A1 'in FIG.

[Embodiment 3] In this embodiment, a method of manufacturing an element substrate (also referred to as an active matrix substrate) to be bonded to the counter substrate obtained in Embodiment 1 or 2 will be described. Here, the pixel portion and the pixel portion on the same substrate,
A method for simultaneously manufacturing TFTs (an n-channel TFT and a p-channel TFT) of a driver circuit provided around a pixel portion will be described in detail.

First, in this embodiment, Corning # 70
A substrate 100 made of glass such as barium borosilicate glass represented by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that as the substrate 100, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, as shown in FIG.
A base film 101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the substrate. Although a two-layer structure is used as the base film 101 in this embodiment, a single-layer film of the insulating film or a structure in which two or more insulating films are stacked may be used. As the first layer of the base film 101, a silicon oxynitride film 102a formed by a plasma CVD method using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is used.
Is formed in a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, a 50 nm-thick silicon oxynitride film 102a (composition ratio: Si = 32%, O = 27%, N = 24)
%, H = 17%). Next, as a second layer of the base film 101, SiH ₄ ,
And a silicon oxynitride film 101b formed using N ₂ O as a reaction gas to a thickness of 50 to 200 nm (preferably 100 to 200 nm).
(150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 101b (composition ratio Si
= 32%, O = 59%, N = 7%, H = 2%).

Next, the semiconductor layers 102 to 10 are formed on the underlying film.
6 is formed. The semiconductor layers 102 to 106 may be formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method)
A crystalline semiconductor film obtained by performing a known crystallization treatment (such as a laser crystallization method, a thermal crystallization method, or a thermal crystallization method using a catalyst such as nickel) is patterned and formed into a desired shape. . The thickness of the semiconductor layers 102 to 106 is 2
It is formed with a thickness of 5 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon or silicon germanium (SiGe).
It is good to form with an alloy etc. In this embodiment, the plasma C
After forming a 55 nm amorphous silicon film by the VD method, a solution containing nickel was held on the amorphous silicon film. Dehydrogenation (500 ° C., 1
After that, thermal crystallization (550 ° C., 4 hours) was performed, and further, a laser annealing treatment for improving crystallization was performed to form a crystalline silicon film. Then, semiconductor layers 102 to 106 were formed by patterning the crystalline silicon film using a photolithography method.

After the semiconductor layers 102 to 106 are formed, a slight amount of impurity element (boron or phosphorus) may be doped to control the threshold value of the TFT.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, or a YVO ₄ laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 40.
(Typically ^{200~300mJ / cm 2) 0mJ / cm} 2 to. When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 10 kHz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 35 to
0 to 500 mJ / cm ² ). And width 100-1
A laser beam condensed linearly at 000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 80 to 98%.
What should be done.

Next, a gate insulating film 107 covering the semiconductor layers 102 to 106 is formed. The gate insulating film 107 has a thickness of 40 to 40
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59) having a thickness of 110 nm by a plasma CVD method.
%, N = 7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O ₂ , a reaction pressure of 40 Pa, and a substrate temperature of 30
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, a film thickness of 20 is formed on the gate insulating film 107.
A first conductive film 108 having a thickness of 100 to 100 nm;
A second conductive film 109 having a thickness of 00 nm is stacked. In this embodiment, a first conductive film 108 made of a TaN film with a thickness of 30 nm and a second conductive film 109 made of a W film with a thickness of 370 nm are formed by lamination. The TaN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode, and the resistivity of the W film is 20 μΩc.
m or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, a sputtering method using a high-purity W (purity 99.9999% or 99.99%) target is used, and a sufficient amount of impurities is prevented from being mixed in the gas phase during film formation. By forming the W film with care, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 108
Is TaN, and the second conductive film 109 is W. However, the present invention is not particularly limited thereto, and any of them is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material containing the above element as a main component or It may be formed of a compound material. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is formed of a W film, and the first conductive film is formed of tantalum nitride (TaN).
A combination of a film and an Al film as the second conductive film;
The first conductive film may be formed of a tantalum nitride (TaN) film and the second conductive film may be formed of a Cu film.

Next, masks 110 to 115 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In addition, as an etching gas, Cl ₂ , B
Cl _3, SiCl _4, can be used CCl ₄ chlorine gas or CF ₄ to the typified like, SF _6, fluorine-based gas NF ₃ and the like typified, or O ₂ as appropriate. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, CF ₄ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are 25/25/10 (sccm). At a pressure of 1 Pa, RF (13.56 MHz) power of 500 W was applied to the coil-type electrode to generate plasma and perform etching. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to form the first film.
Of the conductive layer is tapered.

Then, a mask 110 made of resist is formed.
The etching conditions were changed to the second etching conditions without removing 115, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow rates were 30/30 (sccm), and the coil type electrode was formed at a pressure of 1 Pa. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the resist mask appropriate,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, by the first etching process, the first shape conductive layers 117 to 122 (the first conductive layers 117 a to 122 a and the second conductive layers 117 b to 117 b) each including the first conductive layer and the second conductive layer are formed.
2b) is formed. Reference numeral 116 denotes a gate insulating film,
The region not covered with the conductive layers 117 to 122 having the shape of
A region that is etched and thinned by about 50 nm is formed.

Then, the resist mask is removed.
First doping processing without adding an n-type semiconductor layer.
The added impurity element is added. (FIG. 5B) Dopin
Can be done by ion doping or ion implantation
Good. The condition of the ion doping method is that the dose amount is 1 × 10¹³
~ 5 × 10^Fifteenatoms / cm^TwoAnd the acceleration voltage is 60 to 100
Performed as keV. In this embodiment, the dose is 1.5 × 1
0^Fifteenatoms / cm^TwoAnd the acceleration voltage is set to 80 keV.
Was. Element belonging to Group 15 as an impurity element imparting n-type
Using arsenic, typically phosphorus (P) or arsenic (As)
However, phosphorus (P) was used here. In this case, the conductive layer 1
17 to 121 are masses for the impurity element imparting n-type.
And the first impurity regions 123 to 12 are self-aligned.
7 is formed. In the first impurity regions 123 to 127,
1 × 10²⁰~ 1 × 10^{twenty one}atoms / cm ^ThreeN type in the concentration range of
An impurity element to be added is added.

Next, a second etching process is performed as shown in FIG. 5C without removing the resist mask. The second etching process is performed under the third and fourth etching conditions. Similarly, as the third etching condition, I
Using CP etching method, CF ₄ and C are used as etching gas.
l ₂ and the respective gas flow ratios are 30/30 (s
ccm) and 500 W to the coil type electrode at a pressure of 1 Pa
RF power (13.56 MHz) was supplied to generate plasma, and etching was performed for about 60 seconds. 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage),
A self-bias voltage lower than that in the etching process is applied. Under the third etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent.

Thereafter, the etching conditions were changed to the fourth etching condition without removing the resist mask, CF ₄ , Cl _2, and O ₂ were used as etching gases, and the respective gas flow ratios were 25/25/10. (Sccm), a 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed for about 20 seconds. 20W RF (13.56MH) on the substrate side (sample stage)
z) Power is applied, and a lower self-bias voltage is applied than in the first etching process. The W film is etched under the fourth etching condition.

In this manner, the W film is anisotropically etched under the above third and fourth etching conditions, and the TaN film is anisotropically etched at a lower etching rate than the W film to form the second shape conductive layer 129. To 134 (the first conductive layer 12
9a to 134a and second conductive layers 129b to 134b) are formed. Reference numeral 128 denotes a gate insulating film, and a region which is not covered with the second shape conductive layers 129 to 134 is etched and reduced to a thickness of about 10 to 20 nm.

The etching reaction of the W film or the TaN film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ion species and the vapor pressure of the reaction product. Comparing the vapor pressures of the fluorides of W and TaN with the chlorides, the fluoride of W, WF _6, is extremely high, and the other WCl ₅ , TaF ₅ , and TaCl ₅ are comparable. Therefore, with the mixed gas of CF ₄ and Cl ₂ , both the W film and the TaN film are etched. However, an appropriate amount of O
_{When 2} is added, CF ₄ and O ₂ react to become CO and F,
F radicals or F ions are generated in large quantities. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in TaN, the increase in the etching rate is relatively small even if the F increases. Further, since TaN is more easily oxidized than W, the surface of TaN is slightly oxidized by adding O ₂ . Since the oxide of TaN does not react with fluorine or chlorine, the etching rate of the TaN film is further reduced. Therefore, it is possible to make a difference in the etching rate between the W film and the TaN film, and the etching rate of the W film is made to be Ta.
It can be made larger than the N film.

Next, a second doping process is performed as shown in FIG. 6A without removing the resist mask. In this case, doping with an impurity element imparting n-type is performed under a condition of a higher acceleration voltage with a lower dose than in the first doping process. For example, when the acceleration voltage is 70 to 12
0 keV, and in this embodiment, an acceleration voltage of 90 keV,
As shown in FIG. 5 at a dose of 3.5 × 10 ¹² atoms / cm ² .
A new impurity region is formed in the semiconductor layer inside the first impurity region formed in (B). Doping is second
The second conductive layers 129a to 133a are formed using the conductive layers 129b to 133b having
Is doped so that the impurity element is also added to the semiconductor layer below the tapered portion.

Note that the mask made of resist may be removed before the second doping process.

Thus, the second conductive layers 129a-133
Third impurity regions 140 to 144 overlapping with a, and second impurity regions 135 to 139 between the first impurity regions 145 to 149 and the third impurity region are formed. The impurity element imparting n-type is 1 × 10 ¹⁷ in the second impurity region.
The concentration is set to 1 × 10 ¹⁹ atoms / cm ³ , and the concentration is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ in the third impurity region. The third impurity region 140
To 144, the conductive layer 12 of at least the second shape
There is a change in the concentration of the impurity element imparting n-type contained in the portion overlapping with 9a to 133a. That is, the concentration of phosphorus (P) added to the third impurity regions 140 to 144 gradually decreases inward from the end of the conductive layer in a region overlapping with the conductive layer having the second shape. Become. This is because the concentration of phosphorus (P) reaching the semiconductor layer changes depending on the difference in the thickness of the tapered portion.

Then, after removing the mask made of resist, masks 150 to 152 made of resist are newly formed, and a third doping process is performed as shown in FIG. 6B. By this third doping treatment, fourth impurity regions 153 to 158 in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to a semiconductor layer to be an active layer of a p-channel TFT. . Using the second shape conductive layers 130 and 133 as a mask for the impurity element, a fourth impurity region is formed in a self-aligned manner by adding an impurity element imparting p-type. In this embodiment, the impurity regions 153 to 158 are formed by ion doping using diborane (B ₂ H _6). In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 150 to 152 made of resist. Phosphorus is added to the impurity regions 153 to 158 at different concentrations by the first doping process and the second doping process. In each of the regions, the concentration of the impurity element imparting p-type is set to 2 ×. 10 ^{20 to} 2 × 10 ²¹
By performing the doping process so as to be atoms / cm ³ , no problem occurs because the doping process functions as the source region and the drain region of the p-channel TFT.

Through the above steps, impurity regions are formed in the respective semiconductor layers. The second shape conductive layers 129 to 132 overlapping with the semiconductor layer function as gate electrodes. Reference numeral 134 denotes a source wiring, and 133 functions as a second electrode for forming a storage capacitor.

Next, a mask 150-
152 is removed, and a first interlayer insulating film 159 covering the entire surface is formed. As the first interlayer insulating film 159, a thickness of 100 to
The insulating film containing silicon is formed to have a thickness of 200 nm. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the first interlayer insulating film 159 is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 6C, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
The activation treatment may be performed at 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation treatment, the nickel used as a catalyst during the crystallization is doped with the impurity regions 145 to 149, 153, and 153 containing a high concentration of phosphorus.
The nickel concentration in the semiconductor layer which is gettered at 56 and mainly becomes a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film 159. However, 129-13
In the case where the wiring material used in 4 is weak to heat, an active layer is formed after an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. It is preferable to carry out a chemical treatment.

FIG. 7 is a top view of the pixel portion after the activation process. Note that the same reference numerals are used for portions corresponding to FIGS. The chain line CC 'in FIG.
Corresponds to a cross-sectional view taken along a chain line CC ′ in FIG. Also, the dashed line DD ′ in FIG.
This corresponds to a cross-sectional view cut along D '.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 350 ° C. for one hour in an atmosphere containing about 100% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen.
As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Further, heat treatment (300 to 550 ° C.) is performed using hydrogen contained in the interlayer insulating film made of a silicon nitride film.
For 1 to 12 hours) to hydrogenate the semiconductor layer. In this case, 41
By performing heat treatment at 0 ° C. for one hour, dangling bonds in the semiconductor layer can be terminated by hydrogen contained in the interlayer insulating film.

When a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 160 made of an organic insulating material is formed on the first interlayer insulating film 159. In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed. Next, a contact hole reaching the source wiring 134 and each of the impurity regions 145, 147, 148, and 15 are formed.
Patterning is performed to form contact holes reaching 3,156.

Then, in the driver circuit 406, wirings 161 to 166 electrically connected to the first impurity region or the fourth impurity region are formed. Note that these wirings are formed by patterning a laminated film of a 50-nm-thick Ti film and a 500-nm-thick alloy film (an alloy film of Al and Ti).

In the pixel portion 407, a pixel electrode 169, a gate wiring 168, and a connection electrode 167 are formed. (FIG. 8) The source electrode 13 is
No. 4 is electrically connected to the pixel TFT 404.
Further, the gate wiring 168 is electrically connected to the first electrode (the conductive layer 133 having the second shape). The pixel electrode 169 is electrically connected to the drain region of the pixel TFT, and is also electrically connected to a semiconductor layer functioning as one electrode forming a storage capacitor.
In addition, as the pixel electrode 169, it is preferable to use a material having excellent reflectivity, such as a film containing Al or Ag as a main component or a stacked film thereof.

As described above, the n-channel TFT 40
1, p-channel TFT 402, n-channel TFT 4
03 and a pixel portion 407 including a pixel TFT 404 and a storage capacitor 405 can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The n-channel TFT 40 of the driving circuit 406
Reference numeral 1 denotes a third impurity region 14 overlapping the channel formation region 170 and the second shape conductive layer 129 forming the gate electrode.
0 (GOLD region), a second impurity region 135 (LDD region) formed outside the gate electrode, and a first impurity region 145 functioning as a source region or a drain region.
have. In the p-channel TFT 402, a channel formation region 171, a fourth impurity region 155 overlapping the second shape conductive layer 130 forming a gate electrode, a fourth impurity region 154 formed outside the gate electrode, a source region Alternatively, a fourth impurity region 153 functioning as a drain region is provided. In the n-channel TFT 403, a channel formation region 172 and a third impurity region 142 overlapping with the second shape conductive layer 131 forming a gate electrode
(GOLD region), a second region formed outside the gate electrode
Impurity region 137 (LDD region) and a first impurity region 147 functioning as a source region or a drain region.

In the pixel TFT 404 in the pixel portion, a channel formation region 173, a third impurity region 143 (GOLD region) overlapping the second shape conductive layer 132 forming a gate electrode, and a third impurity region 143 formed outside the gate electrode. And a second impurity region 138 (LDD region) and a first impurity region 148 functioning as a source region or a drain region.
The semiconductor layers 156 to 159 functioning as one electrode of the storage capacitor 405 are each doped with an impurity element imparting p-type at the same concentration as the fourth impurity region. The storage capacitor 405 is formed by using an insulating film (the same film as the gate insulating film) as a dielectric,
56 to 159.

FIG. 9 is a top view of a pixel portion of an active matrix substrate manufactured in this embodiment. 5 to 8.
Are assigned the same reference numerals. A chain line AA ′ in FIG. 9 corresponds to a cross-sectional view cut along a chain line AA ′ in FIG. 9 corresponds to a cross-sectional view taken along a dashed line BB ′ in FIG.

As described above, in the active matrix substrate having the pixel structure of this embodiment, the first electrode 132 partially functioning as a gate electrode and the gate wiring 168 are formed in different layers, and the gate wiring 168 It is characterized in that the semiconductor layer is shielded from light.

In the pixel structure of this embodiment, the end of the pixel electrode is arranged so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

The surface of the pixel electrode of this embodiment may be made uneven by a known method, for example, a sandblasting method or an etching method, to prevent specular reflection and increase the whiteness by scattering the reflected light. desirable.

With the above-described pixel structure, a pixel electrode having a large area can be arranged, and the aperture ratio can be improved.

Further, according to the steps shown in this embodiment, the number of photomasks required for manufacturing the active matrix substrate is five (the semiconductor layer pattern mask, the first wiring pattern mask (the first electrode 132 and the second Electrode 133, the source wiring 134), a pattern mask for forming a source region and a drain region of a p-type TFT, a pattern mask for forming a contact hole, and a second wiring pattern mask (pixel electrode 1).
69, the connection electrode 167, and the gate wiring 168)). As a result, the process can be shortened, which can contribute to a reduction in manufacturing cost and an improvement in yield.

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 3 will be described below.
FIG. 10 is used for the description.

First, according to the third embodiment, after an active matrix substrate in the state shown in FIG. 8 is obtained, an alignment film 567 is formed on the active matrix substrate shown in FIG. 8, and a rubbing process is performed. In this embodiment, before forming the alignment film 567,
A columnar spacer 57 for maintaining a substrate interval by patterning an organic resin film such as an acrylic resin film.
2 was formed at the desired position. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 569 is prepared. According to the first embodiment, the coloring layers 570 and 57
1. A flattening film 573 is formed. The second colored portion is formed by partially overlapping the red colored layer 570 and the blue colored layer 571. Although not shown in FIG. 10, a first light-shielding portion is formed by partially overlapping a red coloring layer and a green coloring layer.

Next, a counter electrode 576 was formed in the pixel portion, an alignment film 574 was formed on the entire surface of the counter substrate, and a rubbing process was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are sealed with a sealant 568.
Paste in. A filler is mixed in the sealant 568, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer 572. Thereafter, a liquid crystal material is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix liquid crystal display device shown in FIG. 10 is completed.

In this embodiment, the substrate shown in the third embodiment is used. Therefore, FIG. 9 shows a top view of the pixel portion of the third embodiment.
Now, at least the gate wiring 168 and the pixel electrode 169,
177, the gap between the gate wiring 168 and the connection electrode 167, and the gap between the connection electrode 167 and the pixel electrode 169 need to be shielded from light. In the present embodiment, the opposing substrate is bonded to the element substrate such that the first light-shielding portion and the second light-shielding portion overlap with those positions where light is to be shielded.

FIG. 11 is a simplified diagram showing a part of a pixel portion of a completed liquid crystal display device. In FIG. 11, the colored layer (B) 12 is formed so as to overlap the pixel electrode 169 indicated by the chain line. Note that in FIG. 11, FIG.
The same reference numerals are used for portions corresponding to. Also, the pixel electrode 1
69 and the adjacent pixel electrode 177, the second light shielding portion 1
6 is shaded. The second light shielding portion 16 is formed by overlapping the colored layer (B) and the colored layer (R). The second light-shielding portion 16 is connected to the pixel TF of the adjacent pixel (R).
T is also shielded from light. Further, the source wiring 13 shown by a dotted line
An end of the colored layer (B) 12 and an end of the colored layer (G) 11 are formed on 4. The first light-shielding portion 15 is formed by overlapping the colored layer (G) and the colored layer (R). In FIG. 11, the patterning was performed so that the end of the colored layer (B) overlapping the source wiring and the end of the colored layer (G) were in contact with each other. Similarly, patterning was performed so that the end of the colored layer (R) overlapping the source wiring and the end of the colored layer (G) were in contact with each other.

As described above, without forming a black mask, the gap between each pixel is formed by the first light shielding portion 15 or the second light shielding portion 15.
The number of steps can be reduced by shielding the light with the light shielding unit 16.

[Embodiment 5] The structure of an active matrix liquid crystal display device (FIG. 10) obtained by using Embodiment 4 will be described with reference to the top view of FIG. Note that the same reference numerals are used for the portions corresponding to FIG.

A top view shown in FIG. 12 shows a pixel portion, a driving circuit, and an FPC (Flexible Printed Wiring Board: Flexible PWB).
rinted circuit), and a wiring 204 connecting the external input terminal to the input section of each circuit.
An active matrix substrate 201 on which
The counter substrate 202 on which the coloring layer and the like are formed is the sealing material 5
68.

On the upper surface of the gate wiring side driving circuit 205 and the source wiring side driving circuit 206, a light shielding portion 2 in which a red color filter or a red and blue coloring layer is laminated on the counter substrate side.
07 is formed. In the coloring layer 208 formed on the counter substrate side over the pixel portion 407, a coloring layer of each color of red (R), green (G), and blue (B) is provided corresponding to each pixel. At the time of actual display, a red (R) colored layer, a green (G) colored layer, and a blue (B) colored layer
Color display is formed by colors, and the arrangement of the colored layers of these colors is arbitrary.

FIG. 13A is a sectional view taken along line EE ′ of the external input terminal 203 shown in FIG. The external input terminal is formed on the active matrix substrate side,
A wiring 209 formed in the same layer as a pixel electrode is connected to a wiring 211 formed in the same layer as a gate wiring via an interlayer insulating film 210 in order to reduce interlayer capacitance and wiring resistance and prevent a failure due to disconnection. .

Further, the base film 2 is connected to the external input terminal.
12 and wiring 213 are anisotropic conductive resin 2
14 are pasted together. Further, the mechanical strength is enhanced by the reinforcing plate 215.

FIG. 13 (B) shows a detailed view of FIG.
2A is a cross-sectional view of the external input terminal shown in FIG. A wiring 21 in which an external input terminal provided on the active matrix substrate side is formed in the same layer as the first electrode and the source wiring
1 and a wiring 209 formed in the same layer as the pixel electrode. Of course, this is an example showing the configuration of the terminal portion, and the terminal portion may be formed with only one of the wires. For example, in the case where the wiring 211 is formed using the same layer as the first electrode and the source wiring, the interlayer insulating film formed thereover needs to be removed. The wiring 209 formed in the same layer as the pixel electrode includes a Ti film 209a, an alloy film (A
(an alloy film of 1 and Ti) 209b. The FPC is formed from a base film 212 and a wiring 213. The wiring 213 and the wiring 209 formed in the same layer as the pixel electrode are made of a thermosetting adhesive 214 and conductive particles 216 dispersed therein. To form an electrical connection structure.

The active matrix type liquid crystal display device manufactured as described above can be used as a display portion of various electronic devices.

[Embodiment 6] In this embodiment, a method of manufacturing an active matrix substrate different from that of Embodiment 3 will be described with reference to FIGS.
This will be described with reference to FIGS. In the third embodiment, n
Although the impurity region is formed by adding an impurity element for imparting a mold, the present embodiment is characterized in that the number of masks is increased by one to form a source region or a drain region of an n-channel TFT.

Since other configurations have already been described in the third embodiment, the detailed configuration is referred to in the third embodiment, and the description is omitted here.

First, the same state as in FIG. 1A is obtained according to the third embodiment. The drawing corresponding to FIG. 1A is FIG.
And the same code was used.

Next, masks 601 to 607 made of resist are formed by photolithography, and a first etching process for forming electrodes and wirings is performed.
In addition, Cl ₂ , BCl ₃ , S
Chlorine gas such as iCl ₄ , CCl ₄ or C
A fluorine-based gas typified by F ₄ , SF ₆ , NF ₃ , or the like, or O ₂ can be used as appropriate. In this embodiment, the IC
Using a P etching method, CF ₄ and C are used as etching gases.
Using l ₂ , RF power (13.56 MHz) of 500 W was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. 20W on substrate side (sample stage)
(13.56 MHz), and a substantially negative self-bias voltage is applied. Under the etching conditions in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

By the first etching process, the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, the W film and T
The aN film is etched to form the first shape conductive layers 608 to 608.
613 (first conductive layers 608a to 613a and second conductive layers 608b to 613b) are formed. Reference numeral 614 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 608 to 613 is etched by about 20 to 50 nm to form a thinned area. (FIG. 14 (B))

Next, a mask 601 to resist is formed.
A second etching process is performed without removing 607. Using CF ₄ , Cl _2, and O _{2 as} etching gases, a 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma, and etching was performed. A 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. The W film is etched under these etching conditions.

The W film is anisotropically etched by the second etching process, and the TaN film, which is the first conductive layer, is slightly etched at a lower etching rate than the W film to form the second shape conductive layer. 615-620 (first conductive layers 615a-620a and second conductive layers 615b-620
b) is formed. Reference numeral 621 denotes a gate insulating film, and a region which is not covered with the second shape conductive layers 615 to 620 is etched and thinned.

Next, a first doping process is performed. The doping treatment may be performed by an ion doping method or an ion implantation method. In this case, the condition of the high acceleration voltage is n
Doping with an impurity element for giving a mold. As the impurity element imparting n-type, an element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used. Here, phosphorus (P) is used. For example, when the acceleration voltage is 70 to 120 k
eV, and impurity regions (A) 622 to 626 are formed. (FIG. 14C) In the doping, the second shape conductive layers 615b to 619b are used as a mask for the impurity element, and the impurity element is also added to the semiconductor layer below the tapered portions of the second conductive layers 615a to 619a. Doping to be performed. Of the impurity regions (A) 622 to 626 thus formed in a self-aligned manner, the conductive layer 615
To 622a, 623a, 6
24a, 625a, and 626a, and the conductive layers 615-6
The impurity regions which do not overlap with 19 are 622b, 623b, 6
24b, 625b, and 626b.

Next, after removing the resist mask, the gate insulating film 621 is selectively removed using the conductive layers 615 to 619 as a mask to remove the insulating layers 627a and 627.
27b and 627c are formed. Further, the insulating layer 627a,
The resist mask used for forming the second shape conductive layers 615 to 619 may be removed at the same time as the formation of the 627b and 627c. (FIG. 14 (D))

Next, after forming resist masks 628 and 629 by using photolithography, a second doping process is performed. In this case, the semiconductor layer is doped with an impurity element imparting n-type as a condition of a higher acceleration voltage and a lower acceleration voltage than the first doping treatment. The impurity regions (B) 630 to 634 have 1 × 10 ²⁰ to
An impurity element for imparting n-type is added in a concentration range of 1 × 10 ²¹ atoms / cm ³ . (FIG. 15 (A))

Thus, the impurity region (B) 630 serving as the source or drain region of the n-channel TFT,
632 and 633 could be formed. In the pixel portion, the impurity region (A) 62 overlapping with the conductive layer 618 is provided.
A region 636 that does not overlap with the conductive layer 618 is formed between 5b and the impurity region 633. This area 636 is n
Functions as an LDD region of a channel type TFT. Also,
The impurity element added to the impurity regions (B) 631 and 634 is added in order to reduce the nickel concentration in the semiconductor layer which mainly serves as a channel formation region in a later gettering step.

After the masks 628 and 629 made of resist are removed as in the third embodiment, masks 637 to 639 made of resist are newly formed and a third doping process is performed. (FIG. 15B) By this third doping treatment, an impurity region (C) in which an impurity element imparting a conductivity type opposite to the one conductivity type is added to a semiconductor layer serving as an active layer of a p-channel TFT. ) 640-644 are formed. Using the second conductive layers 616 and 619 as a mask for the impurity element, an impurity element imparting p-type is added to form an impurity region (C) in a self-aligned manner. In this embodiment, the impurity regions (C) 640 to 644 are formed by an ion doping method using diborane (B ₂ H ₆ ). Also,
As in the third embodiment, phosphorus is added at different concentrations to the impurity regions (C) 640 to 644, but the concentration of the impurity element imparting p-type is 2 × 10 ²⁰ to By performing the doping treatment at 2 × 10 ²¹ atoms / cm ³ , there is no problem because it functions as a source region and a drain region of a p-channel TFT.

Next, similarly to the third embodiment, the masks 637 to 639 made of resist are removed, and a first interlayer insulating film 645 covering the entire surface is formed. This first interlayer insulating film 64
5 is formed with an insulating film containing silicon with a thickness of 100 to 200 nm by using a plasma CVD method or a sputtering method.

Next, as shown in FIG. 15C, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method,
400-700 ° C in a nitrogen atmosphere, typically 500-
What is necessary is just to carry out at 550 degreeC. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the activation treatment, nickel used as a catalyst during crystallization is gettered in impurity regions (B) 630 to 634 containing high-concentration phosphorus, and mainly the channel is formed. The nickel concentration in the semiconductor layer serving as a formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film 635. However, the conductive layer 615
In the case where the wiring material used in Nos. 619 is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment. Preferably, an activation treatment is performed.

Through the above steps, impurity regions are formed in the respective semiconductor layers. The second shape conductive layers 615 to 618 overlapping with the semiconductor layer function as gate electrodes. Further, 620 functions as a source wiring, and 619 functions as a second electrode for forming a storage capacitor.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

A heat treatment (300 to 550 ° C.) is performed using hydrogen contained in an interlayer insulating film made of a silicon nitride film.
For 1 to 12 hours) to hydrogenate the semiconductor layer. In this case, 41
By performing heat treatment at 0 ° C. for one hour, dangling bonds in the semiconductor layer can be terminated by hydrogen contained in the interlayer insulating film.

In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 646 made of an organic insulating material is formed on the first interlayer insulating film 645. Next, a contact hole reaching the source wiring 134 and each of the impurity regions (B) and (C) 630, 632, 6
Patterning for forming contact holes reaching 33, 640 and 643 is performed.

Then, in the driver circuit, wirings 647 to 652 electrically connected to the impurity region (B) or the impurity region (C) are formed. Note that these wirings are formed by patterning a laminated film of a 50-nm-thick Ti film and a 500-nm-thick alloy film (an alloy film of Al and Ti).

In the pixel portion, the pixel electrode 65
6, a gate wiring 654 and a connection electrode 653 are formed.
(FIG. 16) This connection electrode 653 allows the source wiring 620
Is electrically connected to the pixel TFT. Further, the gate wiring 654 is connected to the first electrode (the conductive layer 6 having the second shape).
18) and an electrical connection is formed. In addition, the pixel electrode 6
In 56, an electrical connection is formed with the drain region of the pixel TFT, and further, an electrical connection is formed with the semiconductor layer 643 functioning as one electrode forming a storage capacitor.

As described above, the n-channel TFT, p
A driver circuit including a channel TFT and an n-channel TFT and a pixel portion including a pixel TFT and a storage capacitor can be formed over the same substrate. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

The semiconductor layer of the n-channel TFT of the driver circuit has a channel formation region and an impurity region (A) 622b (G) overlapping with a second shape conductive layer 615 forming a gate electrode.
OLD region) and an impurity region (B) 630 functioning as a source region or a drain region. Also, p
The semiconductor layer of the channel TFT has a channel formation region, an impurity region (C) 642 overlapping with the second shape conductive layer 616 forming a gate electrode, and an impurity region (C) 640 functioning as a source or drain region. ing.
The semiconductor layer of the n-channel TFT is a channel formation region, an impurity region (A) 624b (GOLD region) overlapping with the second shape conductive layer 617 forming a gate electrode, and an impurity region functioning as a source or drain region. (B) 632.

The semiconductor layer of the pixel TFT in the pixel portion is a channel forming region and a second shape conductive layer 6 forming a gate electrode.
18, an impurity region (A) 625b (a GOLD region), an impurity region 636 formed outside the gate electrode.
(LDD region) and an impurity region (B) 633 functioning as a source region or a drain region. Also,
A semiconductor layer 643 functioning as one electrode of the storage capacitor;
644 has the same concentration as the impurity region (C) and has
An impurity element for imparting a mold is added. The storage capacitor is formed using the insulating layer 627c (the same film as the gate insulating film) as a dielectric, the second electrode 619, and the semiconductor layers 643 and 644.
And formed.

A liquid crystal display device can be obtained by using the active matrix substrate manufactured in the present embodiment and following the steps in the fourth embodiment.

This embodiment can be combined with any of Embodiments 1 to 5.

[Embodiment 7] In this embodiment, an example will be described in which a pixel electrode having an uneven surface is formed without increasing the number of manufacturing steps. For the sake of simplicity, only differences from the third embodiment will be described below.

In the third embodiment, a base film 101, an insulating film 128, a first interlayer insulating film 159, and a second interlayer insulating film 160 are laminated on a substrate in a region below a pixel electrode serving as a display region. However, in this embodiment, at the same time when the TFT is manufactured, the convex portions 7 shown in FIG.
01 and 702, and the pixel electrodes formed thereon are made uneven. The pixel TFT 404 and the storage capacitor 405 in FIG. 8 and the pixel TF in FIG.
The T801 and the storage capacitor 802 are manufactured in the same manufacturing process.

The projections 701 and 702 are formed simultaneously with the patterning of the semiconductor layer and the gate electrode in the manufacturing process of the pixel TFT 404 shown in the third embodiment. In addition,
The arrangement of the protrusions is not particularly limited as long as it is a region below a pixel electrode serving as a display region of the pixel portion 803, and the size of the protrusions (the area when viewed from above) is not particularly limited, but is 1 μm.
^{2 to} 400 μm ² , preferably 25 to 100 μm
² is fine. In addition, it is desirable that the size of the convex portion be random, since the reflected light is more scattered.

As described above, the protrusions 701 and 702 are
It can be formed by changing the mask without increasing the number of masks. In the present embodiment, the mask used in the third embodiment is changed, and two types of square convex portions 701 and 702 shown in FIG. 17A are formed in the display area, and the arrangement is randomized.

Although FIG. 18 shows a rectangular shape, the shape is not particularly limited, and the cross section in the radial direction may be polygonal or may not be symmetrical. For example, any of the shapes shown in FIGS. Further, the convex portions may be arranged regularly or irregularly.

The surface of the insulating film 804 covering the projections 701 and 702 thus formed was formed with irregularities, and the pixel electrode 805 formed thereon was also formed with irregularities. The height of the projection of the pixel electrode 805 is 0.3 to 3 μm, preferably 0.5 to 1.5 μm. Due to the irregularities formed on the surface of the pixel electrode 805, as shown in FIG. 19, when the incident light was reflected, the light could be scattered.

As the insulating film 804, an inorganic insulating film or an organic resin film can be used. This insulating film 804
It is also possible to adjust the curvature of the unevenness of the pixel electrode by the above material. When an organic resin film is used as the insulating film 804, the viscosity is 10 to 1000 cp, preferably 4 to 1000 cp.
Using a material having a size of 0 to 200 cp, the protrusions 701 and 70
A material having irregularities on the surface under the influence of 2 is used. However, if a solvent that hardly evaporates is used, unevenness can be formed even if the viscosity of the organic resin film is low.

Next, in this example, an alignment film 806 covering the pixel electrode was formed, and a rubbing process was performed.

Next, the counter substrate shown in Embodiment 1 is prepared. In FIG. 19, reference numeral 808 denotes a counter substrate, and coloring layers 809 and 81 are formed on the counter substrate 808 according to the first embodiment.
0, a flattening film 811 is formed. The second colored portion is formed by partially overlapping the red coloring layer 809 and the blue coloring layer 810. Although not shown in FIG. 19, the first light-shielding portion is formed by partially overlapping a red coloring layer and a green coloring layer.

Next, a counter electrode 812 was formed in the pixel portion, an alignment film 813 was formed on the entire surface of the counter substrate, and a rubbing process was performed.

Further, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded with a sealant. A filler is mixed in the sealant, and the filler and the columnar spacer are spaced at a uniform interval.
Two substrates are bonded. Thereafter, a liquid crystal material 807 is injected between the two substrates, and completely sealed with a sealing agent (not shown). A known liquid crystal material may be used for the liquid crystal material 807. Thus, the active matrix type liquid crystal display device shown in FIG. 19 is completed.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 8] This embodiment shows another example different from the embodiment 7 in which the pixel electrode having the unevenness on the surface is formed. For the sake of simplicity, only differences from the seventh embodiment will be described below. In FIG. 20, the same reference numerals are used for the portions corresponding to FIG.

In this embodiment, as shown in FIG. 20, convex portions 900 and 901 having different heights are formed.

The protrusions 900 and 901 can be formed by changing the mask of the seventh embodiment without increasing the number of masks. In FIG. 20, when patterning the semiconductor layer, a mask in which a semiconductor layer is not formed in the convex portion 901 is used. Therefore, the height of the convex portion 901 is smaller than that of the convex portion 900 by the thickness of the semiconductor layer. In the present embodiment, the mask used for patterning the semiconductor layer used in the seventh embodiment is changed, and two types of square convex portions 90 having different heights are used.
0 and 901 were randomly formed in a portion to be a display area.

By doing so, it is possible to increase the difference in height of the unevenness formed on the surface of the pixel electrode without increasing the number of manufacturing steps, and to further scatter reflected light.

This embodiment can be freely combined with any one of Embodiments 1 to 5.

[Embodiment 9] In Embodiments 7 and 8, an example of manufacturing a pixel electrode using a projection formed simultaneously with the manufacture of a top gate type TFT is shown.
A manufacturing example of a pixel electrode using a projection formed at the same time as the manufacture of an inverted staggered TFT will be described with reference to FIGS.

First, a gate wiring 1000 is formed using a first mask (first photomask). At this time, a metal layer 1001 made of the same material as the gate wiring is formed in a region to be a display region.
To form

Next, the gate wiring 1000 and the metal layer 1
001, an insulating film (gate insulating film) 1002, a first amorphous semiconductor film, a second amorphous semiconductor film containing an impurity element imparting n-type conductivity, and a first conductive film are sequentially formed. Lamination is formed. Note that a microcrystalline semiconductor film may be used instead of the amorphous semiconductor film, or a microcrystalline semiconductor containing an n-type impurity element instead of the n-type impurity element. A membrane may be used. Further, these films can be formed in a plurality of chambers or in the same chamber without being continuously exposed to the atmosphere by a sputtering method or a plasma CVD method. By avoiding exposure to the atmosphere, contamination with impurities can be prevented.

Next, the first conductive film is patterned with a second mask (the second photomask) to form a wiring made of the first conductive film (which will later become a source wiring and an electrode (drain electrode)). Then, the second amorphous semiconductor film is patterned to form a second amorphous semiconductor film containing an impurity element imparting n-type, and the first amorphous semiconductor film is patterned to form a second amorphous semiconductor film. One amorphous semiconductor film is formed. Similarly, a first amorphous semiconductor film, a second amorphous semiconductor film including an impurity element imparting n-type conductivity, and the first conductive film are left over the metal layer 1001. Perform patterning. In this patterning, in order to improve the coverage of the second conductive film to be formed later, the etching was performed so that the end portions became stepwise as shown in FIG.

The shapes of the metal layer 1001 and the laminate (convex portion) formed thereon are not particularly limited, and the cross section in the radial direction may be polygonal or not symmetrical. Is also good. For example, any of the shapes shown in FIGS. Also, the metal layer 1
001 and the laminate (convex portion) formed thereon may be arranged regularly or irregularly. Also, the metal layer 1
The height of 001 and the laminate (convex portion) formed thereon is 0.3 to 3 μm, preferably 0.5 to 1.5 μm.

Next, a resist mask is formed in the terminal portion using a shadow mask, and after selectively removing the insulating film 1002 covering the pad portion of the terminal portion, the resist mask is removed. Further, instead of the shadow mask, a resist mask may be formed by a screen printing method and used as an etching mask.

Thereafter, a second conductive film is formed on the entire surface.
Note that as the second conductive film, a reflective conductive film,
For example, a material film made of Al or Ag is used.

Next, the second conductive film is patterned with a third mask (third photomask) to form a pixel electrode 1004 made of the second conductive film, and the conductive film is patterned to form a source wiring. 1003 and an electrode (drain electrode) 1009 are formed, and the second amorphous semiconductor film including the impurity element imparting n-type by patterning the second amorphous semiconductor film including the impurity element imparting n-type A source region 1008 and a drain region 1009 are formed, and the first amorphous semiconductor film is partially removed to form a first amorphous semiconductor film 1006.

Next, an alignment film 1005 was formed, and a rubbing treatment was performed.

With such a configuration, the pixel TFT
When manufacturing the portion, the number of photomasks used in the photolithography technique can be three.

In addition, with such a structure, the insulating film formed over the metal layer 1001, the first amorphous semiconductor film, and the second amorphous film containing an impurity element imparting n-type are formed. Since the pixel electrode 1004 is formed to have projections and depressions by a stacked body (projection) including the semiconductor film and the first conductive film, the surface of the pixel electrode 1004 can be formed without increasing the number of manufacturing steps. The light scattering property can be achieved by providing the surface with irregularities.

Next, the counter substrate shown in Embodiment 1 is prepared. In FIG. 21, reference numeral 1010 denotes a counter substrate, and according to the first embodiment, a coloring layer 1011 is formed on the counter substrate 1010;
1012, a flattening film 1013 is formed. A part of the red coloring layer 1011 and the blue coloring layer 1012
A light shielding part is formed. Although not shown in FIG. 21, the first light-shielding portion is formed by partially overlapping a red coloring layer and a green coloring layer.

Next, a counter electrode 1014 was formed in the pixel portion, an alignment film 1015 was formed on the entire surface of the counter substrate, and rubbing was performed.

[0176] The active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are bonded with a sealant. A filler is mixed in the sealant, and the filler and the columnar spacer are spaced at a uniform interval.
Two substrates are bonded. Thereafter, a liquid crystal material 1016 is injected between the two substrates, and completely sealed with a sealing agent (not shown). As the liquid crystal material 1016, a known liquid crystal material may be used. Thus, the active matrix type liquid crystal display device shown in FIG. 21 is completed.

FIG. 22 is a diagram for explaining the arrangement of the pixel portion and the terminal portion of the active matrix substrate. A pixel portion 1111 is provided over a substrate 1110. In the pixel portion, a gate wiring 1108 and a source wiring 1107 are formed so as to intersect, and an n-channel TFT 1101 connected thereto is provided for each pixel. A pixel electrode 1004 and a storage capacitor 1102 are provided on the drain side of the n-channel TFT 1101.
Are connected, and the other terminal of the storage capacitor 1102 is connected to the capacitor wiring 1109. n-channel type TFT110
1 and the storage capacitor 1102 have the same structure as the n-channel TFT or the storage capacitor shown in FIG.

An input terminal 1105 for inputting a scanning signal is formed at one end of the substrate, and is connected to a gate wiring 1108 by a connection wiring 1106. An input terminal 1103 for inputting an image signal is formed at the other end, and is connected to a source wiring 1107 by a connection wiring 1104. Gate wiring 1108, source wiring 110
7. A plurality of capacitor wirings 1109 are provided according to the pixel density. Further, an input terminal portion 1112 for inputting an image signal and a connection wiring 1113 are provided.
3 may be alternately connected to the source wiring. The input terminal units 1103, 1105, and 1112 may be provided in an arbitrary number, and may be appropriately determined by a practitioner.

This embodiment corresponds to the first embodiment or the second embodiment.
Can be combined with

[Embodiment 10] In this embodiment, an example will be described in which a pixel electrode having an uneven surface is formed without increasing the number of manufacturing steps. For the sake of simplicity, only differences from the ninth embodiment will be described below. The same reference numerals are used for portions corresponding to FIG.

In the present embodiment, as shown in FIG. 23, convex portions 1201 and 1202 having different heights are formed.

The projections 1201 and 1202 can be formed by changing the mask of the ninth embodiment without increasing the number of masks. In FIG. 23, when patterning the gate electrode, a mask in which a metal layer is not formed in the protrusion 1202 is used.
It is lower than 1 by the thickness of the metal layer. In this embodiment, the mask used for patterning the metal layer used in the ninth embodiment is changed, and two types of convex portions 1201 having different heights are used.
Reference numeral 1202 was randomly formed at a position to be a display area.

Thus, without increasing the number of manufacturing steps, it is possible to increase the difference in height of the unevenness formed on the surface of the pixel electrode 1200 and to scatter reflected light.

This embodiment can be combined with Embodiment 1 or Embodiment 2.

[Embodiment 11] The TFT formed by carrying out any one of the above embodiments 1 to 10 can be used for various electro-optical devices (active matrix liquid crystal display, active matrix EC display). it can. That is, the present invention can be applied to all electronic devices in which the electro-optical device is incorporated in the display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a car stereo,
Examples include a personal computer and a portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like). Examples of these are shown in FIGS.

FIG. 26A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 26B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 26C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 26D shows a goggle type display, which includes a main body 2301, a display portion 2302, and an arm portion 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 26E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 26F shows a digital camera, which includes a main body 2501, a display portion 2502, an eyepiece portion 2503, operation switches 2504, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 27A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 27B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 27C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 10.

[0197]

According to the present invention, a light-shielding portion is formed by a laminated film (R + B or R + G) composed of two colored layers. As a result, the step of forming a black matrix can be omitted.

[Brief description of the drawings]

1A and 1B are a top view and a cross-sectional view illustrating an arrangement of a coloring layer.

FIG. 2 is a cross-sectional view of a coloring layer.

FIG. 3 is a graph showing the reflectance of a stacked colored layer.

FIG. 4 is a diagram showing overlap between a wiring and a coloring layer.

FIG. 5 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 6 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 7 illustrates a top view of a pixel.

FIG. 8 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 9 illustrates a top view of a pixel.

FIG. 10 is a diagram showing a cross-sectional structure diagram of an active matrix liquid crystal display device.

FIG. 11 is a diagram showing an arrangement of a coloring layer.

FIG. 12 is a diagram showing an appearance of an AM-LCD.

FIG. 13 is a diagram showing terminal portions of an AM-LCD.

FIG. 14 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 15 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 16 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 17 is a diagram showing a top surface shape of a convex portion.

FIG. 18 illustrates a top view of a pixel.

FIG. 19 is a diagram illustrating a cross-sectional structure diagram of an active matrix liquid crystal display device.

FIG. 20 is a diagram illustrating a cross-sectional structure diagram of an active matrix liquid crystal display device.

FIG. 21 is a diagram illustrating a cross-sectional structure diagram of an active matrix liquid crystal display device.

FIG. 22 illustrates an arrangement of a pixel portion and a terminal portion of an active matrix substrate.

FIG. 23 is a diagram showing a cross-sectional structure diagram of an active matrix liquid crystal display device.

FIG. 24 is a graph showing absorptance to a non-single-crystal silicon film.

FIG. 25 is a graph showing reflectance of a single colored layer.

FIG 26 illustrates an example of an electronic device.

FIG. 27 illustrates an example of an electronic device.

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2H091 FA03Y FA14Y FA35Y FB08 FC10 FC26 FD04 FD21 GA13 LA13 LA15 2H092 GA59 HA05 JA25 KA02 KA04 KB04 KB26 MA13 MA29 MA30 NA27 PA08 PA09 RA05 5C094 AA08 AA13 CA48 DA09 DA12 DA13 EA04 EA05 EA06 EB04 ED03 ED15 FA01 GB10

Claims (11)

[Claims] 1. A first light-shielding portion comprising a laminate of a first colored layer and a second colored layer, and a second light-shielding portion comprising a laminate of the first colored layer and a third colored layer. An electro-optical device, comprising: 2. A TFT, a first light-shielding portion composed of a laminate of a first colored layer and a second colored layer, and a second light-shielded portion composed of a laminate of the first colored layer and a third colored layer. An electro-optical device, wherein the first light-shielding portion and the second light-shielding portion are formed so as to overlap at least with a channel forming region of the TFT. 3. A plurality of pixel electrodes, a first light-shielding portion comprising a first colored layer and a second colored layer, and a first light-shielding portion comprising a first colored layer and a third colored layer. The first light-shielding portion and the second light-shielding portion are formed so as to overlap between any pixel electrode and a pixel electrode adjacent to the pixel electrode. Electro-optical device characterized. 4. The electro-optical device according to claim 1, wherein the amount of reflected light from the first light-shielding portion and the amount of light reflected from the second light-shielding portion are different from each other. 5. The electro-optical device according to claim 1, wherein the first colored layer is red. 6. The electro-optical device according to claim 1, wherein the second colored layer is blue. 7. The electro-optical device according to claim 1, wherein the third colored layer is green. 8. The electro-optical device according to claim 1, wherein the third colored layer has a stripe shape. 9. The electro-optical device according to claim 1, wherein the first light-shielding portion and the second light-shielding portion are provided on a counter substrate. 10. The method according to claim 1, wherein
The electro-optical device is characterized in that the pixel electrode is a reflective liquid crystal display device in which a pixel electrode is composed of a film containing Al or Ag as a main component or a laminated film thereof. 11. The electro-optical device according to claim 1, wherein the electro-optical device is a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, or an electronic game machine.