JP2002009001A - Compound semiconductor epitaxial wafer and its manufacturing method - Google Patents

Compound semiconductor epitaxial wafer and its manufacturing method

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Publication number
JP2002009001A
JP2002009001A JP2000190051A JP2000190051A JP2002009001A JP 2002009001 A JP2002009001 A JP 2002009001A JP 2000190051 A JP2000190051 A JP 2000190051A JP 2000190051 A JP2000190051 A JP 2000190051A JP 2002009001 A JP2002009001 A JP 2002009001A
Authority
JP
Japan
Prior art keywords
compound semiconductor
epitaxial wafer
conductive layer
semiconductor epitaxial
type conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000190051A
Other languages
Japanese (ja)
Inventor
Jiro Wada
次郎 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP2000190051A priority Critical patent/JP2002009001A/en
Publication of JP2002009001A publication Critical patent/JP2002009001A/en
Pending legal-status Critical Current

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  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor epitaxial wafer which is uniform in distribution of carrier concentration through its surface, with a film formed on its surface kept uniform in thickness and composition distribution through the surface, and to provide a method of manufacturing the same. SOLUTION: When an N-type conductive layer 2 is grown on a semiconductor substrate 1 through an MOVPE method, a mixture of Si2H6 and H2Se as N-type dopant is fed to enable Si and Se to reside in the N-type conductive layer. Si2H6 and H2Se as N-type dopant are different from each other in doping efficiency at growth temperatures, so that Si2H6 and H2Se indicate the opposed doping distributions to a temperature distribution through the surface of the wafer 1. Therefore, Si2H6 and H2Se are supplied at the same time, by which a temperature distribution is canceled through the surface of the wafer, and a carrier concentration gets uniform.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電界効果型トラン
ジスタ用ウェハ、ヘテロバイポーラトランジスタ用ウェ
ハ、および光素子用ウェハ等の化合物半導体エピタキシ
ャルウェハおよびその製造方法に関し、特に、膜厚や組
成の面内分布の均一性を維持しながら、キャリア濃度の
面内分布が均一な化合物半導体エピタキシャルウェハお
よびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor epitaxial wafer such as a wafer for a field effect transistor, a wafer for a hetero bipolar transistor, and a wafer for an optical device, and a method for manufacturing the same. The present invention relates to a compound semiconductor epitaxial wafer having a uniform carrier concentration in-plane distribution while maintaining uniform distribution, and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来の化合物半導体エピタキシャルウェ
ハは、半絶縁性GaAs基板上に有機金属気相成長(M
OVPE:Metal Organic Vaper Phase Epitaxy)法に
より1層以上のエピタキシャルウェハを成長させる場合
に、n型導電性層のドーパント原料として1種類のドー
パント原料を供給して作製されている。
2. Description of the Related Art A conventional compound semiconductor epitaxial wafer is formed on a semi-insulating GaAs substrate by metal organic chemical vapor deposition (M.P.M.).
When one or more epitaxial wafers are grown by the metal organic vapor phase epitaxy (OVPE) method, one kind of dopant material is supplied as a dopant material for the n-type conductive layer.

【0003】[0003]

【発明が解決しようとする課題】しかし、従来の化合物
半導体エピタキシャルウェハによると、n型導電性層の
ドーパント原料として1種類しか用いていないため、成
長条件(成長速度、成長温度、III族原料、V族原料、
成長圧力等)によってはウェハ面内のキャリア濃度分布
が悪くなることがある。一方、キャリア濃度の面内分布
を良くするために成長条件を変えると、その条件で面内
分布が均一であった膜厚分布や組成分布が悪くなること
がある。
However, according to the conventional compound semiconductor epitaxial wafer, only one kind of dopant material is used as the dopant material for the n-type conductive layer, so that the growth conditions (growth rate, growth temperature, group III material, Group V raw material,
(E.g., growth pressure), the carrier concentration distribution in the wafer surface may be deteriorated. On the other hand, when the growth conditions are changed to improve the in-plane distribution of the carrier concentration, the film thickness distribution and the composition distribution whose in-plane distribution is uniform under the conditions may be deteriorated.

【0004】従って、本発明の目的は、膜厚や組成の面
内分布の均一性を維持しながら、キャリア濃度の面内分
布が均一な化合物半導体エピタキシャルウェハおよびそ
の製造方法を提供することにある。
Accordingly, an object of the present invention is to provide a compound semiconductor epitaxial wafer having a uniform in-plane distribution of the carrier concentration while maintaining the uniformity of the in-plane distribution of the film thickness and the composition, and a method of manufacturing the same. .

【0005】[0005]

【課題を解決するための手段】本発明は、上記目的を達
成するため、III−V族化合物半導体基板上に有機金属
気相成長(MOVPE)法によってn型導電性層を成長
させた化合物半導体エピタキシャルウェハにおいて、前
記n型導電性層は、少なくとも1層にSiおよびSeが
存在することを特徴とする化合物半導体エピタキシャル
ウェハを提供する。上記構成によれば、n型導電性層を
成長させる場合に、n型ドーパントとしてSi26およ
びH2Seを供給することにより、n型導電性層中にS
iおよびSeを存在させることができる。n型ドーパン
トのSi26とH2Seは、成長温度に対してドーピン
グ効率が互いに異なるため、ウェハ面内の温度分布に対
して相反するドーピング分布を示す。従って、Si26
およびH2Seを同時に供給することにより、面内の温
度分布がキャンセルされ、キャリア濃度分布が均一にな
る。
In order to achieve the above object, the present invention provides a compound semiconductor in which an n-type conductive layer is grown on a III-V compound semiconductor substrate by metal organic chemical vapor deposition (MOVPE). In the epitaxial wafer, the n-type conductive layer provides a compound semiconductor epitaxial wafer, wherein Si and Se are present in at least one layer. According to the above configuration, when growing the n-type conductive layer, Si 2 H 6 and H 2 Se are supplied as n-type dopants, so that S
i and Se can be present. Since the doping efficiencies of the n-type dopants Si 2 H 6 and H 2 Se are different from each other with respect to the growth temperature, the doping distributions are opposite to the temperature distribution in the wafer surface. Therefore, Si 2 H 6
By simultaneously supplying H 2 Se and H 2 Se, the in-plane temperature distribution is canceled and the carrier concentration distribution becomes uniform.

【0006】本発明は、上記目的を達成するため、III
−V族化合物半導体基板上に有機金属気相成長(MOV
PE)法によってn型導電性層を成長させる化合物半導
体エピタキシャルウェハの製造方法において、前記n型
導電性層の成長は、n型ドーパントとしてSi26およ
びH2Seを供給して前記n型導電性層中にSiおよび
Seを存在させることを特徴とする化合物半導体エピタ
キシャルウェハの製造方法を提供する。
[0006] In order to achieve the above object, the present invention provides
Metalorganic vapor phase epitaxy (MOV) on -V compound semiconductor substrates
In the method of manufacturing a compound semiconductor epitaxial wafer for growing an n-type conductive layer by a PE) method, the n-type conductive layer is grown by supplying Si 2 H 6 and H 2 Se as n-type dopants. Provided is a method for manufacturing a compound semiconductor epitaxial wafer, characterized in that Si and Se are present in a conductive layer.

【0007】[0007]

【発明の実施の形態】図1は、本発明の実施の形態に係
る化合物半導体エピタキシャルウェハを示す。この化合
物半導体エピタキシャルウェハは、面方位が2°OFF
(100)の半絶縁性を有するGaAs(ガリウム砒
素)基板1上に、MOVPE法により、ドーピング原料
としてSi26(ジシラン)とH2Se(セレン化水
素)を同時に供給してn型導電性層としてのAl組成3
0%のAlGaAs(アルミニウムガリウム砒素)2を
成長させて得られる。n型導電性層中のSiとSeの存
在比率は、0.1≦([Si]/[Se])≦10が好
ましい。
FIG. 1 shows a compound semiconductor epitaxial wafer according to an embodiment of the present invention. This compound semiconductor epitaxial wafer has a plane orientation of 2 ° OFF.
On a (100) semi-insulating GaAs (gallium arsenide) substrate 1, Si 2 H 6 (disilane) and H 2 Se (hydrogen selenide) are simultaneously supplied as doping materials by MOVPE to provide n-type conductivity. Composition 3 as conductive layer
It is obtained by growing 0% AlGaAs (aluminum gallium arsenide) 2. The abundance ratio of Si and Se in the n-type conductive layer is preferably 0.1 ≦ ([Si] / [Se]) ≦ 10.

【0008】n型導電性層は、AlGaAsの他に、G
aAs(ガリウム砒素)、InGaAs(インジウムガ
リウム砒素)、InAlAs(インジウムアルミニウム
砒素)、InGaP(インジウムガリウム燐)、AlG
aInP(アルミニウムガリウムインジウム燐)、Ga
P(ガリウム燐)、AlInP(アルミニウムインジウ
ム燐)を用いることができる。
The n-type conductive layer is made of G
aAs (gallium arsenide), InGaAs (indium gallium arsenide), InAlAs (indium aluminum arsenide), InGaP (indium gallium phosphide), AlG
aInP (aluminum gallium indium phosphide), Ga
P (gallium phosphorus) and AlInP (aluminum indium phosphorus) can be used.

【0009】次に、以上のような化合物半導体エピタキ
シャルウェハの製造方法を説明する。ここでは、Ga
(III族)の原料としてTMG(トリメチルガリウ
ム)、Al(III族)の原料としてTMA(トリメチル
アルミニウム)、As(V族)の原料としてAsH
3(アルシン)を用いる。まず、図示しない反応管内の
サセプタにGaAs基板1を配置し、高周波コイルによ
りサセプタを加熱してGaAs基板1を暖める。次に、
反応管にTMG、TMAおよびAsH3ガスを供給する
とともに、これらのガス中にドーパントガスのSi26
およびH2Seを同時に流し、ガス中にSiとSeをド
ーピングしながら成長温度700℃下でGaAs基板1
上にAlGaAs層2を成長させる。
Next, a method of manufacturing the above compound semiconductor epitaxial wafer will be described. Here, Ga
TMG (trimethylgallium) as a raw material of (III), TMA (trimethylaluminum) as a raw material of Al (III), and AsH as a raw material of As (V)
3 Use (arsine). First, the GaAs substrate 1 is placed on a susceptor in a reaction tube (not shown), and the susceptor is heated by a high-frequency coil to warm the GaAs substrate 1. next,
TMG, TMA and AsH 3 gas are supplied to the reaction tube, and Si 2 H 6 as a dopant gas is contained in these gases.
And H 2 Se at the same time, and doping Si and Se in the gas while growing the GaAs substrate 1 at 700 ° C.
An AlGaAs layer 2 is grown thereon.

【0010】図2〜図4は、エピタキシャルウェハのA
lGaAsキャリア濃度面内分布をC−V測定により求
めた結果であり、図2はドーピング原料としてSi26
およびH2Seを用いた本実施の形態を示し、図3はド
ーピング原料としてSi26を用いた場合の比較例1を
示し、図4はドーピング原料としてH2Seを用いた場
合の比較例2を示す。
FIGS. 2 to 4 show A of the epitaxial wafer.
The lGaAs carrier concentration in-plane distribution is a result obtained by C-V measurements, Si 2 H 6 2 as doping material
And H 2 illustrates the present embodiment using the Se, Comparison of Figure 3 shows a comparative example 1 when using Si 2 H 6 as a doping material, 4 with H 2 Se as doping material Example 2 will be described.

【0011】キャリア濃度分布を比較すると、図3に示
す比較例1と図4に示す比較例2とでは、分布がそれぞ
れ上凸と下凸となり、相反する分布を示している。従っ
て、Si26およびH2Seの2種類のドーピング原料
を同時に供給することによって、図2に示すように、面
内のキャリア濃度分布が均一なAlGaAs層2が得ら
れる。
Comparing the carrier concentration distributions, in Comparative Example 1 shown in FIG. 3 and Comparative Example 2 shown in FIG. 4, the distributions are upwardly convex and downwardly convex, respectively. Therefore, by simultaneously supplying two types of doping materials of Si 2 H 6 and H 2 Se, an AlGaAs layer 2 having a uniform in-plane carrier concentration distribution can be obtained as shown in FIG.

【0012】なお、本発明は、n型導電性層のみなら
ず、p型導電性層においても、最適な2種類のドーパン
トが有れば、均一な面内キャリア濃度分布を有するエピ
タキシャルウェハの製造が可能となる。
It is to be noted that the present invention is directed to a method of manufacturing an epitaxial wafer having a uniform in-plane carrier concentration distribution in the p-type conductive layer as well as in the n-type conductive layer, provided that there are two kinds of optimum dopants. Becomes possible.

【0013】[0013]

【発明の効果】以上説明したように、本発明の化合物半
導体エピタキシャルウェハおよびその製造方法によれ
ば、n型導電性層を成長させる場合に、n型ドーパント
としてSi26およびH2Seを供給してn型導電性層
中にSiおよびSeを存在させているので、成長条件の
変更をする必要が無く、かつ、膜厚分布や組成分布均―
性を維持したまま、キャリア濃度分布を均一にできる。
これにより、面内分布が均一な電界効果型トランジスタ
用エピタキシャルウェハ、ヘテロバイポーラトランジス
タ用エピタキシャルウエハ、光素子用エピタキシャルウ
ェハ等を作製することができる。
As described above, according to the compound semiconductor epitaxial wafer and the method of manufacturing the same of the present invention, when growing an n-type conductive layer, Si 2 H 6 and H 2 Se are used as n-type dopants. Since Si and Se are present in the n-type conductive layer by supply, there is no need to change the growth conditions, and the film thickness distribution and composition distribution uniformity do not need to be changed.
The carrier concentration distribution can be made uniform while maintaining the properties.
Thereby, an epitaxial wafer for a field-effect transistor, an epitaxial wafer for a hetero-bipolar transistor, an epitaxial wafer for an optical element, and the like having a uniform in-plane distribution can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態に係る化合物半導体エピタ
キシャルウェハの断面図である。
FIG. 1 is a cross-sectional view of a compound semiconductor epitaxial wafer according to an embodiment of the present invention.

【図2】本発明の実施の形態に係る化合物半導体エピタ
キシャルウェハのキヤリア濃度面内分布である。
FIG. 2 shows a carrier concentration in-plane distribution of a compound semiconductor epitaxial wafer according to an embodiment of the present invention.

【図3】比較例1に係るSi26をドーピングして成長
したAlGaAs単層エピタキシャルウェハのキャリア
濃度面内分布である。
FIG. 3 is an in-plane carrier concentration distribution of an AlGaAs single-layer epitaxial wafer grown by doping with Si 2 H 6 according to Comparative Example 1.

【図4】比較例2に係るH2Seをドーピングして成長
したAlGaAs単層エピタキシャルウェハのキャリア
濃度面内分布である。
FIG. 4 shows a carrier concentration distribution in an AlGaAs single-layer epitaxial wafer grown by doping with H 2 Se according to Comparative Example 2.

【符号の説明】[Explanation of symbols]

1 GaAs基板 2 AlGaAs層 1 GaAs substrate 2 AlGaAs layer

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 4G077 AA03 BE43 BE46 BE47 DB08 EB01 HA06 TJ06 4K030 AA11 BA02 BA08 BA11 BA25 BA51 BB02 CA04 FA10 JA06 LA15 5F045 AA04 AB10 AB11 AB17 AB18 AC01 AC08 AC19 AD10 AD11 AF04 AF13 BB02 BB04 CA02 DA59 EK02 5F103 AA10 DD03 DD05 DD07 DD08 HH03 JJ03 KK01 KK10 LL01 LL07 LL11 NN06 RR04  ──────────────────────────────────────────────────続 き Continued on front page F-term (reference) 4G077 AA03 BE43 BE46 BE47 DB08 EB01 HA06 TJ06 4K030 AA11 BA02 BA08 BA11 BA25 BA51 BB02 CA04 FA10 JA06 LA15 5F045 AA04 AB10 AB11 AB17 AB18 AC01 AC08 AC19 AD10 AD11 AF04 AF13 BB02 BB59 EK02 5F103 AA10 DD03 DD05 DD07 DD08 HH03 JJ03 KK01 KK10 LL01 LL07 LL11 NN06 RR04

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】III−V族化合物半導体基板上に有機金属
気相成長(MOVPE)法によってn型導電性層を成長
させた化合物半導体エピタキシャルウェハにおいて、 前記n型導電性層は、少なくとも1層にSiおよびSe
が存在することを特徴とする化合物半導体エピタキシャ
ルウェハ。
1. A compound semiconductor epitaxial wafer in which an n-type conductive layer is grown on a group III-V compound semiconductor substrate by metal organic chemical vapor deposition (MOVPE), wherein the n-type conductive layer has at least one layer. Si and Se
A compound semiconductor epitaxial wafer characterized by the presence of:
【請求項2】前記n型導電性層は、GaAs、AlGa
As、InGaAs、InAlAs、InGaP、Al
GaInP、GaPおよびAlInPのうちいずれか1
つからなる構成の請求項1記載の化合物半導体エピタキ
シャルウェハ。
2. The method according to claim 1, wherein the n-type conductive layer is formed of GaAs, AlGa.
As, InGaAs, InAlAs, InGaP, Al
Any one of GaInP, GaP and AlInP
2. The compound semiconductor epitaxial wafer according to claim 1, wherein the compound semiconductor epitaxial wafer has a single-layer structure.
【請求項3】前記SiとSeの存在比率は、0.1≦
([Si]/[Se])≦10である構成の請求項1記
載の化合物半導体エピタキシャルウェハ。
3. The method according to claim 1, wherein the content ratio of Si and Se is 0.1 ≦
2. The compound semiconductor epitaxial wafer according to claim 1, wherein ([Si] / [Se]) ≦ 10.
【請求項4】III−V族化合物半導体基板上に有機金属
気相成長(MOVPE)法によってn型導電性層を成長
させる化合物半導体エピタキシャルウェハの製造方法に
おいて、 前記n型導電性層の成長は、n型ドーパントとしてSi
26およびH2Seを供給して前記n型導電性層中にS
iおよびSeを存在させることを特徴とする化合物半導
体エピタキシャルウェハの製造方法。
4. A method of manufacturing a compound semiconductor epitaxial wafer for growing an n-type conductive layer on a III-V group compound semiconductor substrate by a metal organic chemical vapor deposition (MOVPE) method, wherein the n-type conductive layer is grown. , Si as an n-type dopant
2 H 6 and H 2 Se are supplied to form S in the n-type conductive layer.
A method for producing a compound semiconductor epitaxial wafer, wherein i and Se are present.
JP2000190051A 2000-06-23 2000-06-23 Compound semiconductor epitaxial wafer and its manufacturing method Pending JP2002009001A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000190051A JP2002009001A (en) 2000-06-23 2000-06-23 Compound semiconductor epitaxial wafer and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000190051A JP2002009001A (en) 2000-06-23 2000-06-23 Compound semiconductor epitaxial wafer and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2002009001A true JP2002009001A (en) 2002-01-11

Family

ID=18689583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000190051A Pending JP2002009001A (en) 2000-06-23 2000-06-23 Compound semiconductor epitaxial wafer and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2002009001A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103938269A (en) * 2014-04-28 2014-07-23 上海华力微电子有限公司 Chamber temperature calibrating method of epitaxial technique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103938269A (en) * 2014-04-28 2014-07-23 上海华力微电子有限公司 Chamber temperature calibrating method of epitaxial technique

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