JP2001509336A5 - - Google Patents

Download PDF

Info

Publication number
JP2001509336A5
JP2001509336A5 JP1998531755A JP53175598A JP2001509336A5 JP 2001509336 A5 JP2001509336 A5 JP 2001509336A5 JP 1998531755 A JP1998531755 A JP 1998531755A JP 53175598 A JP53175598 A JP 53175598A JP 2001509336 A5 JP2001509336 A5 JP 2001509336A5
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998531755A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001509336A (ja
JP3885119B2 (ja
Filing date
Publication date
Priority claimed from EP97300562A external-priority patent/EP0858167A1/en
Application filed filed Critical
Publication of JP2001509336A publication Critical patent/JP2001509336A/ja
Publication of JP2001509336A5 publication Critical patent/JP2001509336A5/ja
Application granted granted Critical
Publication of JP3885119B2 publication Critical patent/JP3885119B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP53175598A 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサデバイス Expired - Fee Related JP3885119B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97300562A EP0858167A1 (en) 1997-01-29 1997-01-29 Field programmable processor device
EP97300562.2 1997-01-29
PCT/GB1998/000248 WO1998033276A1 (en) 1997-01-29 1998-01-28 Field programmable processor

Publications (3)

Publication Number Publication Date
JP2001509336A JP2001509336A (ja) 2001-07-10
JP2001509336A5 true JP2001509336A5 (https=) 2006-01-05
JP3885119B2 JP3885119B2 (ja) 2007-02-21

Family

ID=8229198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53175598A Expired - Fee Related JP3885119B2 (ja) 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサデバイス

Country Status (5)

Country Link
US (2) US6262908B1 (https=)
EP (2) EP0858167A1 (https=)
JP (1) JP3885119B2 (https=)
DE (1) DE69822796T2 (https=)
WO (1) WO1998033276A1 (https=)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
EP1061439A1 (en) 1999-06-15 2000-12-20 Hewlett-Packard Company Memory and instructions in computer architecture containing processor and coprocessor
JP2004506261A (ja) 2000-06-13 2004-02-26 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト パイプラインｃｔプロトコルおよびｃｔ通信
US7383424B1 (en) 2000-06-15 2008-06-03 Hewlett-Packard Development Company, L.P. Computer architecture containing processor and decoupled coprocessor
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
AU2002220600A1 (en) 2000-10-06 2002-04-15 Pact Informationstechnologie Gmbh Cell system with segmented intermediate cell structure
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7581076B2 (en) * 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
JP2004533691A (ja) * 2001-06-20 2004-11-04 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト データを処理するための方法
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
WO2003060747A2 (de) 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
EP2043000B1 (de) 2002-02-18 2011-12-21 Richter, Thomas Bussysteme und Rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US6844757B2 (en) * 2002-06-28 2005-01-18 Lattice Semiconductor Corp. Converting bits to vectors in a programmable logic device
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
US6980390B2 (en) * 2003-02-05 2005-12-27 Quantum Corporation Magnetic media with embedded optical servo tracks
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
US7219325B1 (en) 2003-11-21 2007-05-15 Xilinx, Inc. Exploiting unused configuration memory cells
US7853774B1 (en) * 2005-03-25 2010-12-14 Tilera Corporation Managing buffer storage in a parallel processing environment
WO2007082730A1 (de) 2006-01-18 2007-07-26 Pact Xpp Technologies Ag Hardwaredefinitionsverfahren
WO2008028330A1 (en) * 2006-08-31 2008-03-13 Beijing Xizheng Microelectronics Co. Ltd. A programmable interconnect network for logic array
US7994818B2 (en) * 2007-06-20 2011-08-09 Agate Logic (Beijing), Inc. Programmable interconnect network for logic array
JP5336398B2 (ja) * 2010-02-01 2013-11-06 ルネサスエレクトロニクス株式会社 半導体集積回路、半導体集積回路の構成変更方法
EP2575597B1 (en) 2010-05-25 2022-05-04 The General Hospital Corporation Apparatus for providing optical imaging of structures and compositions

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4236204A (en) 1978-03-13 1980-11-25 Motorola, Inc. Instruction set modifier register
US5233539A (en) 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5204556A (en) 1991-05-06 1993-04-20 Lattice Semiconductor Corporation Programmable interconnect structure for logic blocks
US5291431A (en) 1991-06-03 1994-03-01 General Electric Company Array multiplier adapted for tiled layout by silicon compiler
US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
US5498975A (en) * 1992-11-19 1996-03-12 Altera Corporation Implementation of redundancy on a programmable logic device
WO1995022205A1 (en) 1994-02-15 1995-08-17 Xilinx, Inc. Tile based architecture for fpga
US5453706A (en) * 1994-04-01 1995-09-26 Xilinx, Inc. Field programmable gate array providing contention free configuration and reconfiguration
GB2289354B (en) 1994-05-03 1997-08-27 Advanced Risc Mach Ltd Multiple instruction set mapping
US5426379A (en) * 1994-07-29 1995-06-20 Xilinx, Inc. Field programmable gate array with built-in bitstream data expansion
US5493239A (en) 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5659785A (en) 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5583450A (en) * 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
GB9611994D0 (en) 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor

Similar Documents

Publication Publication Date Title
JP2000509942A5 (https=)
JP2000509637A5 (https=)
JP2000507042A5 (https=)
JP2000509912A5 (https=)
JP2000509635A5 (https=)
JP2000510751A5 (https=)
JP2000509587A5 (https=)
JP2000507369A5 (https=)
JP2000507433A5 (https=)
JP2000508866A5 (https=)
JP2000510793A5 (https=)
JP2000508022A5 (https=)
JP2000508841A5 (https=)
JP2000508680A5 (https=)
JP2000509804A5 (https=)
JP2000509853A5 (https=)
JP2000509755A5 (https=)
JP2000510969A5 (https=)
JP2000510247A5 (https=)
JP2000508836A5 (https=)
JP2000508102A5 (https=)
JP2000509520A5 (https=)
JP2000509818A5 (https=)
JP2000507434A5 (https=)
JP2000508880A5 (https=)