JP2001509336A5 - - Google Patents

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Publication number
JP2001509336A5
JP2001509336A5 JP1998531755A JP53175598A JP2001509336A5 JP 2001509336 A5 JP2001509336 A5 JP 2001509336A5 JP 1998531755 A JP1998531755 A JP 1998531755A JP 53175598 A JP53175598 A JP 53175598A JP 2001509336 A5 JP2001509336 A5 JP 2001509336A5
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JP
Japan
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JP1998531755A
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JP3885119B2 (ja
JP2001509336A (ja
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Priority claimed from EP97300562A external-priority patent/EP0858167A1/en
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Publication of JP2001509336A5 publication Critical patent/JP2001509336A5/ja
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Publication of JP3885119B2 publication Critical patent/JP3885119B2/ja
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Description

Figure 2001509336
Figure 2001509336
Figure 2001509336
Figure 2001509336
Figure 2001509336
Figure 2001509336
Figure 2001509336
JP53175598A 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサデバイス Expired - Fee Related JP3885119B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97300562A EP0858167A1 (en) 1997-01-29 1997-01-29 Field programmable processor device
EP97300562.2 1997-01-29
PCT/GB1998/000248 WO1998033276A1 (en) 1997-01-29 1998-01-28 Field programmable processor

Publications (3)

Publication Number Publication Date
JP2001509336A JP2001509336A (ja) 2001-07-10
JP2001509336A5 true JP2001509336A5 (ja) 2006-01-05
JP3885119B2 JP3885119B2 (ja) 2007-02-21

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Family Applications (1)

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JP53175598A Expired - Fee Related JP3885119B2 (ja) 1997-01-29 1998-01-28 フィールドプログラマブルプロセッサデバイス

Country Status (5)

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US (2) US6262908B1 (ja)
EP (2) EP0858167A1 (ja)
JP (1) JP3885119B2 (ja)
DE (1) DE69822796T2 (ja)
WO (1) WO1998033276A1 (ja)

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DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
AU5805300A (en) 1999-06-10 2001-01-02 Pact Informationstechnologie Gmbh Sequence partitioning in cell structures
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EP1342158B1 (de) 2000-06-13 2010-08-04 Richter, Thomas Pipeline ct-protokolle und -kommunikation
US7383424B1 (en) 2000-06-15 2008-06-03 Hewlett-Packard Development Company, L.P. Computer architecture containing processor and decoupled coprocessor
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7581076B2 (en) * 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
WO2005045692A2 (en) 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
EP1402382B1 (de) 2001-06-20 2010-08-18 Richter, Thomas Verfahren zur bearbeitung von daten
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
ATE402446T1 (de) 2002-02-18 2008-08-15 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US6844757B2 (en) 2002-06-28 2005-01-18 Lattice Semiconductor Corp. Converting bits to vectors in a programmable logic device
WO2004021176A2 (de) 2002-08-07 2004-03-11 Pact Xpp Technologies Ag Verfahren und vorrichtung zur datenverarbeitung
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003289844A1 (en) 2002-09-06 2004-05-13 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US6980390B2 (en) * 2003-02-05 2005-12-27 Quantum Corporation Magnetic media with embedded optical servo tracks
US7219325B1 (en) * 2003-11-21 2007-05-15 Xilinx, Inc. Exploiting unused configuration memory cells
US7853774B1 (en) * 2005-03-25 2010-12-14 Tilera Corporation Managing buffer storage in a parallel processing environment
JP2009524134A (ja) 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト ハードウェア定義方法
WO2008028330A1 (en) * 2006-08-31 2008-03-13 Beijing Xizheng Microelectronics Co. Ltd. A programmable interconnect network for logic array
WO2008154775A1 (en) * 2007-06-20 2008-12-24 Agate Logic, Inc. A programmable interconnect network for logic array
JP5336398B2 (ja) 2010-02-01 2013-11-06 ルネサスエレクトロニクス株式会社 半導体集積回路、半導体集積回路の構成変更方法
EP2575597B1 (en) 2010-05-25 2022-05-04 The General Hospital Corporation Apparatus for providing optical imaging of structures and compositions

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