JP2001358782A - Device for detecting phase error - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that detection can not correctly be performed and locking is sometimes made on wrong detection timing for a long time when the phase error of detection timing is large in the case of calculating the phase error in the detection timing by using data sampled detection. SOLUTION: This device is provided with a in-phase/reverse phase data generating part for inputting a data string that is equalized to a partial response characteristic and oversampled and generating a sampled data of a phase common with and a sampled data of a phase reverse to a data detection phase, a phase error detection part for calculating the respective detection phase errors of in-phase/reverse phase data, a level error calculating part for calculating the accumulation of the respective level errors of the in-phase/reverse phase data, a detection level error comparing part for comparing the accumulated level errors of the in-phase data with the accumulated level errors of the reverse phase data, and a phase error calculating part for calculating phase error quantity by switching formulas from phase error quantity from the in-phase data and from phase error quantity from the reverse phase data in accordance with comparison results and outputting the phase error quantity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase error detecting device for detecting a phase error at a timing for determining data from a reproduction signal reproduced from a recording medium on which digital data is recorded.

[0002]

2. Description of the Related Art An interleaved NRZI is used as a recording modulation method for recording digital data at high density on a magnetic recording medium.
There is a method. This modulation method is a method of equalizing a reproduced signal to a partial response (hereinafter abbreviated as PR) (1, 0, -1) characteristic and decoding data from a three-level signal.

[0003] Signal processing in the interleaved NRZI system will be described with reference to FIG.

At the time of recording, input recording data 102
Is a precoder 10 having a transfer characteristic of 1 / (1-D2).
Is recorded on the magnetic recording medium. If the waveform of the recording data 102 at this time is as shown in FIG. 9A, the waveform after the precoding process is as shown in FIG. 9B.

At the time of reproduction, the reproduced signal is corrected by the high frequency range compensation circuit 11 to compensate for the loss in the high frequency range (1).
-D) Equalized to characteristics. Further, by passing through a (1 + D) circuit 12 having a (1 + D) characteristic, it is equalized to a (1-D2) characteristic. At this time, the reproduced signal 11 after the high frequency range correction is performed.
The waveform of 1 is shown in FIG. 9C, and the waveform of the signal 121 after the (1 + D) processing is shown in FIG. 9D.

[0006] The output signal 121 of the (1 + D) circuit is input to the sampling circuit 13 and the detection timing reproducing unit 14
Is sampled at the timing of the timing signal 141. The sampled signal 131 is input to the detection timing recovery circuit 14, where the detection timing indicated by the upward arrow in FIG. 9D is reproduced, and the decoding unit 15 changes the level of the signal 131 (indicated by a black circle) at that timing into three values. Judgment, level ± 1 is data 1 and level 0 is data 0
, The recorded data is reproduced. Further, the error performance can be improved by using Viterbi decoding in the data decoding process. For details of Viterbi decoding, see “Digital Video Recording Technology” (Eto, Mita and Doi, published by Nikkan Kogyo Shimbun), pp. 72-84.

The above-described detection timing reproducing section 14 will be described in detail with reference to FIG.

[0008] The signal 131 sampled at the data detection timing is input to the three-level determination unit 16 and is determined to be the closest level among the three levels (1, 0, -1). The determination result 161 (xn) and the sampled signal 131 (yn) are input to the phase error calculation circuit 17, and the phase error value 17 calculated according to (Equation 2) is obtained.
1 is output.

[0009]

(Equation 2)

The details of the phase error detector are described in F. Dolivo, WS
chott, and G. Ungerboeck, "Fast timing recovery for
partial-response signaling systems, "Int. Conf. Co
mmun. '89 (ICC'89), pp. 573-577.

FIG. 10 shows the relationship between the phase error amount at the detection timing and the calculated phase error amount in the above-described method. However, since the calculated phase error amount depends on the data pattern, it is an average value calculated from a random data string including various patterns.

The calculated phase error value 171 is fed back to the detection timing generator 19 via the loop filter 18. Thereby, the detection timing is reproduced.

[0013]

However, FIG.
As can be seen from the figure, when the phase error of the detection timing is small, the phase error is correctly detected, but when the phase error is large, the phase error cannot be detected correctly. In the worst case,
Locking is performed at an erroneous detection timing (a timing shifted by 180 degrees from the correct detection timing) for a long time, and correct recorded data cannot be reproduced. Further, even when locking is performed at the correct timing, it takes time to lock.

[0014]

In order to solve the above-mentioned problems, a phase error detecting apparatus according to the present invention receives a data sequence equalized to a partial response characteristic and oversampled, and outputs a signal having the same phase as the data detection phase. An in-phase / negative-phase data generation unit for generating two-system data strings of a first data string corresponding to the sampling data and a second data string corresponding to the negative-phase sampling data; A first phase error detector for detecting a data detection phase error as an input and outputting a first phase error amount; and a second phase detector for detecting the detected phase error by receiving the second data string as an input.
A second phase error detector that outputs a phase error amount of
A first level error calculator that receives the first data string as input, calculates the accumulation of level errors for N levels, and outputs a first cumulative level error; A second level error calculator for calculating the cumulative error and outputting a second cumulative level error; and inputting the first cumulative level error and the second cumulative level error as inputs and determining the magnitude of the two cumulative level errors. Calculating a phase error amount by switching a calculation formula from the first phase error amount and the second phase error amount according to a comparison result from the detection level error comparison unit to be compared and the comparison result from the detection level error comparison unit; And a phase error calculating section for outputting.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A phase error detecting device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a phase error detecting device according to the embodiment. A case will be described in which a data sequence obtained by oversampling a three-level reproduced signal equalized to the PR (1, 0, -1) characteristic at twice the bit rate is input.

The PR (1, 0,-) reproduced from the recording medium
1) A data string 101 obtained by sampling a signal equalized in characteristics at a frequency approximately twice the bit rate is input to an input terminal 1
Is entered from The input data sequence 101 is input to the in-phase / negative-phase data generation unit 2 and the in-phase data sequence 2 corresponding to the data sampled at the data detection timing.
01 and an opposite-phase data sequence 202 corresponding to data sampled at the opposite-phase timing are generated. In the case of a data string oversampled at a double frequency synchronized with the detection timing, it can be easily realized by separating the data string into odd and even data strings. In the case of a data string that is asynchronously oversampled at almost twice the frequency,
By deriving data at a desired sampling timing by interpolation processing, an in-phase / out-phase data sequence can be generated. Specifically, in-phase data indicated by a black circle and inverted-phase data indicated by a cross are generated from double-oversampled data indicated by a white circle in FIG. 2A.

Also, only the case where a signal that is oversampled twice is input has been described. However, even when a signal that is oversampled at a frequency other than twice is input, the same and opposite phases are similarly obtained by interpolation. Can be generated.

The in-phase data sequence 201 is input to the in-phase error detector 3, and the phase error (Pen) 301 is calculated and output according to the equation (2). (Equation 2)
Yn is the level indicated by the current data, and yn-
1 is the level indicated by the immediately preceding data. Further, xn is one of three values (1, 0, -1) as a result of three levels of determination from yn.

(Equation 2) is a calculation formula for calculating the current phase error from the current data and the immediately preceding data, and will be described with a specific example. As shown in FIG. 3A, when the determination result is 1 after 1, the immediately preceding signal level yn-
The current phase error (Pen) is calculated by subtracting the current signal level yn from 1. If the detection timing is late, Pen> 0, and if the detection timing is advanced, Pen <0. FIG. 3 (b)
When the determination result is 0 following 1 as shown in FIG. 5, the phase error P is inverted by inverting the sign of the current signal level yn.
en is calculated.

Similarly, the anti-phase data sequence 202 is input to the anti-phase error detector 4, and the phase error 401 is calculated and output according to the equation shown in (Expression 2).

The in-phase data sequence 201 is input to the in-phase level error detection unit 5 and the closest ternary level (1, 0, -1)
Is calculated, and the accumulated level error 50 is calculated.
1 is output. As an example of the configuration of the level error detection unit, FIG. 4 shows a configuration in the case where the accumulation of the level errors of n data is detected retroactively from the present. Input data 2
01 is determined in three levels, and the level error 203 is calculated by taking the difference from the original level. The n level errors calculated in this way are stored, and a cumulative level error 501 is output by taking a weighted average of the n level errors. At this time, all of a0 to an-1 may be 1,
A coefficient is only 1 for a0 and smaller as the previous level error (1> a
1>a2...> An-1). The same can be realized with a simple configuration by using another configuration example as shown in FIG. The cumulative level error 501 is an index indicating the deviation amount of the detection timing, and indicates that the smaller the cumulative level error is, the smaller the deviation amount of the detection timing is.

Similarly, the reversed-phase data sequence 202 is input to the reversed-phase level error detector 6, and the closest ternary level (1,
The accumulation of the level error from (0, -1) is calculated, and the accumulated level error 601 is output.

The cumulative level errors 501 and 601 are input to the detection level error comparing section 7, where the two cumulative level error values are compared in magnitude and a comparison result 701 is output.

In-phase error 301 and out-of-phase error 4
01 and the comparison result 701 are input to the phase error calculator 8. When the accumulated level error 501 of the in-phase data is smaller, the phase error calculator 8
Is output as the phase error 801. If the cumulative level error 601 of the negative phase data is smaller, the value calculated based on the negative phase error 401
Output as As an example, if the negative phase error 401 is a value larger than 0, a negative constant value is output as the phase error 801, and if the negative phase error 401 is a value smaller than 0, a positive constant is output as the phase error 801. Output the value. When the negative phase error 401 is 0, a zero value may be output as the phase error 801. By doing so, the relationship between the phase shift amount between the sampling timing of the in-phase data 201 generated from the input data 101 and the actual detection timing and the phase error 801 has good characteristics as shown in FIG. . As another example, if the negative phase error 401 is a positive value, a value obtained by inverting the positive / negative of the negative phase error 401 and adding a negative constant value as the phase error 801 is output, and the negative phase error is output. If the error 401 is a negative value, a value obtained by inverting the positive / negative of the negative phase error 401 as the phase error 801 and adding a positive constant value may be output.

The comparison result 701 indicates that the in-phase error 3
If the difference between 01 and the out-of-phase error 401 indicates that the difference is smaller than a certain value, the average value of the in-phase error 301 and the out-of-phase error 401 may be output as the phase error 801.

Also, a case has been described where a three-level reproduced signal equalized to the PR (1, 0, -1) characteristic is input. However, equalization to another PR characteristic such as the PR (1, -1) characteristic is performed. The same holds true when the multi-level reproduced signal is input.

[0028]

As described above, according to the present invention, the phase error is calculated by using not only the in-phase data sampled at the detection timing but also the out-of-phase data shifted from the detection timing by approximately 180 degrees. The phase error of the detection timing can be correctly detected over the entire range from -180 degrees to +180 degrees. This makes it possible to reproduce the detection timing with good stability and responsiveness.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a phase error detection device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining an operation outline of an in-phase / negative-phase data generation unit according to the embodiment of the present invention;

FIG. 3 is a schematic diagram for explaining an outline of calculating a phase error amount in a phase error detection unit according to the embodiment of the present invention.

FIG. 4 is a block diagram showing an example (FIR type) of a configuration of a level error detection unit according to the embodiment of the present invention.

FIG. 5 is a block diagram showing an example (IIR type) of a configuration of a level error detection unit according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a relationship between a timing phase shift amount and a detected phase error amount in the phase error detection device according to the embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a magnetic recording / reproducing apparatus based on an interleaved NRZI method.

FIG. 8 is a block diagram showing a configuration of a detection timing reproduction unit including a conventional phase error detection unit.

FIG. 9 is an explanatory diagram showing signal waveforms of respective parts of the magnetic recording / reproducing apparatus based on the interleaved NRZI method.

FIG. 10 is an explanatory diagram showing a relationship between a timing phase shift amount and a detected phase error amount in a conventional phase error detection device.

[Explanation of symbols]

 2 In-phase / negative-phase data generator 3, 4 Phase error detector 5, 6 Level error detector 7 Detection level error comparator 8 Phase error calculator

Claims (3)

[Claims] 1. A data sequence equalized to an N-level (N is an integer of 3 or more) partial response characteristic and oversampled at a higher rate than a bit rate is input. An in-phase / negative-phase data generation unit that generates two-system data strings of a first data row corresponding to sampling data having the same phase as the detected phase and a second data row corresponding to sampling data having the opposite phase; A first phase error detection unit that receives a data sequence of 1 as an input, detects a data detection phase error, and outputs a first phase error amount, and detects a detected phase error with the input of the second data sequence as a second A second phase error detector for outputting a phase error amount; calculating the accumulation of level errors with respect to N levels by inputting the first data string to generate a first accumulated level error; A first level error calculator that inputs the second data string, calculates a cumulative level error with respect to N levels, and outputs a second cumulative level error; A detection level error comparison unit that receives the cumulative level error of the first and second cumulative level errors as inputs and compares the two cumulative level errors with each other; A phase error detection device, comprising: a phase error calculator that calculates and outputs a phase error amount by switching a calculation formula from a phase error amount and the second phase error amount. 2. N is 3 and the first and second phase error detectors use the following formula based on the current data yn of the input data sequence and the previous data yn-1. ] The phase error detection device according to claim 1, wherein the phase error amount Pen is calculated and output by the calculation. 3. The detection level error comparison section according to claim 1, wherein:
The magnitude of the accumulated level error is compared with the magnitude of the second accumulated level error, and if the first accumulated level error is large, the first phase error amount is output. 3. The phase error detecting device according to claim 1, wherein when the value is larger, a sign whose sign is opposite to the sign of the second phase error is output.