JP2001358151A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the conventional semiconductor element that the restraining a semiconductor element provided with a guard ring formed through a usual diffusion method from becoming unnecessarily large in size, due to the fact that the position of the guard ring is required to be determined, taking the effect of lateral diffusion into consideration. SOLUTION: A groove is cut in the surface of a silicon base material 1 by a reactive ion etching method, at a position at which a gourd ring 3 is formed, and silicon different in characteristics from the silicon base material is deposited in the groove for the formation of the guard ring.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a transistor having a guard ring mechanism for obtaining a withstand voltage, a semiconductor device such as a MOSFET, and a semiconductor device having an isolation diffusion portion.

[0002]

2. Description of the Related Art FIG. 1 is a partial structural view of a conventional transistor having a guard ring mechanism. Guard rings 3 are formed three times around the collector junction 2 of the N-type silicon base material 1. The guard ring 3 is a P layer formed by diffusion. With such a structure of the plurality of guard rings 3, the space charge layer around the collector junction 2 spreads, and breakdown on the element surface can be prevented. High breakdown voltage of the element can be realized by a guard ring mechanism for preventing breakdown on the element surface. The guard ring 3 is formed by diffusion of the oxide film 4 from the mask opening.

[0003]

However, in the structure shown in FIG. 1, since the guard ring 3 is formed by diffusion, the diffusion direction advances vertically and horizontally. For this reason, in order to obtain the vertical diffusion length necessary to obtain a predetermined withstand voltage characteristic, it is necessary to calculate the lateral diffusion of the guard ring and design the ring position. However, there is a problem that the distance of the object becomes larger than necessary.
In FIG. 1, three guard rings 3 each having a depth of 5
The dimension for obtaining a predetermined withstand voltage when the width of the micron is 3 microns is shown. That is, the width occupied by one guard ring 3 is required to be a width (13 microns) obtained by adding twice the width of 5 microns, which is the same as the diffusion depth, from the end of the diffusion window to 3 microns of the diffusion window. After all, to form three guard rings 3, 13
* 3 = 39 microns is required. Generally, forming n guard rings requires n * 13 microns.

As described above, in a conventional semiconductor device in which a guard ring is formed by diffusion, it is necessary to determine the ring formation position in consideration of the influence of lateral diffusion.
There has been a problem that the semiconductor size becomes unnecessarily large.

An object of the present invention is to provide a semiconductor device capable of forming a guard ring without using diffusion.

[0006]

According to the present invention, there is provided a semiconductor device in which a semiconductor junction is surrounded by a guard ring junction and a predetermined withstand voltage characteristic is ensured. A groove is formed by etching, and silicon having characteristics different from those of the base material is deposited in the groove to form the guard ring.

The ion etching has anisotropy in the etching direction and has a small side etch effect. Therefore, unlike the diffusion, very sharp etching can be performed. Reactive ion etching can be applied to obtain fine etching accuracy.

The concept of the guard ring in the present invention is to prevent breakdown on the element surface, but includes all ring structures having the same purpose. For example, a ring structure called a floating ring, a diffused quad ring, a field limiting ring, or a floating field ring is also included in the guard ring of the present invention.

In the present invention, a guard ring is formed by forming a groove by ion etching, not by diffusion, and depositing silicon (P-type or N-type silicon or the like) having characteristics different from those of the base material on the groove. In addition, there is no need to determine the ring formation position in consideration of the influence of lateral diffusion. Therefore, the semiconductor size does not increase unnecessarily.

The present invention provides, in addition to the above guard ring,
It can also be used for a separation diffusion unit. The separation / diffusion portion for electrically separating the semiconductor chip in the lateral direction is necessary when a plurality of semiconductor elements are formed on the same chip, but conventionally, the separation / diffusion portion is formed exclusively by diffusion. Was. When the present invention is used for forming the separation / diffusion portion, the size of the device can be reduced.

[0011]

FIG. 2 shows the structure of a high breakdown voltage transistor according to an embodiment of the present invention. In this transistor, three guard rings 3 are formed.

An emitter and a base are respectively diffused and formed in the N-type silicon base material 1, and three guard rings 3 are formed in a subsequent step.

The order of the steps is as follows.

(1) A groove is formed at a predetermined position from above the oxide film 4.

The groove is formed by reactive ion etching (RIE).
Formed. RIE uses the combined effect of physical etching in which accelerated ions bombard the sample and chemical etching with active neutral radicals. The side-etch effect is extremely small, and high-precision at high etching rates is achieved. Fine processing is possible. Therefore, the guard ring position can be determined without calculating the progress of the etching in the horizontal direction due to the anisotropy in which the etching proceeds only in the vertical direction. The predetermined position is determined using a photoresist film.

(2) Silicon (P-type or N-type silicon or the like) having characteristics different from those of the base material is deposited on the surface of the semiconductor element by the CVD method.

(3) Unnecessary deposits are removed by etching.

In the transistor formed as described above, the size reduction in the lateral direction is as follows.

Assuming that there are three guard rings 3, each having a depth of 5 microns and a ring width of 3 microns, the transistor of this embodiment has one guard ring as shown in FIG. The lateral dimension occupied by 3 is only 3 microns, and the entire guard ring 3 is 9 microns. Therefore, the size is reduced by 30 μm in comparison with the related art.

In the present invention, not only the guard ring 3 but also the formation of a concentration difference region with the base material on the silicon surface, which has conventionally been performed by diffusion, and a P-type or N-type region different from the base material.
By forming the portion having the characteristics of the mold by etching by RIE and CVD deposition of silicon having characteristics different from those of the base material, the required characteristics can be realized with a smaller area.

FIG. 3 shows a semiconductor device in which the present invention is applied to the formation of an isolation diffusion portion. In the figure, reference numeral 5 denotes a separation / diffusion unit. The method for forming the separation / diffusion portion 5 may be exactly the same as the above-described guard ring forming method.

Further, according to the present invention, a semiconductor element having a junction portion on a chip surface, such as a thyristor or a triac, can be made smaller in size and improved in reliability from a conventional double-sided mesa type. FIG. 4 shows a double-sided mesa-type semiconductor device. The junctions J1 and J2 in the upper and lower mesas are protected by glass or the like. It is said to be quite difficult to manufacture.
Therefore, as shown in FIG. 5, isolation / diffusion portions 5 are provided on both sides of the device. Further, a groove 6 is formed on the upper surface by etching. The groove 6 is for separating the upper P layer. With such a structure, the P layer 7 outside the groove 6 is formed.
Are connected to the lower P layer 8 by the separation diffusion portion 5,
The potential difference between the two becomes zero. As a result, as compared with the double-sided mesa type semiconductor element shown in FIG. The upper junction J1 of the double-sided mesa type semiconductor element shown in FIG. 1 corresponds to the inner junction J1 'formed in the groove 6. This means that protection of the junction is possible only on the upper side. Therefore, manufacturing becomes easy, and the upper junction can be completely protected, so that the yield of the entire device is increased and the reliability is improved.

[0023]

According to the present invention, a guard ring is formed by forming a groove by ion etching, not by diffusion, and depositing silicon (P-type or N-type silicon) having characteristics different from those of the base material on the groove. Therefore, it is not necessary to determine the ring formation position in consideration of the influence of lateral diffusion. Therefore, there is an advantage that the semiconductor size does not increase unnecessarily.

The application of the present invention to the separation / diffusion portion also has the advantage that the semiconductor size does not increase unnecessarily, and further facilitates the manufacture of semiconductor devices having a junction portion on the chip surface, such as thyristors and triacs. And the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a partial structural view of a transistor having a conventional guard ring mechanism.

FIG. 2 is a structural diagram of a high breakdown voltage transistor according to an embodiment of the present invention.

FIG. 3 is a schematic structural view of a semiconductor device when the present invention is applied to a separation / diffusion unit;

FIG. 4 is a schematic structural diagram of a double-sided mesa type semiconductor device.

FIG. 5 is a schematic structural view of a semiconductor device when the present invention is applied to a separation / diffusion unit.

[Explanation of symbols]

 1: Silicon base material 2: Collector junction 3: Guard ring 4: Oxide film

Claims (2)

[Claims] In a semiconductor device in which a semiconductor junction is surrounded by a guard ring junction and a predetermined breakdown voltage characteristic is secured, a groove is formed by ion etching at a position on the surface of the silicon base material where the guard ring is to be formed. A semiconductor element, wherein silicon having a characteristic different from that of a base material is deposited in a groove to form the guard ring. 2. A semiconductor device having an isolation / diffusion portion for electrical isolation of a semiconductor chip in a lateral direction, wherein a groove is formed at a position where the isolation / diffusion portion is to be formed by ion etching. A semiconductor element characterized by depositing silicon having characteristics different from those of the base material to form the separation / diffusion portion.