JP2001345772A - Sdh transmission device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To receive asynchronous DS3 signal independent of kind of VC corresponding to a VC switch function provided to an objective SDH transmission device, and to reduce occurrence of staff jitter at restoring DS3 signal independent of VC kind or quantity of SDH signal for receiving DS3 signal. SOLUTION: Intermediate signal synchronous with system clock of a device is generated, in which the asynchronous DS3 signal is housed by pulse staff synchronous process, which is synchronously received in the SDH signal for transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SDH transmission apparatus for accommodating an asynchronous DS3 signal in an SDH transmission apparatus, and more particularly to a DS3 signal stuff synchronization circuit.

[0002]

2. Description of the Related Art In recent years, with the progress of the ISDN era, CC
The ITT (International Telegraph and Telephone Advisory Committee) has recommended an SDH transmission system which is a basis for building a globally unified network. Along with this, it is required that asynchronous signals of the existing network be accommodated in SDH frames to achieve interconnectivity.

[0003]

However, the asynchronous DS
As for accommodating three signals in the SDH transmission apparatus, the related art has the following problems. The first problem is that in order to accommodate asynchronous DS3 signals in SDH signals,
SDH with C-3 unit switch (line editing) function
It is necessary to prepare a transmission device, and the SDH transmission device which does not have the switching function of the VC-3 unit (it has only the switching function of the VC-2 unit or the VC-11 unit) can accommodate the asynchronous DS3 signal. There was no problem.

[0004] The second problem is that the asynchronous DS3 signal is converted to the SD signal.
When accommodating in the H signal VC-n, the STM-n SOH which is an overhead byte on the SDH signal format
DS3 signals must be accommodated by avoiding the bytes and the POH bytes and fixed stuff bytes of VC-3.
When restoring the S3 signal, it is very difficult to suppress the generation of stuff jitter due to the overhead bytes of these SDH signals, and it is very difficult for a normal PLO circuit to keep the accuracy of the reproduced DS3 clock within ± 20 ppm of the DS3 standard. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object the object of the present invention.
The H transmission apparatus can accommodate asynchronous DS3 signals without depending on the corresponding VC type of the VC switch function provided by the H transmission device, and can execute DS3 signals without depending on the type and number of SDH signals that accommodate DS3 signals. SDH that can reduce the amount of stuff jitter generated during restoration
A transmission device is provided.

[0006]

In order to achieve the above object, a feature of the present invention is that an asynchronous DS3 signal is converted to an SD3 signal.
Means for generating an intermediate signal synchronized with the system clock of the apparatus in an SDH transmission apparatus that accommodates and transmits an H (Synchronous Digital Hierarchy) signal, and accommodates an asynchronous DS3 signal in the generated intermediate signal by performing a pulse stuff synchronous process. And means for transmitting the intermediate signal synchronously accommodating the asynchronous DS3 signal by stuffing synchronously with the SDH signal.

The feature of the second aspect of the present invention is that the system clock is synchronized with the SDH network synchronous clock from the asynchronous DH network synchronous clock.
An object of the present invention is to generate an intermediate signal clock which is a clock faster than the S3 signal frequency.

[0008] A feature of the invention of claim 3 is that the asynchronous DS
An intermediate signal in which three signals are accommodated by stuff synchronization is divided and mapped into seven VC-2 signals by VC-2 mapping.

A feature of the invention of claim 4 is that the asynchronous DS
The intermediate signal containing the three signals stuffed synchronously is represented by VC-11
The mapping consists of dividing and mapping into 28 VC-11 signals.

A feature of the invention of claim 5 is that the data rate, frame format, and stuff rate of the intermediate signal are
It is to choose to minimize stuff jitter.

In the present invention, the bit rate and frame format of the intermediate signal in FIG.
It is arbitrarily and optimally determined in consideration of the nominal bit rate of the signal, the accommodability to the SDH signal, the stuff rate, the transmission elastic store capacity (write / read phase difference comparison cycle), and the like.

SDH at intermediate signal clock generation PLO 16
D from the system clock synchronized with the network synchronization clock
An intermediate signal clock that is a clock faster than the S3 signal frequency is generated. Since the intermediate signal clock is synchronized with the system clock, the intermediate signal data and the SDH signal are clock synchronized.

As the processing on the transmission side, the input DS3 data 1 is sequentially written to the transmission elastic store 3 in accordance with the DS3 clock extracted from the input DS3 signal which is an asynchronous signal. On the other hand, according to the intermediate signal clock, the intermediate signal generation 6 is transmitted from the transmission elastic store circuit 3 to D
S3 Data 2 is read. The phase difference between the writing and the reading of the transmission elastic store circuit 3 is monitored by the phase comparison circuit 4, and when the phase difference becomes smaller than a certain phase difference, a stuff request is output to the intermediate signal generation circuit 6.

As shown in FIG. 4, the intermediate signal generating circuit 6 is adapted to receive a stuff request bit position other than the information bit area in the intermediate signal format, a fixed stuff bit position, and a stuff request from the phase comparison circuit 4. The read from the transmission elastic store circuit 3 is stopped at the stuff bit position, and a read enable signal is output to the address generation counter circuit 5.

The intermediate signal generating circuit 6 includes the DS3 data 2 read from the transmission elastic store 3, the stuff designation bit and the fixed stuff bit in the intermediate signal format, and the stuff bit when there is a stuff request from the phase comparison circuit 4. To add an extra bit (stuff operation) to generate an intermediate signal. As a result, the DS3 signal which is an asynchronous signal is stuffed and accommodated in the intermediate signal. D
The intermediate signal containing the S3 signal is a VC-2 mapping 7
Are divided and mapped into seven VC-2 signals, which are converted to SDH signals and output to the SDH transmission network.

Here, an example in which the intermediate signal is accommodated in seven VC-2 signals is shown. However, since the intermediate signal is synchronized with the system clock, a VC (Virtual Container) of the SDH signal accommodating the intermediate signal is provided. ) Any type is acceptable. For example, one VC-3 signal or VC-1
It is sufficient that the number of VC signals and the number of VC signals that can secure the capacity to accommodate the bit rate of the intermediate signal, such as 28 signals, be ensured.

As the processing on the receiving side, seven VC-2 signals are extracted from the SDH signal input in SDH signal synchronization 9.
In VC-2 demapping 10, seven VC-2 signals are multiplexed to restore the original intermediate signal data sequence. The intermediate signal format is terminated at the intermediate signal end 11. Specifically, a majority decision is made on the stuff designation bits in the intermediate signal frame, and as a result, when the stuff bits are determined as surplus bits instead of information bits, the stuff bits are added to the stuff bit positions in addition to the stuff designation bits and the fixed stuff bits. An intermittent intermediate signal clock in which the signal clock is stopped is generated. The stuff designation bits, the fixed stuff bits, and the stuff bits, which are surplus bits, in the intermediate signal are discarded (destuff operation) from the toothless intermediate signal clock without being written to the reception elastic store 13 and only the information bit (DS3 signal) is output. Written.

The DS3 clock generating PLO 12 smoothes the missing intermediate signal clock and reproduces and outputs a continuous DS3 clock. Data is continuously read from the reception elastic store 13 with the reproduced DS3 clock,
The DS3 data is output to the U / B converter 14. The U / B converter 14 converts the DS3 data into a bipolar signal and
Output as an output DS3 signal to the interface.

As described above, by introducing the intermediate signal, it is possible to realize the pulse stuffing process in units of 1 bit and to set the stuffing ratio to an ideal value without depending on the VC type of the SDH signal as the transmission medium. Therefore, the stuff jitter generated when the DS3 signal is restored can be minimized.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the SDH transmission device of the present invention. S in this example
The DH transmission device includes a B / U conversion & CLK extraction circuit 1, a write address generation counter circuit 2, a transmission elastic store circuit 3, a phase comparison circuit 4, a read address generation counter circuit 5, an intermediate signal generation circuit 6, and a VC-2 mapping. Circuit 7, SDH signal generation circuit 8, SDH signal synchronization circuit 9, VC-2 demapping circuit 10, intermediate signal termination circuit 11, DS3 clock generation PLO circuit 12, reception elastic store circuit 13, U / B conversion circuit 14, An SDH synchronous clock generation PG circuit 15 and an intermediate signal clock generation PLO circuit 16 are provided.

Next, the operation of this embodiment will be described.
The B / U conversion & CLK extraction circuit 1 extracts the clock component from the input DS3 signal to generate a DS3 clock,
This is output to the write address generation counter circuit 2. Further, the B3ZS encoded bipolar signal is converted into a unipolar signal to generate a DS3 data 1 signal, which is output to the transmission elastic store circuit 3.

The write address generation counter circuit 2
The capacity of the transmission elastic store circuit 3 is counted as the maximum value by the ring counter incremented by the DS3 clock, and the count value is output to the transmission elastic store circuit 3 and the phase comparison circuit 4 as a write address W_ADR signal.

The read address generation counter circuit 5
A ring counter that increments with the intermediate signal clock input from the intermediate signal clock generation PLO circuit 16 and stops the count-up operation when the read enable signal input from the intermediate signal generation circuit 6 is in the read stop state and holds the count value. The counting operation is performed with the capacity of the transmission elastic store 3 as the maximum value. The counter value is output to the transmission elastic store circuit 3 and the phase comparison circuit 4 as an R_ADR signal as a read address.

The phase comparison circuit 4 has a write address W_
The ADR signal is compared with the read address R_ADR signal, and when the read address approaches the write address by a certain value or more, a stuff request signal requesting execution of a stuff operation is output to the intermediate signal generation circuit 6.

The transmission elastic store circuit 3 has a B /
DS3 data 1 input from U conversion & CLK extraction circuit 1
A signal is written to the address specified by the W_ADR signal input from the write address generation counter circuit 2 and R_AD input from the read address generation counter circuit 5
The data at the address specified by the R signal is output to the intermediate signal generation circuit 6 as a DS3 data 2 signal.

The intermediate signal generation circuit 6 generates an intermediate signal frame phase based on the intermediate signal clock. An example is shown in FIG. Based on the generated intermediate signal frame phase, at the timing of the information bits in the intermediate signal format, the read enable signal output to the read address generation counter circuit 5 is read and executed, and the stuff designation bit and the fixed stuff bit in the intermediate signal format are read. At this timing, the read enable signal is set to the read stop state, and if the stuff request signal input from the phase comparison circuit 4 is in a state requiring execution of the stuff operation, the read enable signal is read at the timing of the stuff bit in the intermediate signal format. To stop.

Conversely, if the input stuff request signal does not request the execution of the stuff operation, the read enable signal is read at the timing of the stuff bit in the intermediate signal format and the execution state is set. Then, a stuff designation bit, a fixed stuff bit, and a stuff bit are inserted into the DS3 data 2 signal input from the transmission elastic store circuit 3 in accordance with the timing of the intermediate signal frame phase to generate an intermediate signal. Output to

The intermediate signal generation will be further described.
If the stuff request signal input from the phase comparison circuit 4 requests execution of a stuff operation, the intermediate signal frame is set as a stuff execution frame, a stuff designation bit is set to a stuff execution state logic, and Insert extra bits. If the stuff request signal input from the phase comparison circuit 4 does not request the execution of the stuff operation, the intermediate signal frame is set to the stuff non-executing frame, the stuff designation bit is set to the stuff non-executing logic, and The DS3 data 2 signal input from the transmission elastic store 3 is inserted using the bits as information bits. In addition, the intermediate signal frame 1 signal indicating the frame start position of the intermediate signal is also VC-
2 to the mapping circuit 7.

The VC-2 mapping circuit 7 divides the intermediate signal data into seven by the inputted intermediate signal data 1 signal and intermediate signal frame 1 signal, and divides each into seven VC signals.
-2 in the payload portion. Further, a VC-2 path overhead (POH) signal is added and output to the SDH signal generation circuit 8.

The SDH signal generation circuit 8 receives the input VC-
A TU-2 pointer (V1 to V4 bytes) is assigned to the seven signals to perform multiplexing processing on VC-3 and STM-n signals to generate STM-n signals and output SD signals.
The signal is output to the SDH network as an H signal (see FIGS. 2 and 3).

Next, the STM-n input from the SDH network
The signal is input to the SDH signal synchronization circuit 9 as an input SDH signal. The SDH signal synchronization circuit 9 performs termination processing (pointer processing, POH termination) of the STM-n signal and the VC-3 signal, extracts seven VC-2 signals, and outputs the same to the VC-2 demapping circuit 10.

The VC-2 demapping circuit 10 extracts an intermediate signal divided into seven VC-2 signals from the VC-2 payload, restores the intermediate signal into one intermediate signal based on the intermediate signal clock, and outputs the intermediate signal. The signal 2 is output to the intermediate signal terminal 11. In addition, the intermediate signal frame 2 signal indicating the frame start position of the intermediate signal is also transmitted to the intermediate signal termination circuit 11.
Output to

The intermediate signal terminating circuit 11 recognizes the phase of the intermediate signal frame based on the intermediate signal frame 2 signal and the intermediate signal clock, extracts a stuff designation bit in the intermediate signal and performs majority decision processing. It is determined whether the stuff bit is an information bit or a surplus bit (stuff operation execution). The contents of the input intermediate signal data 2 are not changed as they are,
The signal is output to the reception elastic 13 as the S3 data 3, and the timing of the stuff designation bit, the fixed stuff bit, and the stuff bit determined as the surplus bit (execution of stuff operation) in the intermediate signal with respect to the intermediate signal clock is determined. An intermittent missing signal clock that has been omitted (clock stopped) is generated and output to the reception elastic store circuit 13 in the same manner.

In the reception elastic circuit 13, DS3
Data 3 is input by the missing tooth intermediate signal clock, and the DS3 data 3 is not written at the timing when the missing tooth intermediate signal clock is missing. This allows
The stuff bits designated as the stuff designation bits, the fixed stuff bits, and the surplus bits (stuff operation execution) in the intermediate signal are discarded, and the information bits (DS3
) Is written into the reception elastic store circuit 13.

The DS3 clock generation PLO circuit 12 receives the missing intermediate signal clock and generates a divided clock thereof. A VCO (Voltage Controlled Oscillator) having a central oscillation frequency of 44.736 MHz is provided, and the phase comparison between the divided clock of the VCO output and the divided clock of the missing intermediate signal clock is performed. The result is fed back to the VCO for phase synchronization, and the VCO output clock is output to the reception elastic store circuit 13 and the U / B converter 14 as a smoothed reproduced DS3 clock.

In the reception elastic store circuit 13,
The data is sequentially read out based on the reproduced DS3 clock, and this is output to the U / B conversion circuit 14 as DS3 data 4. The U / B conversion circuit 14 performs B3ZS encoding processing and unipolar / bipolar conversion from the input DS3 data 4 and the reproduced DS3 clock, generates an output DS3 signal, and outputs this to the DS3 interface.

The SDH synchronous clock generation PG circuit 15
An SDH network synchronization clock input from the outside is input, a system clock signal synchronized with this is generated, and an SDH signal processing unit (VC-2 mapping 7, SDH signal generation circuit 8, SDH signal synchronization circuit 9, VC-2 data) is generated. Output to the mapping circuit 10) and generate an intermediate signal clock PLO.
Also output to the circuit 16.

The intermediate signal clock generation circuit PLO16 is
A system clock signal synchronized with the SDH network synchronization clock is input and divided. DS3 signal frequency 44.736M
VCO with oscillation frequency (frequency of intermediate signal) higher than 1 Hz
(Voltage-controlled oscillator), and compares the phase of the divided clock of the output with the divided clock of the system clock. The result is fed back to the VCO for phase synchronization, and the VCO output is output as an intermediate signal clock.

Next, the operation of this embodiment will be further described. When performing pulse stuff synchronization of a DS3 signal which is an asynchronous digital signal, a signal having a higher bit rate than the DS3 signal (an intermediate signal in the present invention) is used, and the surplus bits are obtained by subtracting the bit rate of the DS3 signal from the higher bit rate signal. By inserting at a bit rate of, stuff synchronization can be realized.

Whether or not to insert a surplus bit (execute a stuff operation) is determined by the phase comparison circuit 4 by using the write address signal W_ADR and the read address signal R_
Recognize by comparing to ADR. The execution of the phase comparison is performed every time the read address signal R_ADR performs one cycle. For example, a comparison is performed each time the R_ADR signal becomes “0”. If the read address R_ADR approaches the write address W_ADR below a certain value, the intermediate signal generation circuit 6 determines that stuff processing needs to be performed, Requests bit insertion.

A signal having a higher bit rate than the DS3 signal (an intermediate signal in the present invention) must satisfy the following conditions in order to suppress the occurrence of stuff jitter.

First, the overhead bit for inserting the stuff designation bit for transmitting the stuff operation execution to the transmission destination is not defined continuously (or concentrated / closely arranged) at least two bits. . Because DS
When restoring three signals, removing two or more (or concentrated / close) overhead bits results in clock loss of two or more clocks (or concentrated / close), which is a jitter. This is because it is an increasing factor. In addition, if there is a part that cannot be used as an information bit area for accommodating the DS3 signal due to other factors besides the overhead bit such as the stuff designation bit or the like, the part becomes a clock dropout part when restoring the DS3 signal. This is a factor of increasing jitter.

Secondly, the number of stuff designation bits needs to be large enough to make a majority decision. This is because, if the stuff designation bit is erroneous due to an error or the like, erroneous stuff processing is performed. As a result, the DS3 signal is shifted in bit phase, DS3 frame synchronization is lost, and a large number of bit errors (loss) are caused. This is because it will occur.

Third, the staff ratio Sr is empirically 0.1%.
A degree is desirable. If the stuff rate is too large, stuff jitter will increase.

Fourth, the frame length must be longer than the phase comparison performed in the cycle of the transmission elastic store capacity. In other words, it is necessary for the transmission elastic store reading to take at least one cycle until the effect of the stuff operation is reflected in the phase comparison result of the transmission elastic store. If the frame length is short, the next stuff execution will be determined before the effect of the stuffing is obtained, and the stuff will be executed unnecessarily for two consecutive frames, increasing the stuff jitter. .

As described above, if none of the above conditions can be satisfied, the stuff jitter generated when the DS3 signal is restored is increased.

Therefore, when an intermediate signal is introduced as in the present invention, it is possible to arbitrarily define and use an intermediate signal that satisfies the above conditions. By accommodating the intermediate signal synchronously, the amount of stuff jitter can be reduced. Further, there is an advantage that the VC type of the SDH signal as a transmission medium can be arbitrarily selected, and the stuff jitter generation amount can be kept low and constant regardless of the VC type.

FIG. 4 shows a signal format example of an intermediate signal satisfying the above conditions. The first and second conditions described above are satisfied by preparing three stuff designating bits, distributing stuff designating bits and fixed stuff bits / stuff bits in a frame, and setting the rest as an information bit area. . The fourth condition can be satisfied by setting the interval between the stuff designation bit and the next stuff designation bit and the interval between the stuff bit and the stuff designation bit, that is, the subframe length to be equal to or larger than the transmission elastic store capacity. Normally, the transmission elastic store capacity is sufficient to be 16 bits. Therefore, the number of bits per frame (frame length) in FIG.
Is 18 bits × 4 subframes = 72 bits or more.

The stuff ratio is expressed by the following equation. Sr = M × (N−1) −M × N × fl ÷ fh (1) Sr: Stuff rate M: Number of subframes per intermediate signal frame N: Number of bits per subframe fl: DS3 The signal bit rate fh: the bit rate of the intermediate signal.
The third condition can be satisfied by deciding that M is equal to or greater than 4 subframes, N is equal to or greater than 18 bits, and fh is equal to or less than the total bit rate of the SDH signal VC payload to be accommodated.

In FIG. 1, intermediate signal clock generation PL
The O circuit 16 generates an intermediate signal clock synchronized with the system clock dependent on the SDH network synchronization clock,
An intermediate signal is generated based on the intermediate signal clock.
Therefore, since the intermediate signal is synchronized with the system clock, it is possible to map (accommodate) the intermediate signal to the SDH signal without causing a slip. Further, the intermediate signal can be freely mapped to any type of VC (Virtual Container), and if the contents of accommodation (how) are matched between the transmitting end and the receiving end, the DS can be changed.
Transmission of three signals becomes possible.

According to this embodiment, the DS3 signal (44.736 Mbps ± 20 pp) which is an asynchronous digital signal is used.
m) is transmitted in a pulse stuff-synchronous manner with an intermediate signal having a bit rate higher than that of the DS3 signal, and the intermediate signal is synchronously accommodated in an SDH signal.
Asynchronous DS3 signals can be accommodated irrespective of the corresponding VC type of the VC switch function provided in the H transmission device, and stuff jitter generated when the original DS3 signal is restored on the receiving side can be reduced.

Next, another embodiment of the present invention will be described. FIG. 1 shows an example in which the intermediate signal is accommodated in seven VC-2 signals, but other VCs can also accommodate the intermediate signal. For example, when the VC-2 signal accommodates 28 VC-11 signals having a total bit rate of 44.8 Mb / s, the VC-2 mapping circuit 7 in FIG.
11 mapping circuit, the intermediate signal is divided into 28 and accommodated in the payload of 28 VC-11 signals,
Output to the signal generation circuit 8. Further, the VC-2 demapping circuit 10 is changed to VC-11 demapping,
28 VC-11 signals extracted by the H signal synchronizing circuit 9 are input, an intermediate signal divided from the payload of the VC-11 is extracted, and the intermediate signal is restored to one intermediate signal based on the intermediate signal clock. Output to the termination circuit 11.

Similarly, when the VC-2 signal is accommodated in one VC-3 signal having a total bit rate of 48.384 Mb / s, the VC-2 mapping circuit 7 in FIG.
-3 mapping circuit, and the VC-2 demapping circuit 10 changes to VC-3 demapping.

[0054]

As described above in detail, according to the present invention, an asynchronous DS3 signal is subjected to pulse stuff synchronization processing on an intermediate signal synchronized with a system clock in an SDH apparatus, thereby enabling a target SDH transmission apparatus. V provided by
Asynchronous DS3 signals can be accommodated without depending on the corresponding VC type of the C switch function. Since the data rate, frame format, and stuff rate of the intermediate signal can be selected so as to minimize stuff jitter, the stuff at the time of DS3 signal restoration can be performed without depending on the type and number of SDH signals VC that accommodate DS3 signals. The amount of jitter generation can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an SDH transmission apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of an SDH signal generated by the SDH signal generation circuit illustrated in FIG. 1;

FIG. 3 is a diagram illustrating an example of an SDH signal generated by the SDH signal generation circuit illustrated in FIG. 1;

4 is a diagram illustrating a format example of an intermediate signal generated by the intermediate signal generation circuit illustrated in FIG. 1;

[Explanation of symbols]

 1 B / U conversion & CLK extraction circuit 2 Write address generation counter circuit 3 Transmission elastic store circuit 4 Phase comparison circuit 5 Read address generation counter circuit 6 Intermediate signal generation circuit 7 VC-2 mapping circuit 8 SDH signal generation circuit 9 SDH signal synchronization Circuit 10 VC-2 demapping circuit 11 Intermediate signal termination circuit 12 DS3 clock generation PLO circuit 13 Reception elastic store circuit 14 U / B conversion circuit 15 SDH synchronous clock generation PG circuit 16 Intermediate signal clock generation PLO circuit

Claims (5)

[Claims] An asynchronous DS3 (Digital Signal-level)
3) In an SDH transmission apparatus for transmitting a signal by accommodating the signal in an SDH (Synchronous Digital Hierarchy) signal, a means for generating an intermediate signal synchronized with a system clock of the apparatus, and an asynchronous DS3 signal synchronized with the generated intermediate signal by pulse stuff synchronization An SDH transmission apparatus, comprising: means for processing and accommodating; and means for synchronously accommodating and transmitting an intermediate signal in which the asynchronous DS3 signal is stuffed and accommodated in an SDH signal. 2. The SDH transmission apparatus according to claim 1, wherein an intermediate signal clock which is a clock faster than an asynchronous DS3 signal frequency is generated from a system clock synchronized with the SDH network synchronization clock. 3. The SDH transmission apparatus according to claim 1, wherein an intermediate signal containing the asynchronous DS3 signal in stuff synchronization is divided and mapped into seven VC-2 signals by VC-2 mapping. 4. An intermediate signal accommodating the asynchronous DS3 signal in a stuff synchronous manner is VC-11 mapped by VC-11.
3. The SDH transmission apparatus according to claim 1, wherein division mapping is performed on 28 signals. 5. The SDH transmission apparatus according to claim 1, wherein a data rate, a frame format, and a stuff rate of the intermediate signal are selected so as to minimize stuff jitter.