JP2008092409A - Demapping method and circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide phase comparison signals without variations of a phase cycle even when there is a gap in client signals on the write side and to set a phase comparison cycle by a threshold, by using cyclic signals corresponding to a client data amount estimated to be stored in a demapping FIFO as the phase comparison signals being the phase reference of a phase locked loop for reproducing a client clock. <P>SOLUTION: In the demapping method, a virtual data amount counter 15 is provided, the virtual data amount of client data estimated to be stored in the demapping FIFO 12 is counted from the frame interval of received line data and the data amount of the period, and the phase comparison signals being the phase reference in the phase locked loop are generated on the basis of the count value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a demapping technique for extracting client data from line data transmitted in a frame format. In particular, it relates to the reproduction of a clock for outputting client data.

  FIG. 3 is a block diagram showing a conventional demapping circuit. This demapping circuit processes data according to the situation of the stuff byte included in the line data and extracts the client data included in the line data, and the client data extracted by the destuff processing circuit 21 A de-mapping FIFO 22 that temporarily stores data, a write address counter 23 that generates a write address to the de-mapping FIFO 22 based on a line clock, and a read address counter 24 that generates a read address of the de-mapping FIFO 22, As a phase-locked loop for synchronizing the count cycle of the read address counter 24 with the count cycle of the write address counter 23, a phase comparison circuit 25, a filter 26 and a voltage controlled oscillator (VCO) 27 are provided.

  The phase comparison circuit 25 compares the phase of the most significant bit of the count value of the write address counter 23 with the most significant bit of the count value of the read address counter 24. As a result, a client clock synchronized with the count cycle of the write address counter is obtained at the output of the voltage controlled oscillator 27. The read address counter 24 generates a read address for the demapping FIFO 22 based on the client clock.

JP-A-6-46084

The line data input to the demapping circuit includes overhead area and FEC (Forward
Error Correction) area exists and a gap occurs in the client signal on the writing side. For this reason, a shift occurs in the period of the most significant bit of the write address counter that should be the phase reference, and jitter also occurs in the phase comparison output. Such jitter needs to be smoothed by a filter, but for this purpose, a filter having a complicated configuration is required, and it is difficult to achieve both high response and response. ITU-T recommendation G. In order to support ODU (Optical Data Unit) multiplexing used in the optical transmission network defined in 709, the frame period differs from layer to layer, resulting in more irregular client signal gaps, making filter design more difficult become. In addition, since the phase comparison cycle depends on the demapping FIFO capacity, the phase comparison cycle cannot be freely selected, and thus there are significant restrictions on the circuit configuration.

  An object of the present invention is to solve such problems and to provide a demapping method and circuit capable of performing demapping processing by reproducing a client clock with a relatively simple configuration.

  According to the first aspect of the present invention, the storage means (demapping FIFO) for temporarily storing the client data included in the line data transmitted in the frame format, and the frequency of writing data to the storage means In a configuration comprising a phase-locked loop for reproducing a clock of client data and means for reading out client data from the storage means according to a clock output from the phase-locked loop, the frame interval of received line data and the amount of data in that period Virtual data amount counting that counts the virtual data amount of client data estimated to be accumulated in the accumulating means from the output and outputs a phase comparison signal as a phase reference in the phase-locked loop based on the counted value A demapping circuit comprising means is provided.

The virtual data amount counting means includes, for each line data of N frames, means for counting an interval T for receiving the line data of N frames, and a data amount a of client data when there is no stuffing process per frame, Data amount A of client data increased / decreased by destuffing processing during N frames, and value b obtained by rounding down the decimal point of the data amount output from the storage means virtually per clock at the clock of the pre-counting means b Against
I = aN-bT + A
Means for determining the virtual data amount I, and means for adding the virtual data amount I to the variable J over T clocks every clock by the clock of the counting means, and subtracting T from the variable J when the variable J is T or more And means for adding b to the variable K when the variable J is less than T, and adding b + 1 to the variable K when the variable J is equal to or greater than T, each time the variable K reaches a predetermined threshold S. And means for inverting the phase comparison signal output to the phase locked loop.

  According to the second aspect of the present invention, the client data included in the line data transmitted in the frame format is temporarily stored in the storage means, and the client is executed by the phase-locked loop corresponding to the frequency of data writing to the storage means. In the demapping method of reproducing a clock of data and reading out client data from the accumulating means according to the regenerated clock, it is estimated that the accumulating means accumulates from the frame interval of the received line data and the data amount during that period. There is provided a demapping method characterized by counting a virtual data amount of client data to be generated and generating a phase comparison signal as a phase reference in the phase locked loop based on the counted value.

The virtual data amount is counted for each N frame line data by counting the interval T at which the N frame line data is received, and when there is no stuff processing per frame, the client data amount a and N frame The data amount A of the client data increased or decreased by the destuffing process in between and the value b obtained by rounding off the decimal point of the data amount output from the storage means virtually per clock with the clock for counting the interval T And
I = aN-bT + A
The variable I is obtained, and the variable I is added to the variable J for every T clocks for counting the interval T. When the variable J is equal to or greater than T, T is subtracted from the variable J, and the variable J is less than T. In this case, b is added to the variable K, and b + 1 is added to the variable K when the variable J is equal to or greater than T. Every time the variable K reaches a predetermined threshold value S, an output is made to the phase-locked loop. It is preferable to invert the phase comparison signal.

  In the present invention, a periodic signal corresponding to the amount of client data estimated to be accumulated in the demapping FIFO is used as a phase comparison signal that serves as a phase reference of a phase locked loop for reproducing a client clock. Thereby, even if there is a gap in the client signal on the write side, a phase comparison signal with no variation in the phase period can be obtained. Further, the phase comparison period can be set by the threshold value S.

  In the present invention, the clock for counting the interval T may be slower than the clock for line data. In addition, the necessary calculations are simple and can be performed very easily. On the other hand, the phase comparison signal is smoothed, which reduces the burden of filter design. Since the filter and the VCO are often configured outside the LSI, this is also effective in terms of simplifying the external circuit. Furthermore, since the phase comparison period can be set freely, the degree of freedom in designing the phase locked loop is remarkably increased.

  FIG. 1 is a block diagram showing a demapping circuit according to an embodiment of the present invention.

  The demapping circuit destuffs the line data transmitted in the frame format to extract the client data included in the line data, and the demapping FIFO 12 temporarily stores the extracted client data. And a write address counter 13 that generates a write address to the demapping FIFO 12 based on the line clock, a read address counter 14 that generates a read address of the demapping FIFO 12, and a frequency of writing data to the demapping FIFO 12. A phase comparison circuit 16 as a phase-locked loop for reproducing the clock of client data, a filter 17, a voltage controlled oscillator 18 and a frequency dividing counter 19, and the read address counter 14 is connected to the voltage controlled oscillator 1. It generates a read address according to the client clock output of.

  Here, a feature of the present embodiment is that it includes a virtual data amount counter 15 that receives destuff information and frame information from the destuffing processing circuit 11, and this virtual data amount counter 15 determines the frame interval of the received line data. The virtual data amount of client data estimated to be accumulated in the demapping FIFO 12 is counted from the data amount during that period, and a phase comparison signal is output to the phase comparison circuit 16 based on the counted value. . The frequency division counter 19 in the phase locked loop is provided so as to correspond to the output period of the phase comparison signal of the virtual data amount counter 15.

  FIG. 2 is a flowchart for explaining the operation of the virtual data amount counter 15. The virtual data amount counter 15 repeats the following operation for each line data of N frames.

First, an interval T for receiving N frames of line data is counted (S1). The data amount a of client data when there is no stuffing process per frame, the data amount A of client data increased / decreased by the destuffing process between N frames, and the clock for counting the interval T are virtually per clock. For the value b obtained by rounding down the decimal point of the data amount output from the demapping FIFO 12,
I = aN-bT + A
A variable I is obtained (S2).

  Subsequently, the variable I is added to the variable J for each clock for counting the interval T (S3), and when the variable J is equal to or greater than T (S4), T is subtracted from the variable J (S5). When the variable J is less than T, b is added to the variable K (S7), and when the variable J is T or more, b + 1 is added to the variable K (S6). Each time the variable K reaches a predetermined threshold S (S8), the phase comparison signal output to the phase locked loop is inverted, and S is subtracted from the variable K (S9). This is repeated over T clocks (S10).

  The virtual data amount I represents the amount of data that is considered to remain in the storage means after the processing of N frames when data b is output every clock. In actuality, such data must be distributed in an almost even manner during N frames. Therefore, the variable J is calculated so that I outputs can be obtained almost equally during N frames (T clocks). Then, the output data amount should be increased by 1 for the I time. Therefore, the variable K, which is a value obtained by integrating the output data amount, represents the data amount to be output from the demapping FIFO 12. Each time the amount of data reaches a predetermined threshold value S, the phase comparison signal is inverted. The frequency division number of the frequency division counter 19 in the phase locked loop is set corresponding to the threshold value S.

As a specific example, a case where client data is demapped from an ODU2 frame will be described as an example. In this case, a = 15168 bytes. If T is counted with a clock of 84 MHz, b = 14 bytes can be obtained from the number of bytes included in the ODU2 frame, its bit rate, and the frequency of the clock. Therefore, the virtual data amount I is
I = 15168N-14T + A [bytes]
It becomes. Variable I is added to variable J every clock. When variable J is greater than or equal to T, T is subtracted from variable J. When variable J is less than T, variable K is 14 bytes, and variable J is greater than or equal to T. 15 bytes are added to the variable K, and every time the variable K reaches a predetermined threshold value S bytes, S is subtracted from the variable K and the phase comparison signal output to the phase comparison circuit 16 is inverted.

  Since the phase comparison signal is inverted every S bytes, the period corresponds to 2S bytes of the client clock. If the client clock output from the voltage controlled oscillator 18 is in units of bits, the frequency division number of the frequency division counter 19 may be 16S. If the threshold value S and the frequency division number of the frequency division counter 19 correspond to each other, these values can be freely selected.

  In the above embodiment, the case where the frequency dividing counter 19 is provided in the phase-locked loop has been described as an example. However, when the frequency dividing number of the read address counter 14 is a value corresponding to the threshold value S, the frequency dividing counter 19 Instead of using, the most significant bit of the read address counter 14 can be used. Further, the most significant bit output of the read address counter 14 can be processed and used.

The block block diagram which shows the demapping circuit of this invention Example. The flowchart explaining operation | movement of a virtual data amount counter. The block block diagram which shows the demapping circuit of a prior art example.

Explanation of symbols

11, 21 Destuffing processing circuit 12, 22 Demapping FIFO
13, 23 Write address counter 14, 24 Read address counter 15 Virtual data amount counter 16, 25 Phase comparison circuit 17, 26 Filter 18, 27 Voltage controlled oscillator 19 Frequency division counter

Claims (4)

Storage means for temporarily storing client data included in line data transmitted in a frame format;
A phase-locked loop that regenerates the clock of the client data corresponding to the frequency of data writing to the storage means;
In a demapping circuit comprising: means for reading out client data from the storage means according to a clock output from the phase-locked loop;
The virtual data amount of the client data estimated to be accumulated in the accumulation means is counted from the frame interval of the received line data and the data amount during that period, and based on the counted value, the phase in the phase-locked loop is counted. A demapping circuit comprising virtual data amount counting means for outputting a reference phase comparison signal. The virtual data amount counting means includes
Means for counting the interval T for receiving line data of N frames for each line data of N frames;
The data amount a of client data when there is no stuffing process per frame, the data amount A of client data increased / decreased by the destuffing process during N frames, and the clock of the counting means virtually per clock For the value b obtained by rounding down the decimal point of the data amount output from the storage means,
I = aN-bT + A
Means for determining the variable I
Means for adding the variable I to the variable J over T clocks every clock of the counting means, and subtracting T from the variable J when the variable J is equal to or greater than T;
Means for adding b to variable K when variable J is less than T, and adding b + 1 to variable K when variable J is greater than or equal to T;
The demapping circuit according to claim 1, further comprising: means for inverting a phase comparison signal output to the phase-locked loop every time the variable K reaches a predetermined threshold value S. The client data included in the line data transmitted in the frame format is temporarily stored in the storage means,
In response to the frequency of data writing to the storage means, the client data clock is regenerated by a phase-locked loop,
In a demapping method of reading client data from the storage means according to a regenerated clock,
Count the virtual data amount of the client data estimated to be stored in the storage means from the frame interval of the received line data and the data amount of that period,
A demapping method comprising: generating a phase comparison signal that serves as a phase reference in the phase-locked loop based on the count value. Virtual data count is
For each N frame line data, the interval T for receiving the N frame line data is counted,
Data amount a of client data when there is no stuffing process per frame, data amount A of client data increased / decreased by destuffing processing during N frames, and a clock for counting the interval T, virtually per clock For a value b obtained by rounding down the decimal point of the data amount output from the storage means,
I = aN-bT + A
To obtain the variable I
The variable I is added to the variable J over T clocks for each clock of the interval T.
Subtract T from variable J when variable J is greater than or equal to T
When variable J is less than T, b is added to variable K,
If variable J is greater than or equal to T, add b + 1 to variable K,
The demapping method according to claim 3, wherein the phase comparison signal output to the phase-locked loop is inverted every time the variable K reaches a predetermined threshold value S.

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