JP2001345425A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rapidly discharge a charge generated by a plasma process to the rear of a semiconductor substrate and to prevent a gate insulating film from being broken in the manufacturing method of a semiconductor integrated circuit device. SOLUTION: A semiconductor integrated circuit device is constituted in a structure that a conductive film is embedded in wiring grooves 19 formed in an insulating film 17 and connection holes to reach a p-type well 9, and the excessive conductive film on the film 17 is removed by a polishing using a CMP method. A wiring layer 21, a charge take-out part 2 and a charge discharge layer 6, which are used as routes for discharging a charge generated by a plasma process to the rear of a semiconductor substrate of the device, are formed in the film 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a technology for manufacturing a semiconductor integrated circuit device in which wiring is formed by a plasma process.

[0002]

2. Description of the Related Art MISFET (Metal Insulator Semico)
In a manufacturing process of a semiconductor integrated circuit device having an nductor field effect transistor), a plasma process is frequently used.

In general, in the step of forming circuit elements and wirings in a plasma process, the wirings thus formed serve as an antenna, and a high voltage is applied to a gate electrode to collect electric charges generated by plasma. Causes membrane destruction. The inventor has investigated prior art examples in terms of a technique for avoiding the destruction of a gate oxide film in a step of forming a wiring by a plasma process. As a result, the following technology was discovered, although it was not a known technology.

That is, when a semiconductor element, a circuit element and a wiring are formed on the main surface of a bulk substrate, a diffusion layer and a gate electrode are connected by a metal wiring or an LI (Local Inter Connect) layer and generated by plasma. The discharged charges are discharged to the back surface of the bulk substrate through the well.

When a semiconductor element, a circuit element, and a wiring are formed on the main surface of an SOI (Silicon On Insulator) substrate, there is no path for directly discharging charges generated by plasma to the back surface of the SOI substrate. The diffusion layer and the gate electrode are connected by the LI layer, and the electric charge is transferred to the SOI.
A method is used in which the semiconductor substrate (wafer) is released from the edge to the back along the oxide layer of the substrate. Further, the diffusion layer and the gate electrode are connected by metal wiring or LI layer, and SO
A method of discharging electric charges to the back surface of the SOI substrate by forming a portion having no oxide film on the oxide film layer of the I substrate is also employed.

[0006]

However, a semiconductor element, a circuit element, and a wiring are formed on a main surface of an SOI substrate.
The following problem arises in the prior art in which the charge generated by the plasma is released from the end of the SOI substrate to the back surface along the oxide film layer of the SOI substrate.

That is, since the electric charge is released from the end of the semiconductor substrate (wafer) to the back surface along the oxide film layer of the SOI substrate, the moving distance of the electric charge is increased, and the substrate resistance is increased. As a result, the discharge of electric charges is delayed, and the voltage applied to the gate electrode is increased. In addition, M in the charge release path
The charge concentrates on the substrate side of the ISFET and the MISFET
May be destroyed.

Further, the diffusion layer and the gate electrode are connected by a metal wiring or an LI layer, and a portion without an oxide film is formed in the oxide film layer of the SOI substrate, so that the electric charge is reduced.
In the conventional technology for emitting light to the back surface of the I-substrate, the following problem occurs.

That is, by forming a portion having no oxide film in the oxide film layer of the SOI substrate, charges are discharged to the back surface of the SOI substrate, so that the increase in substrate resistance can be reduced. The number of steps for forming a portion without an oxide film increases, leading to an increase in cost.

An object of the present invention is to provide a technique for forming a wiring by a plasma process without destroying a gate oxide film of a MISFET.

Another object of the present invention is to provide a technique for forming a wiring by a plasma process without increasing the number of steps.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps. (A) forming a plurality of semiconductor chip regions on a main surface of a semiconductor substrate;
(B) forming a first conductive layer for electrically connecting a semiconductor element and the semiconductor substrate in each semiconductor chip area;
(C) forming a second conductive layer surrounding each semiconductor chip region and partially electrically connected to the back surface of the semiconductor substrate;

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps. (A) forming a plurality of semiconductor chip regions on a main surface of a semiconductor substrate;
(B) forming a first conductive layer for electrically connecting a semiconductor element and the semiconductor substrate in each semiconductor chip area;
(C) forming a second conductive layer surrounding each semiconductor chip region; and (d) forming a third conductive layer electrically connected to the back surface of the semiconductor substrate outside the plurality of semiconductor chip regions. .

According to the manufacturing methods (1) and (2),
In order to simultaneously form the LI layer or the lowermost wiring as the first conductive layer, the charge extracting portion or the charge emitting layer as the second conductive layer, and the charge emitting layer as the third conductive layer, the charges generated by the plasma process are formed. Can be formed without increasing the number of steps.

Further, according to the above-described manufacturing method, the electric charge generated by the plasma process is transferred to the LI layer or the lowermost wiring, which is the first conductive layer, which serves as a charge discharging path, or the charge extracting portion, which is the second conductive layer. Through the charge emission layer and the charge emission layer serving as the third conductive layer, the semiconductor layer is rapidly emitted to the back surface of the semiconductor substrate, and a high voltage can be prevented from being applied to the gate electrode.

Further, according to the above manufacturing method,
The charge generated by the plasma process is rapidly released to the back surface of the semiconductor substrate to prevent a high voltage from being applied to the gate electrode.
The reliability and yield of the semiconductor integrated circuit device can be improved.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

Embodiment 1 FIG. 1 is a plan view showing an example of a semiconductor chip on which a semiconductor integrated circuit device manufactured according to the present invention is mounted. A charge extraction portion (second conductive layer) 2 (a guard ring portion or a scribe portion) having a wiring layer or an LI layer pattern serving as a discharge path of charges generated by a plasma process is formed on an outer peripheral portion of the semiconductor chip 1. Although not shown, the wiring inside the semiconductor chip 1 is electrically connected to the charge extracting portion 2.

FIG. 2 is an enlarged plan view of the area indicated by A in FIG. The adjacent semiconductor chip 1 is shown in FIG.
As shown in FIG. 2A, they are electrically connected by a connection pattern 3, or as shown in FIG. 2B, the charge extraction portions 2 of the adjacent semiconductor chips 1 are directly electrically connected to each other. It is connected to the. In the case where the connection pattern 3 is used, the cut portion at the time of separating the semiconductor chip 1 is reduced, so that the load on the dicer is reduced and the semiconductor chip 1 can be prevented from breaking.

FIG. 3 is a plan view showing an example of a semiconductor substrate (wafer) on which the semiconductor chip 1 is formed. Non-semiconductor chip area (semiconductor substrate outer peripheral part) 4 shown in FIG.
Since the charge extraction pattern 2a electrically connected to the charge extraction unit 2 is patterned, all the charge extraction units 2 are electrically connected to the non-semiconductor chip region (semiconductor substrate outer peripheral portion) 4. And finally discharge the electric charge from the semiconductor substrate (wafer) end portion 5 to the back surface of the semiconductor substrate.

As shown in FIG. 5, instead of patterning the charge extracting portion 2 in the non-semiconductor chip region (peripheral portion of the semiconductor substrate) 4, instead of patterning the entire surface wiring layer or a dummy pattern, a charge emitting layer (third layer) is used. A conductive layer 6 may be formed. At this time, the entire surface of the charge emission layer 6 does not necessarily have to be metal.

In the case where the semiconductor chip 1 is formed at a position sufficiently close to discharge electric charges from the semiconductor wafer edge 5 to the back surface of the semiconductor substrate, the non-semiconductor chip region (the semiconductor wafer outer peripheral portion) is formed. 4), it is not necessary to form the guard ring portion or the scribe portion 2 or the charge emission layer 6.

Next, a method of manufacturing the semiconductor integrated circuit device manufactured in the first embodiment will be described with reference to FIGS.

[0026] First, as shown in FIG. 6, hyperoxia implantation or the like p having an SOI insulating layer 8 formed by ^- in preparing a semiconductor substrate 7 made of type single-crystal silicon, p-type conductivity , For example, boron is introduced by ion implantation or the like to form the p-type well 9. The p
The mold well 9 may be doped by mixing an impurity gas during epitaxial growth by the high-concentration oxygen implantation method.

Subsequently, a groove 10 is formed on the main surface of the semiconductor substrate 7.
After that, for example, a silicon oxide film is deposited to bury the silicon oxide film in the trench 10,
The excess silicon oxide film is removed by using an MP (Chemical Mechanical Polishing) method or the like, and the element isolation region 1 is removed.
Form one.

Subsequently, a silicon oxide film serving as a gate insulating film 12 and a gate electrode 13 are formed on the main surface of the semiconductor substrate 7.
A polycrystalline silicon film to become a film and a silicon oxide film to become a cap insulating film 14 are sequentially deposited to form a laminated film, and the laminated film is etched using a resist patterned by a photolithography technique as a mask to form a gate electrode 13 and a cap. An insulating film 14 is formed. The gate insulating film 12 can be deposited by, for example, a thermal CVD method, and the polycrystalline silicon film forming the gate electrode 13 can be deposited by a CVD method. However, in order to reduce the resistance value of the gate electrode 13, Is doped with an n-type impurity (for example, phosphorus). The upper the WSi _x of the polycrystalline silicon film, MoSi _x, TiSi _x, may be stacked refractory silicide film such as TaSi _x and CoSi _x. The silicon oxide film serving as the cap insulating film 14 includes:
For example, it can be deposited by a CVD method.

Next, after a silicon oxide film is deposited on the semiconductor substrate 7 by a CVD method, the silicon oxide film is anisotropically etched by a reactive ion etching (RIE) method to thereby form the gate electrode 13. Side wall spacers 15 are formed on the side walls. Subsequently, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 9 and an n-channel MI
An impurity semiconductor region 16 forming the source and drain regions of the SFET Qn is formed. Note that a low-concentration impurity semiconductor region may be formed before the sidewall spacer 15 is formed, and a high-concentration semiconductor region may be formed after the sidewall spacer 15 is formed.

Next, as shown in FIG. 7, after a silicon oxide film is deposited on the semiconductor substrate 7 by a sputtering method or a CVD method, for example, the silicon oxide film is
By polishing by the P method, the insulating film 17 whose surface is flattened is formed.

Next, as shown in FIG. 8, a connection hole 18 and a wiring groove 19 are formed in the insulating film 17 on the semiconductor substrate 7 by using a photolithography technique.

Next, as shown in FIG. 9, a barrier conductor film is formed on the entire surface of the semiconductor substrate 7 to improve adhesion of a copper film deposited in a subsequent step and prevent copper diffusion, for example. Deposit a titanium nitride film. The titanium nitride film can be deposited by, for example, a CVD method or a sputtering method, and has a thickness of about 500 °. In the first embodiment, a titanium nitride film is illustrated, but a metal film of a metal film such as tantalum or a tantalum nitride film may be used. When the barrier film is tantalum or tantalum nitride, titanium nitride is used. Adhesion with the copper film is better than when used. Further, it is also possible to sputter-etch the surface of the titanium nitride film immediately before depositing the copper film, which is a subsequent step. By such a sputter etch, water, oxygen molecules and the like adsorbed on the surface of the titanium nitride film can be removed, and the adhesiveness of the copper film can be improved. In particular, the effect is great when the copper nitride film is deposited by vacuum breaking after the deposition of the titanium nitride film to expose the surface to the atmosphere.

Subsequently, a main conductive layer is formed on the insulating film 17 to fill the connection holes 18 and the wiring grooves 19.
For example, a copper film is deposited, heat-treated and fluidized,
The conductive film 20 is formed together with the titanium nitride film. For the deposition of the copper film, a normal sputtering method can be used, but a physical vapor deposition method such as an evaporation method or a plating method may be used. When the plating method is used, it is necessary to deposit a seed film before depositing a copper thin film, and the seed film is deposited by a sputtering method. The heat treatment requires a temperature and a time at which the copper film is fluidized, and examples thereof include about 400 ° C. to 450 ° C. and about 3 minutes to 5 minutes. Although a copper film is exemplified in the first embodiment, a metal film having a lower resistance value than the resistance value of the SOI insulating layer 8 in a direction parallel to the semiconductor substrate 7 may be used.

Next, as shown in FIG.
7 is removed by polishing using a CMP method, and the conductive film 20 is left inside the connection hole 18 and the wiring groove 19 to form a wiring layer (first layer).
The conductive layer 21, the charge extraction portion 2, and the charge emission layer 6 are formed. As a result, in the subsequent steps,
When performing processes such as film formation by a sputtering method or a CVD method, removal of a photoresist film by ashing (carbonization), etching, and doping of semiconductor impurities by a plasma process, electric charges generated by the plasma are removed.
According to the charge emission path via the wiring layer 21, the p-type well 9, the charge extraction portion 2 and the charge emission layer 6 shown in FIG. Therefore, it is possible to prevent a high voltage from being applied to the gate electrode 13 and prevent the gate insulating film 12 from being broken.

Further, the wiring layer 21, the charge extraction section 2, and the charge emission layer 6, which correspond to the charge emission path,
Are formed at the same time, so that the number of steps is reduced as compared with the case where a charge emission path is formed by forming a conductive portion in the SOI insulating layer, and the manufacturing cost can be reduced.

Next, as shown in FIG. 11, a silicon nitride film is deposited on the entire surface of the semiconductor substrate 7, and a barrier insulating film 22 is deposited. For deposition of this silicon nitride film, for example, a plasma CVD method can be used, and its thickness is set to about 50 nm. The barrier insulating film 22 includes the wiring layer 21, the charge extraction section 2, and the charge emission layer 6.
Has the function of suppressing the diffusion of copper forming the main conductive layer. As a result, the insulating film 2 deposited in the subsequent process
3 can be prevented from diffusing, the insulating property of the insulating film 23 can be maintained, and the reliability of the semiconductor integrated circuit device can be improved. The barrier insulating film 22 also functions as an etch stopper when etching is performed in a later step.

Subsequently, an insulating film 23 having a thickness of about 400 nm is deposited on the surface of the barrier insulating film 22, and the semiconductor integrated circuit device of the first embodiment is substantially completed. The insulating film 23
May be an SOG film deposited by a coating method, a low dielectric constant film such as a CVD oxide film to which fluorine is added, a silicon nitride film, or a combination of a plurality of types of insulating films. When the dielectric constant film is used, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be reduced, and the wiring delay can be improved.

According to the method of manufacturing a semiconductor integrated circuit device of the first embodiment, the charge generated by the plasma process is transferred to the wiring layer 21, the charge extracting portion 2, and the charge emitting layer 6.
Is rapidly released to the back surface of the semiconductor substrate 7 through the gate insulating film 12, thereby preventing the gate insulating film 12 from being broken. for that reason,
It is possible to improve the reliability and yield of the semiconductor integrated circuit device.

(Second Embodiment) In a method of manufacturing a semiconductor integrated circuit device according to a second embodiment, an LI layer is formed below a lowermost wiring layer 21 and generated by a plasma process using the LI layer as a path. The charge is emitted to the back surface of the semiconductor substrate 1. Other members and processes are described in Embodiment 1.
Is the same as Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

The method of manufacturing the semiconductor integrated circuit device of the second embodiment is the same as that of the first embodiment described with reference to FIG.

Thereafter, as shown in FIG. 12, for example, a copper film is deposited on the main surface of the semiconductor substrate 7 by a sputtering method. Subsequently, the copper film is etched to form an LI layer (first conductive layer) 25, a charge extraction portion (second conductive layer) 2, and a charge emission layer (third conductive layer) 6. As a result, in the subsequent processes, when a process such as film formation by a sputtering method or a CVD method, removal of a photoresist film by ashing (carbonization), etching, and doping of semiconductor impurities is performed by a plasma process, the plasma generated. Charges can be rapidly released to the back surface of the semiconductor substrate 7 according to a charge release path passing through the LI layer 25, the p-type well 9, the charge extraction portion 2 and the charge release layer 6 shown in FIG. Therefore, it is possible to prevent a high voltage from being applied to the gate electrode 13 and prevent the gate insulating film 12 from being broken.

The LI corresponding to the charge discharging path
Layer 25, charge extraction section 2 and charge emission layer 6
Are formed at the same time, so that the number of steps is reduced as compared with the case where a charge emission path is formed by forming a conductive portion in the SOI insulating layer, and the manufacturing cost can be reduced.

Thereafter, in Embodiment 1, FIGS.
The semiconductor integrated circuit device according to the second embodiment is substantially completed through the same steps as those described with reference to FIG. 1 (FIG. 13).

According to the method of manufacturing a semiconductor integrated circuit device of the second embodiment, the charge generated by the plasma process is transferred to the LI layer 25, the charge extracting section 2, and the charge emitting layer 6.
Is rapidly released to the back surface of the semiconductor substrate 7 through the gate insulating film 12, thereby preventing the gate insulating film 12 from being broken. for that reason,
It is possible to improve the reliability and yield of the semiconductor integrated circuit device.

(Embodiment 3) A method of manufacturing a semiconductor integrated circuit device according to Embodiment 3 is directed to a case where the element isolation region 11 and the gate electrode 13 are also patterned in the non-semiconductor chip region 4 on the outer periphery of the semiconductor wafer. To which the technology of the present invention is applied. Other members and steps are the same as those of the first or second embodiment, and therefore, description of those same members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

The method of manufacturing the semiconductor integrated circuit device according to the third embodiment is the same as that described with reference to FIG. 6 in the first embodiment, but as shown in FIG. 14, a semiconductor substrate (wafer) The element isolation region 11, the gate insulating film 12, the gate electrode 13, the cap insulating film 14, and the sidewall spacer 15 are also formed in the non-semiconductor chip region 4 in the outer peripheral portion.
Are formed simultaneously with the element isolation region 11, the gate insulating film 12, the gate electrode 13, the cap insulating film 14, and the sidewall spacer 15 in the semiconductor chip formation region.

Next, the LI layer (first conductive layer) 25, the charge extracting portion (second conductive layer) 2, and the charge emitting layer are formed in the same steps as those described in the second embodiment with reference to FIG. (Third conductive layer) 6 is formed. Since the LI layer 25, the charge extraction portion 2, and the charge emission layer 6 which are in the charge emission path are formed simultaneously, the SOI
By forming a conductive portion in the insulating layer, the number of steps is reduced as compared with the case where a charge emission path is formed, so that manufacturing cost can be reduced.

Thereafter, in Embodiment 1, FIGS.
The semiconductor integrated circuit device according to the third embodiment is substantially completed through the same steps as those described with reference to FIG. 1 (FIG. 15).

According to the method of manufacturing the semiconductor integrated circuit device of the third embodiment, the charges generated by the plasma process are discharged through the LI layer 25, the charge extraction section 2 and the charge release layer 6 shown in FIG. It can be rapidly released to the back surface of the semiconductor substrate 7 along the route. Therefore, it is possible to prevent a high voltage from being applied to the gate electrode 13 and prevent the gate insulating film 12 from being broken. as a result,
It is possible to improve the reliability and yield of the semiconductor integrated circuit device.

(Fourth Embodiment) In the method of manufacturing a semiconductor integrated circuit device according to the fourth embodiment, a charge extracting portion is also formed inside the semiconductor chip 1 to further improve the efficiency of extracting charges generated by the plasma process. It was done.
Other members and steps are the same as those of the first, second, or third embodiment, and therefore, description of those similar members and steps will be omitted.

FIG. 16 is a plan view showing an example of a semiconductor substrate (wafer) on which the semiconductor chip 1 of the fourth embodiment is formed. In the first embodiment, an example is described in which the charge generated by the plasma process is extracted from the charge extracting portion (second conductive layer) 2 (guard ring portion or scribe portion). However, in the fourth embodiment, the semiconductor is extracted. Charge extraction part (first conductive layer) inside chip 1
26, the charge is taken out to the charge take-out portion 26 even near the charge generation location, and the charge is discharged to the back surface of the semiconductor substrate according to the charge release path,
The charge extraction efficiency can be further improved.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIG.

The manufacturing method of the semiconductor integrated circuit device according to the fourth embodiment is the same as the process described in the first embodiment with reference to FIGS. Take-out section 26 for electrically connecting
Are formed at the same time in the step of forming the charge extraction portion 2 and the wiring layer 21. Therefore, the number of steps is reduced as compared with the case where a charge emission path is formed by forming a conductive portion in the SOI insulating layer, and the manufacturing cost can be reduced. Further, as shown in FIG. 17, in addition to the charge discharging path from the wiring layer 21 to the charge extracting portion 2 via the p-type well 9, the wiring layer 21
Thus, a charge discharge path is formed to be connected to the charge extracting section 2 through the charge extracting section 26, so that charges generated by the plasma process can be more effectively released to the back surface of the semiconductor substrate 7. for that reason,
It is possible to prevent a high voltage from being applied to the gate electrode 13 and more effectively prevent the gate insulating film 12 from being broken. As a result, the reliability and yield of the semiconductor integrated circuit device can be further improved.

In the fourth embodiment, an example has been described in which the charge extracting portion 2 and the wiring layer 21 of the semiconductor integrated circuit device shown in the first embodiment are electrically connected by the charge extracting portion 26. However, in the semiconductor integrated circuit devices shown in the second and third embodiments, the charge extracting portion 2 and the wiring layer 21 are similarly formed.
Can be electrically connected by the charge extracting portion 26.

(Fifth Embodiment) A method of manufacturing a semiconductor integrated circuit device according to a fifth embodiment employs a wiring layer (first conductive layer) 21.
Charge extraction part (second conductive layer) 2 and charge emission layer (third conductive layer)
The charge generated by the plasma process is discharged to the back surface of the semiconductor substrate 7 by forming a multilayer charge extraction portion and a charge release layer on the upper layer 6. Other members and steps are the same as those in the first embodiment. Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

In the method of manufacturing the semiconductor integrated circuit device of the fifth embodiment, the steps described in the first embodiment with reference to FIGS. 6 to 11 are the same.

Thereafter, as shown in FIG. 18, a connection hole 27 and a wiring groove 28 are formed in the barrier insulating film 22 and the insulating film 23 by using a photolithography technique.

Next, as shown in FIG.
Is deposited on the entire surface of the substrate, for example, a titanium nitride film serving as a barrier conductor film for improving adhesion of a copper film deposited in a subsequent step and preventing copper diffusion. The titanium nitride film can be deposited by, for example, a CVD method or a sputtering method, and has a thickness of about 500 °. Although a titanium nitride film is exemplified in the fifth embodiment, a metal film of a metal film such as tantalum or a tantalum nitride film may be used. In the case where the barrier film is tantalum or tantalum nitride, titanium nitride is used. Adhesion with the copper film is better than when used. Further, it is also possible to sputter-etch the surface of the titanium nitride film immediately before depositing the copper film, which is a subsequent step. By such a sputter etch, water, oxygen molecules and the like adsorbed on the surface of the titanium nitride film can be removed, and the adhesiveness of the copper film can be improved. In particular, the effect is great when the copper nitride film is deposited by vacuum breaking after the deposition of the titanium nitride film to expose the surface to the atmosphere.

Subsequently, a main conductive layer is formed on the insulating film 23 to fill the connection holes 27 and the wiring grooves 28.
For example, a copper film is deposited and heat-treated to fluidize.
For the deposition of the copper film, a normal sputtering method can be used, but a physical vapor deposition method such as an evaporation method or a plating method may be used. When the plating method is used, it is necessary to deposit a seed film before depositing a copper thin film, and the seed film is deposited by a sputtering method. In addition, the condition of the treatment requires a temperature and a time at which the copper film is fluidized, for example, about 400 ° C. to 450 ° C. and about 3 minutes to 5 minutes. Although a copper film is exemplified in the fifth embodiment, a metal film having a resistance lower than the resistance of the SOI insulating layer 8 in a direction parallel to the semiconductor substrate 7 may be used.

Subsequently, the excess titanium nitride film and copper film on the insulating film 23 are removed by polishing using a CMP method, and the titanium nitride film and the copper film are formed inside the connection holes 27 and the wiring grooves 28. By leaving the copper film, a wiring layer 29, a charge extraction portion (second conductive layer) 30, and a charge emission layer (third conductive layer) 31 are formed. When the wiring layer is formed as a multi-layered wiring layer such that the wiring layer 29 is formed above the wiring layer 21, the charge generated by the plasma process in which the wiring layer becomes an antenna and collects as the number of wiring layers increases. The amount also increases. Since the amount of electric charge generated by the plasma process becomes larger in the upper wiring layer, the electric charge extracting section 30 and the electric charge emitting layer 31 are formed above the electric charge extracting section 2 and the electric charge emitting layer 6. As a result, the charge generated by the plasma can be rapidly released to the back surface of the semiconductor substrate 7 according to the charge release path shown in FIG. Therefore, it is possible to prevent a high voltage from being applied to the gate electrode 13 and prevent the gate insulating film 12 from being broken.

Further, since the wiring layer 29, the charge extracting portion 30, and the charge emitting layer 31 are formed at the same time, the number of steps is reduced, and the manufacturing cost can be reduced.

Next, as shown in FIG. 20, a barrier insulating film 32 is deposited on the entire surface of the semiconductor substrate 7 by depositing a silicon nitride film. For deposition of this silicon nitride film, for example, a plasma CVD method can be used, and its thickness is set to about 50 nm. The barrier insulating film 32 has a function of suppressing the diffusion of copper forming the main conductive layer of the wiring layer 29, the charge extraction portion 30, and the charge emission layer 31. Thus, diffusion of copper into the insulating film 33 deposited in the subsequent step can be prevented, the insulating property of the insulating film 33 can be maintained, and the reliability of the semiconductor integrated circuit device can be improved. The barrier insulating film 32 also functions as an etch stopper layer when etching is performed in a later step.

Subsequently, an insulating film 33 having a thickness of about 400 nm is deposited on the surface of the barrier insulating film 32, and the semiconductor integrated circuit device according to the first embodiment is substantially completed. The insulating film 33
May be an SOG film deposited by a coating method, a low dielectric constant film such as a CVD oxide film to which fluorine is added, a silicon nitride film, or a combination of a plurality of types of insulating films. When the dielectric constant film is used, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be reduced, and the wiring delay can be improved.

In the fifth embodiment, the semiconductor integrated circuit device shown in the first embodiment is different from the semiconductor integrated circuit device in the first embodiment in that a multi-layered wiring layer 29, charge extraction section 30 and charge emission layer 31 are provided.
Is formed, but in the semiconductor integrated circuit devices described in the second and third embodiments, similarly, the multi-layered wiring layer 29, the charge extraction portion 30, and the charge emission layer 31 are similarly formed. It is possible.

(Embodiment 6) In a method of manufacturing a semiconductor integrated circuit device according to Embodiment 6, an
The present invention is applied when reaching the insulating layer 8. Other members and steps are the same as those of the first or second embodiment. Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

First, as shown in FIG. 21, a p-type well 9 and a trench 10 are formed in a semiconductor substrate 7 having an SOI insulating layer 8 in the same steps as those described with reference to FIG. And an element isolation region 11 are sequentially formed.
At this time, since a part of the trench 10 reaches the SOI insulating layer 8, a part of the element isolation region 11 reaches the SOI insulating layer 8.

Next, as shown in FIG. 22, the LI layer (first conductive layer) 25 and the charge extraction portion (first conductive layer) 25 are formed in the same steps as those described with reference to FIG. The conductive layers 26 and 2b (second conductive layer) and the charge emission layer (third conductive layer) 6a are formed.

Thereafter, in Embodiment 1, FIGS.
The semiconductor integrated circuit device according to the sixth embodiment is substantially completed through the same steps as those described with reference to FIG. 1 (FIG. 23).

When the element isolation region 11 reaches the SOI insulating layer 8, in a region surrounded by the element isolation region 11 reaching the SOI insulating layer 8, a path for releasing charges generated by the plasma process is: Leakage current from the element isolation region 11 or impurity semiconductor region 16
Therefore, charge is likely to accumulate only through the wiring connected to. According to the method of manufacturing the semiconductor integrated circuit device of the sixth embodiment, since the charge extracting portion 26 is formed inside the semiconductor chip 1, the charges generated by the plasma process are transferred along the charge discharging path shown in FIG. It is possible to rapidly emit the light to the back surface of the semiconductor substrate 7. Therefore, it is possible to prevent a high voltage from being applied to the gate electrode 13 and prevent the gate insulating film 12 from being broken.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first embodiment, the case where the structure of the well is a p-type well is described, but a rectifying junction of an n-type well and a p-type well may be used. The junction area between the gate and the p-type well can be made sufficiently large so as not to hinder the charge emission.

Further, for example, in the sixth embodiment, the case where the charge emission path is formed by using the LI layer and the wiring layer is described, but only one of the LI layer and the wiring layer may be used. .

[0077]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows. (1) A path for discharging charges generated by the plasma process can be formed without increasing the number of steps. (2) The charge generated by the plasma process is rapidly released to the back surface of the semiconductor substrate, and a high voltage can be prevented from being applied to the gate electrode. (3) The gate insulating film can be prevented from being broken, and the reliability and yield of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a main part plan view showing an example of a semiconductor chip on which a semiconductor integrated circuit device according to a first embodiment of the present invention is formed;

FIG. 2 is an enlarged plan view of a main part of the semiconductor chip shown in FIG.

FIG. 3 is a plan view of a main part of a semiconductor substrate (wafer) on which the semiconductor chip shown in FIG. 1 is formed.

FIG. 4 is a plan view of a principal part for explaining a non-chip region of a semiconductor substrate (wafer).

5 is a plan view of a main part of a semiconductor substrate (wafer) on which the semiconductor chip shown in FIG. 1 is formed.

FIG. 6 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1 of the present invention.

7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9;

11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10;

FIG. 12 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 2 of the present invention.

13 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 12;

FIG. 14 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 3 of the present invention.

15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14;

FIG. 16 is an essential part plan view showing one example of a semiconductor chip on which a semiconductor integrated circuit device according to a fourth embodiment of the present invention is formed;

FIG. 17 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 4 of the present invention.

FIG. 18 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 5 of the present invention.

19 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 18;

20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;

FIG. 21 is an essential part cross sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 6 of the present invention.

FIG. 22 is an essential part cross sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 21;

23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 22;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor chip 2 charge extraction portion (second conductive layer) 2 a charge extraction pattern 2 b charge extraction portion (second conductive layer) 3 connection pattern 4 non-semiconductor chip region (peripheral portion of semiconductor wafer) 5 semiconductor substrate (wafer) end Reference Signs List 6 charge-emitting layer (third conductive layer) 6a charge-emitting layer (third conductive layer) 7 semiconductor substrate 8 SOI insulating layer 9 p-type well 10 trench 11 element isolation region 12 gate insulating film 13 gate electrode 14 cap insulating film 15 side Wall spacer 16 impurity semiconductor region 17 insulating film 18 connection hole 19 wiring groove 20 conductive film 21 wiring layer (first conductive layer) 22 barrier insulating film 23 insulating film 25 LI layer (first conductive layer) 26 charge extracting portion (first 1 conductive layer) 27 connection hole 28 wiring groove 29 wiring layer 30 charge extraction portion (second conductive layer) 31 charge release layer (second conductive layer) Conductive layer) 32 barrier insulating film 33 insulating film Qn n-channel type MISFET

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masaya Iida 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Fumio Otsuka 6-16-16 Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi, Ltd. Device Development Center (reference) BH20 CA01 CA12 CA13 CD01 CD09 EZ06 EZ11 EZ13 EZ14 EZ15 EZ16 EZ17 EZ20 5F110 AA16 AA26 CC02 DD05 EE05 EE09 EE14 EE32 EE45 FF02 FF29 GG02 GG12 GG32 GG52 HJ01 HJ13 NN02 NN23 NN02 NN23 NN02 NN23 NN15

Claims (4)

[Claims] (A) forming a plurality of semiconductor chip regions on a main surface of a semiconductor substrate; and (b) a first conductive layer for electrically connecting a semiconductor element and the semiconductor substrate within each semiconductor chip region. Forming a layer, and (c) forming a second conductive layer surrounding each semiconductor chip region, wherein a part of the second conductive layer is electrically connected to a back surface of the semiconductor substrate at an end of the semiconductor substrate. A method for manufacturing a semiconductor integrated circuit device, comprising: (A) forming a plurality of semiconductor chip regions on a main surface of a semiconductor substrate; and (b) a first conductive layer for electrically connecting a semiconductor element and the semiconductor substrate in each semiconductor chip region. Forming a layer, (c) forming a second conductive layer surrounding each of the semiconductor chip regions, and (d) a third electrically connected to a back surface of the semiconductor substrate outside the plurality of semiconductor chip regions. A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a conductive layer. 3. A step of forming a plurality of semiconductor chip regions on a main surface of a semiconductor substrate, and b. A first conductive layer for electrically connecting a semiconductor element and the semiconductor substrate in each semiconductor chip region. Forming a layer, and (c) forming a second conductive layer surrounding each semiconductor chip region and partially electrically connected to a back surface of the semiconductor substrate, wherein the semiconductor substrate has an SOI insulating layer. A method for manufacturing a semiconductor integrated circuit device, comprising: 4. A semiconductor device comprising: (a) forming a plurality of semiconductor chip regions on a main surface of a semiconductor substrate; and (b) a first conductive layer for electrically connecting a semiconductor element and the semiconductor substrate in each semiconductor chip region. Forming a layer, (c) forming a second conductive layer surrounding each semiconductor chip region, and (d) a third electrically connected to the back surface of the semiconductor substrate outside the plurality of semiconductor chip regions. Forming a conductive layer, wherein the semiconductor substrate has an SOI insulating layer.