JP2001332582A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of a circuit board flip-chip-mounted with a semiconductor chip and method of manufacturing the same, wherein a repair work or reworking is possible for the chip and even a bare chip for area wiring of a fine pitch can be flip-chip-mounted. SOLUTION: Ni plating bumps 14 are formed on Al pad sections 12 on the surface of a bare chip 10, and an Ag- or AgPa-based conductive adhesive 20 is printed on wiring electrodes 18 on the surface of a circuit board 16. The bare chip 10 is placed facedown on the circuit board 16, with the leading edges of the Ni plating bumps 14 of the bare chip 10 inserted into an upper face of the cured conductive adhesive 20 on the wiring electrodes 18 on the circuit board 16, that is, the Al pad sections 12 on the surface of the bare chip 10 and the wiring electrodes 18 on the surface of the circuit board 16 are electrically connected through the Ni plating bumps 14 and the conductive adhesive 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a conventional method of flip-chip mounting a semiconductor chip on a circuit board, for example, an ACF (Anis
anisotropic conductive film) or ESC
(Epoxyencapsulated Solder Connection). In addition, for example, C4 (Co
ntrolled Collapsed Chip Connection) process and SB
A B (Stud-Bump Bonding) process and the like have been proposed.

In a conventional pressure welding method using ACF, ESC, or the like, a bare chip, which is a semiconductor chip that has not been subjected to mounting of general electronic components, mounting of odd-shaped electronic components, resin molding, etc., after a circuit board has been loaded. Flip chip mounting is performed in a predetermined order.

In the conventional C4 process, a solder bump is formed on a pad portion on the surface of a bare chip, a flux or the like is transferred to the solder bump, and the pad portion on the face of the bare chip which is face-down is connected to the circuit board via the solder bump. It is bonded to the surface wiring electrodes, connected and mounted by the batch reflow method. Subsequently, after performing flux cleaning, a sealing resin is injected between the circuit board and the bare chip, and the injected sealing resin is cured. Thus, the bare chip is flip-chip mounted on the circuit board via the solder bump.

[0005] In such a C4 process, until the sealing resin is cured, if a characteristic defect of the bare chip or a defect at the time of mounting is found by an electrical inspection after the mounting of the bare chip on the circuit board, In addition, it is possible to perform repair or rework by removing the mounted bare chip.

[0006] In the conventional SBB process,
Using a wire bonding technique, a stud bump having a two-step projection is formed on the pad portion of the bare chip surface, and a conductive adhesive is transferred onto the stud bump. The upper stud bump is connected to a wiring electrode on the surface of the circuit board via a conductive adhesive and mounted. Subsequently, a sealing resin is injected between the circuit board and the bare chip, and the injected sealing resin is cured. Thus, the bare chip is flip-chip mounted on the circuit board via the stud bump to which the conductive adhesive has been transferred.

[0007] Even in such an SBB process, until the sealing resin is cured, the electrical inspection after the mounting of the bare chip on the circuit board reveals that the characteristic defect of the bare chip and the defect at the time of mounting are found. Then, it is possible to remove the mounted bare chip and perform repair or rework.

[0008]

However, the conventional A
In the pressure welding method using CF, ESC, etc., SMT (Surface Mount Tech.
nology) Not only is the mounting of the component and the flip chip mounting of the bare chip twice troublesome, but also the following problems occur.

That is, when mounting SMT components such as general electronic components and odd-shaped electronic components before flip-chip mounting of bare chips, the bare chips on the circuit board 30 as shown in FIG. To protect the mounting area 32 from dirt, flux, oxidation, etc., FIG.
As shown in (b), it is necessary to protect the heat-resistant masking tape 34 by, for example, coating it.

For this reason, the bare chip mounting area 32
A step of applying a heat-resistant masking tape 34 covering the
A step of removing the pasted masking tape 34 or the like is required. In some cases, a cleaning step is further required after the masking tape 34 is removed, resulting in a problem that a work loss occurs. In addition, there is a problem that the peeled masking tape 34 is discarded, which is not preferable from an environmental point of view.

On the other hand, when flip chip mounting of bare chips is performed prior to mounting of SMT components such as general electronic components and odd-shaped electronic components, a special squeegee is required for solder printing for mounting SMT components. Use a projection or COB (Chip On Boaed) screen mask with a space to protect the bare chip already mounted on the circuit board, and take measures to protect the mounting part of the bare chip mounted earlier. Must.

For example, as shown in FIG. 13, when performing solder printing for mounting SMT components using a projected COB screen mask 38 to protect a bare chip 36 previously mounted on a circuit board 30. , Protrusion COB
An area of about 1 mm in width around the projection of the screen mask 38 is provided with an opening 40 in the projection COB screen mask 38.
, That is, a dead space area 42 where solder printing cannot be performed.

For this reason, the SM is provided in the vicinity of the bare chip 36 by the amount of the unprintable dead space area 42.
There is a problem that it becomes difficult to mount the T component, and the merit of high-density mounting by flip-chip mounting of a bare chip with a bent angle is reduced.

Further, in the pressure welding method such as ACF or ESC, once an electronic component is mounted on a circuit board, it is extremely difficult to remove and repair or rework the mounted bare chip. , KGD
In the situation where the establishment of (Known Good Die: quality guaranteed bare chip) is delayed, generally, a pair chip is mounted first, and an NG (No Good) product is rejected or discarded from an early stage. The method is adopted. For this reason, there has been a problem that the cost is increased.

Further, even when using KGD,
At the production site level, process defects are unavoidably generated to some extent, and there has been a high need from the production site side for a construction method that enables repair and rework after mounting electronic components. As a flip-chip mounting method capable of repair and rework, a C4 process, an SBB process, and the like have been proposed.

However, in the conventional C4 process, when a bare chip is flip-chip mounted on a circuit board via solder bumps, solder bumps are formed on pads on the surface of the bare chip, and flux or the like is transferred onto the solder bumps. However, since the batch reflow method is used, there is a limit to the fine pitch of the pad portion due to the restriction of the bump pitch when forming the solder bump. Conversely, if the pitch of the pad is reduced to less than 100 μm while the fine pitch of the semiconductor process is advanced, it is difficult to apply the C4 process to an actual manufacturing process. Become.

In addition, since a washing step is usually required, the cost is increased, and it is not preferable in terms of environment. The material of the solder bump is mainly Pb (lead) / S
Since n (tin) based solder is used, development of a Pb-free bump is required from the viewpoint of environmental protection in the future. In addition, when Pb-free, Pb-free
When using a re-solder, for example, the curing temperature can be reduced to the conventional 21.
In many cases, the composition rises from 0 ° C. to 250 ° C. At present, it is difficult to realize a C4 process that solves all of these problems.

In the above-mentioned conventional SBB process, when a stud bump is formed on a pad portion on a bare chip surface by using a wire bonding technique, stress is generated in the pad portion by ultrasonic waves, weighting, heat, or the like. .
For this reason, aside from the bare chip in which the pad portion is formed only in the peripheral portion, in the case of the bare chip of the area wiring in which the pad portion is formed not only in the peripheral portion but also in the inside, the chip is formed immediately below the pad portion. There is a risk of damaging elements such as transistors and wiring, and destroying circuits in the chip.

Therefore, for a bare chip of an area wiring, which becomes more and more important as the semiconductor device becomes higher in integration and higher in density and the semiconductor process becomes finer in the future, such a pad portion just below such a pad portion is required. However, it is difficult to use an SBB process that may damage elements such as transistors and wirings formed on the chip and damage circuits in the chip.

Further, the conductive adhesive is transferred onto the stud bump formed on the pad portion. However, the quality of the normal conductive adhesive is remarkably deteriorated after being exposed to the air.
Cost is high. For this reason, a small amount of the conductive adhesive is taken out of the container and transferred onto only the stud bumps, but quality control of the conductive adhesive at that time is very difficult. Further, in this method, after transferring the conductive adhesive on the stud bumps, the remaining conductive adhesive is discarded, which is not preferable in terms of cost.

The present invention has been made in view of the above-mentioned problems, and a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board, and a method of manufacturing the same,
It is an object of the present invention to provide a semiconductor device capable of repairing and reworking, and capable of flip-chip mounting even a bare chip having a fine pitch area wiring, and a method of manufacturing the same.

[0022]

The above object is achieved by a semiconductor device and a method of manufacturing the same according to the present invention described below. That is, the semiconductor device according to claim 1 is a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board, and a plating bump formed on a pad portion of the semiconductor chip and printed on an electrode portion of the circuit board. The conductive adhesive is connected to the conductive adhesive.

As described above, in the semiconductor device according to the first aspect, since the bump formed on the pad portion of the semiconductor chip is a plated bump, the stud bump is formed on the pad portion of the conventional semiconductor chip. When the bumps are formed, the pad
Since no stress is generated due to load, heat, etc., even if the semiconductor chip is a bare chip of area wiring, elements such as transistors and wiring formed directly under the pad part are damaged and the circuit in the chip is broken Therefore, a highly reliable semiconductor device is realized.

Further, since a conductive adhesive printed on the electrode portion of the circuit board is used as a medium for connecting the plated bump on the pad portion of the semiconductor chip and the electrode portion of the circuit board, In comparison with the case where the pad portion of the semiconductor chip is connected to the electrode portion of the circuit board using the solder bump, the restriction on the bump pitch when forming the solder bump is released, and the fine pitch of the pad portion is advanced. Therefore, a semiconductor device in which a high-density and highly integrated semiconductor chip is flip-chip mounted on a circuit board, that is, a high-density and highly integrated semiconductor device is realized.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the plated bump is
The semiconductor device is characterized in that the semiconductor chip is formed by dividing into a plurality of parts on the same pad part.

In the semiconductor device according to the second aspect of the present invention, since the plating bump is divided into a plurality of parts on the same pad portion, the plurality of divided plating bumps on the same pad portion are connected to the circuit board. Of the semiconductor chip and the circuit board due to the difference in the linear expansion coefficient between the semiconductor chip and the circuit board. Occurs, the effect of thermal stress is reduced as compared with the case where only one plating bump is formed on the same pad portion. That is, the stress generated in the connection part due to the thermal stress is dispersed and reduced. Therefore, in addition to the effect of the first aspect, a highly reliable semiconductor device is realized.

The contact area between the plated bump on the same pad portion of the semiconductor chip and the electrode portion of the circuit board via the conductive adhesive is smaller when the plated bump is divided into a plurality of plated bumps. It is smaller than the case where one large plated bump is formed, and there is a concern that the die share may be reduced. However, the resin is injected between the semiconductor chip and the circuit board, and the resin is sealed. A sufficient connection strength between the plurality of divided plated bumps on the same pad portion of the chip and the electrode portion of the circuit board via the conductive adhesive is ensured.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board, wherein a bump is formed on a pad portion of the semiconductor chip. And a step of printing a conductive adhesive on the electrode portion of the circuit board, placing the semiconductor chip on the circuit board, and forming a bump on a pad portion of the semiconductor chip and a conductive material on the electrode portion of the circuit board. And a step of connecting to an adhesive.

As described above, in the method of manufacturing a semiconductor device according to the third aspect, a conductive adhesive is printed on the electrode portion of the circuit board, and the conductive adhesive and the bump formed on the pad portion of the semiconductor chip are printed. Compared to the case of connecting using a solder bump formed on the pad portion of the conventional semiconductor chip, fine pitch printing is possible because conductive adhesives generally have smaller particles than solder. In order to reduce the bump pitch when forming solder bumps and to promote the fine processing of the semiconductor process that enables the finer pitch of the pad portion, a high-density, highly integrated semiconductor chip is mounted on a circuit board. The semiconductor device can be flip-chip mounted thereon, and high density and high integration of the semiconductor device can be realized.

In connecting the bump on the pad portion of the semiconductor chip and the conductive adhesive on the electrode portion of the circuit board,
Since the bumps are hardly weighted, the damage to the pads is extremely small. Even if the semiconductor chip is a bare chip of area wiring, it damages elements such as transistors and wiring formed directly under the pads. Flip a bare chip for area wiring, which becomes increasingly important as flip-chip mounting of semiconductor chips on circuit boards, especially as semiconductor processes become finer in the future, since there is no risk of damaging the circuit inside the chip. The reliability at the time of chip mounting is improved.

Also, there are various problems when using solder bumps, such as an increase in cost due to the necessity of a cleaning step, the occurrence of environmental pollution due to the use of Pb, and an increase in the curing temperature when using Pb-less solder. Problems such as increased damage to semiconductor chips due to prolonged curing time and difficulty in responding to fine processes are eliminated, reducing costs, preventing environmental pollution, and reducing the heat-resistant temperature of semiconductor chips. Reduction and improvement in reliability of the semiconductor device are realized.

When a conductive adhesive is printed on an electrode portion of a circuit board, a small circuit or MCM (Mu) is printed on the same circuit board.
Since it is possible to print simultaneously a conductive adhesive necessary for mounting general electronic components such as an lti chip module), realization of high-density mounting and high productivity can be easily realized. Further, in-line with the current SMT line is also possible.

Further, compared with the conventional method of transferring the conductive adhesive on the stud bump formed on the pad portion on the surface of the semiconductor chip, there is no waste such as discarding the conductive adhesive remaining after the transfer. Is eliminated, so that the cost can be reduced.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, when forming a bump on the pad portion of the semiconductor chip, the method comprises the steps of: In addition, a plating bump is formed using a plating method.

In the method for manufacturing a semiconductor device according to the fourth aspect of the present invention, the stud bump is formed on the pad portion of the conventional semiconductor chip by forming the plated bump on the pad portion of the semiconductor chip by using the plating method. Compared to the case of forming a bump, since stress due to ultrasonic waves, weight, heat, etc. does not occur in the pad part during bump formation,
Even if the semiconductor chip is a bare chip with area wiring, there is no danger of damaging elements such as transistors and wiring formed immediately below the pad portion and destroying circuits in the chip. In addition, the reliability when flip-chip mounting a semiconductor chip on a circuit board, particularly when flip-chip mounting a bare chip of area wiring, which becomes more and more important as the semiconductor process becomes finer in the future, is improved.

In addition, since plating bumps are formed at once on all the pad portions of the semiconductor chip by the plating method,
Higher productivity can be obtained as compared with the conventional case where stud bumps are sequentially formed on pad portions of a semiconductor chip.
For this reason, aside from the current situation, in the near future, it is expected that using a plating method, which is expected to rapidly develop infrastructure development, will be more cost-effective than the stud bump method.

The plating at this time was performed using Ni
Representative examples include (nickel) plating, Au (gold) plating, and Ni-Au plating, but are not limited thereto, and may be electrolytic plating or electroless capable of forming a metal bump on a pad portion of a semiconductor chip. Any plating may be used.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, when forming a bump on the pad portion of the semiconductor chip, the same pad of the semiconductor chip is formed. The bump is divided into a plurality of portions and formed on the portion.

As described above, in the method of manufacturing a semiconductor device according to the fifth aspect, the bump is divided into a plurality of portions on the same pad portion of the semiconductor chip, thereby dividing the bump into a plurality of portions on the same pad portion. Since the plated bump and the electrode portion of the circuit board are connected via a conductive adhesive, the difference between the linear expansion coefficient of the semiconductor chip and the circuit board causes the difference between the plated bump and the electrode portion of the circuit board. Even if stress due to thermal stress occurs in the connection portion, the effect of thermal stress is reduced as compared with the case where only one plated bump is formed on the same pad portion. That is, the stress generated in the connection part due to the thermal stress is dispersed and reduced. Therefore, in addition to the effect of the third aspect, high reliability and high manufacturing yield of the semiconductor device are realized.

The contact area between the plated bump on the same pad portion of the semiconductor chip and the electrode portion of the circuit board via the conductive adhesive is one large when divided into a plurality of plated bumps. Although it is smaller than the case of forming the plated bump, there is a concern that the die share will decrease, but by injecting resin between the semiconductor chip and the circuit board and performing resin sealing, it is possible to A sufficient connection strength between the plurality of divided plated bumps and the electrode portions of the circuit board via the conductive adhesive is ensured.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the conductive adhesive is printed on the electrode portion of the circuit board when the conductive adhesive is printed. It is characterized by controlling the temperature and humidity of the agent.

As described above, in the method of manufacturing a semiconductor device according to the sixth aspect, by controlling the temperature and humidity of the conductive adhesive when printing on the electrode portion of the circuit board, the conventional pad of the semiconductor chip is controlled. Compared to the case where the conductive adhesive is transferred onto the stud bump formed on the part, it is difficult to transfer a small amount of conductive adhesive to transfer the conductive adhesive to control the quality of the conductive adhesive, which is remarkably degraded in quality. The optimum temperature and humidity according to the conductive adhesive to be used are maintained, and quality control of the conductive adhesive can be easily performed without performing laborious work. Therefore, in addition to the effect of the third aspect, high reliability and high production yield of the semiconductor device are realized.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the third aspect, the conductive adhesive is printed on the electrode portion of the circuit board. The contact area of the agent with the electrode part is made smaller than the area of the electrode part, and the area of the upper surface of the conductive adhesive is made smaller than the contact area with the electrode part.

Thus, in the method of manufacturing a semiconductor device according to the seventh aspect, when the conductive adhesive is printed on the electrode portion of the circuit board, the contact area of the conductive adhesive with the electrode portion is reduced. By making the area of the upper surface of the conductive adhesive smaller than the contact area with the electrode part,
When connecting the bump on the pad portion of the semiconductor chip and the conductive adhesive on the electrode portion of the circuit board, the tip of the bump is inserted into the upper surface of the conductive adhesive, and the conductive adhesive is moved in the horizontal direction. Even if it is spread, the conductive adhesive does not protrude from the electrode portion or the conductive adhesive on the upper surface side does not drip, thereby preventing the occurrence of connection failure. Therefore, in addition to the effect of the third aspect, high reliability and high production yield of the semiconductor device are realized.

[0045]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described. FIG. 1A is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, that is, a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board, and FIG. It is the elements on larger scale which expanded the plating bump part of the semiconductor device shown to a), and FIG.1 (c) is the schematic plan view which looked at FIG.1 (b) from the bottom. FIG. 1D is a schematic cross-sectional view showing a plated bump portion of a semiconductor device according to a modification of the embodiment.
FIG. 1B shows a case where the plating bump shown in FIG. 1B is divided into two, and FIG. 1E is a schematic plan view of FIG. 1D viewed from below.

As shown in FIG. 1A, in a semiconductor device according to the present embodiment, a bare chip 10 is flip-chip mounted on a circuit board 16. Specifically, Ni plating bumps 14 having a height of about 40 to 50 μm are formed on Al (aluminum) pad portions 12 on the surface of the bare chip 10. An Ag (silver) -based or AgPa (protoactinium) -based conductive adhesive 20 is printed on the wiring electrodes 18 on the surface of the circuit board 16.

The bare chip 10 is placed face down on the circuit board 16, and the tip of the Ni plating bump 14 of the bare chip 10 is placed on the conductive adhesive 20 on the wiring electrode 18 on the surface of the circuit board 16. Inserted into
It is electrically connected. That is, the Al pad 12 on the surface of the bare chip 10 and the wiring electrode 18 on the surface of the circuit board 16 are electrically connected via the Ni plating bump 14 and the conductive adhesive 20. In addition, a sealing resin 28 is injected and hardened between the bare chip 10 and the circuit board 16.

Here, as shown in FIGS. 1B and 1C, one Ni plating bump 14 is formed on the entire surface of one Al pad 12. Instead of such a Ni-plated bump 14, FIG.
As shown in (d) and (e), a plurality of, for example, two divided Ni plating bumps 14a and 14b may be formed on one Al pad portion 12.

Next, a method of manufacturing the semiconductor device shown in FIG.
That is, a mounting method for flip-chip mounting a semiconductor chip on a circuit board will be described with reference to FIGS.

FIG. 2 is a flowchart for explaining a method of manufacturing the semiconductor device shown in FIG. 1, that is, a method of flip-chip mounting a semiconductor chip on a circuit board.
FIGS. 3, 4A, 5, 6, 7, 7A, 8, 9A, and 10A each show a method of manufacturing the semiconductor device shown in FIG. FIG. 4 is a process cross-sectional view for describing a mounting method of flip-chip mounting a semiconductor chip on a circuit board. FIG. 4B is a partially enlarged view of the plated bump portion of the semiconductor device shown in FIG.
FIG. 4C is a schematic plan view of FIG.
9B is a partially enlarged view of the conductive adhesive of the semiconductor device shown in FIG. 7A, and FIG. 9B is a view showing the connection between the plated bumps and the conductive adhesive of the semiconductor device shown in FIG. FIG. 10B is a schematic plan view showing a state of resin sealing of the semiconductor device shown in FIG.
FIG. 11 shows a connection portion between a case where two Ni-plated bumps are formed on one Al pad portion and a case where one Ni-plated bump is formed on one Al pad portion. FIG. 4 is a schematic cross-sectional view for comparing and explaining generated stress. FIG. 4D is a view for explaining a semiconductor device mounting method according to a modification of the present embodiment, and the plating bump portion shown in FIG. 4B is formed by dividing it into two. FIG. 4E is a schematic cross-sectional view showing the case.
It is the schematic plan view which looked at (d) from the top. FIG.
10C is a diagram for explaining the method of mounting the semiconductor device according to the modification of the present embodiment, and is a schematic plan view illustrating a state of resin sealing of the semiconductor device different from the case illustrated in FIG. FIG.

(1) Step S1: First, as shown in FIG. 3, an Al pad portion 12 is formed on the surface of the bare chip 10. Subsequently, as shown in FIGS. 4A, 4B and 4C, the Al pad portion 12 on the surface of the bare chip 10 is formed.
The Ni-plated bump 14 is formed thereon. In particular,
First, after the clean surface of the Al pad portion 12 is exposed on the surface of the bare chip 10, Zn (zinc) substitution is performed and Ni plating is performed using, for example, an electroless plating method. Thus, by replacing Zn and Ni on the Al pad portion 12, Ni
As plating proceeds, Ni-plated bumps 14 are formed.

At this time, the height of the Ni-plated bump 14 is usually set to about 40 to 50 μm. Regarding the shape, by providing a predetermined resist pattern, as shown in FIGS. 4B and 4C, one Ni plating bump 14 is formed on the entire surface of one Al pad portion 12. Form.

Here, instead of the Ni-plated bumps 14 shown in FIGS. 4B and 4C, a resist pattern different from the above-mentioned predetermined resist pattern is provided, so that FIGS. As shown in e), a plurality of divided Ni plating bumps 14a and 14b may be formed on one Al pad portion 12, for example.

(2) Step S2: Next, as shown in FIG. 5, a wiring electrode 18 is formed on the surface of the circuit board 16. Subsequently, a conductive adhesive 20 is printed on the wiring electrodes 18 on the surface of the circuit board 16. Specifically, as shown in FIG. 6, the wiring electrodes 18 are formed by, for example, a squeegee method.
Through a screen mask 22 provided with an opening at a position corresponding to the above, for example, a paste-like Ag-based or AgPa-based conductive adhesive 20a placed on the screen mask 22 is extruded into the opening using a squeegee 24. , Wiring electrode 1
The conductive adhesive 20 is printed on 8. Thus, FIG.
As shown in (a), a conductive adhesive 20 is formed on the wiring electrodes 18 on the surface of the circuit board 16.

At this time, as shown in FIG.
The contact area of the conductive adhesive 20 with the wiring electrode 18 is made smaller than the area of the wiring electrode 18. Further, the conductive adhesive 20 has a truncated pyramid shape, and the area of the upper surface thereof is smaller than the contact area with the wiring electrode 18. However, the shape of the conductive adhesive 20 is not limited to a truncated pyramid,
For example, it may be a squirrel shape or a truncated cone. Thus,
The conductive adhesive 20 does not protrude from the upper surface of the wiring electrode 18 and the area of the horizontal cross section above the conductive adhesive 20 is smaller than the area of the bottom surface.

Further, for example, an air conditioner is installed in a processing chamber where the conductive adhesive 20 is printed, or a temperature and humidity adjusting mechanism is attached to the printing equipment, so that the conductive adhesive 20 can be used for printing. , 20a. Specifically, the conditions vary depending on the type of the conductive adhesives 20 and 20a to be used. For example, in the case of a low boiling point system, the temperature of the conductive adhesives 20 and 20a is lowered and the conductive adhesive 20 , 20a in a range where moisture does not enter. In this way, quality control of the conductive adhesives 20 and 20a is minimized, and management is performed to maintain the quality. Further, at this time, it is desirable to protect the conductive adhesives 20 and 20a during printing from contamination due to suspended fine particles by making the processing room for printing the conductive adhesives 20 a clean room or the like.

When printing such an Ag-based or AgPa-based conductive adhesive 20, the conductive adhesive 20
Are usually smaller than the solder particles, so that fine pitch printing is possible. In the prototype of the inventor,
It was confirmed that fine printing at a pitch of 20 to 40 μm was possible.

(3) Step S3: Next, the wiring electrode 1
An image inspection of the circuit board 16 on which the conductive adhesive 20 is printed on 8 is performed. Thus, the wiring electrodes 18 on the surface of the circuit board 16
A print test is performed to determine whether the conductive adhesive 20 has been properly printed on the top. If printing of the conductive adhesive 20 is proper, the process proceeds to the next step.
The conductive adhesive 20 is wiped off, and although not shown in FIG. 2, the process returns to step S2 and printing is performed again.

(4) Step S4: Next, the circuit board 1
A general electronic component (not shown) is mounted on the wiring electrodes 18 on the surface 6 via the conductive adhesive 20, and then a modified electronic component (not shown) is mounted, and then the bare chip 10 is mounted.

That is, as shown in FIG. 8, the bare chip 10 is transported above the circuit board 16 in a face-down state using the mounting machine nozzle 26, and the bare chip 10 is further lowered. Then, as shown in FIG. 9A, the Ni-plated bumps 14 on the Al pad portions 12 on the surface of the bare chip 10 are brought into contact with the conductive adhesive 20 on the wiring electrodes 18 on the surface of the circuit board 16, and the Ni plating The bump 14 is inserted on the upper surface of the conductive adhesive 20. Thus, the circuit board 1
The bare chip 10 is flip-chip mounted on the wiring electrodes 18 on the six surfaces via the conductive adhesive 20.

At this time, the conductive adhesive 20 before mounting the flip chip on the bare chip 10 does not protrude from the upper surface of the wiring electrode 18 as shown in FIG. Since the area of the conductive adhesive 20 is smaller than the area of the bottom, Ni
When the plated bump 14 is inserted, as shown in FIG. 8B, the upper surface of the conductive adhesive 20 is pushed out in the horizontal direction, but the conductive adhesive 20 protrudes from the upper surface of the wiring electrode 18 or the conductive adhesive 20 The upper surface 20 does not sag. Therefore, even if the adjacent wiring electrodes 18 are formed at a fine pitch, a connection failure such as contact between the conductive adhesives 20 on these wiring electrodes 18 does not occur.

When the bare chip 10 is mounted, the Ni-plated bump 14 on the Al pad 12 on the surface of the bare chip 10 is merely inserted into the upper surface of the paste-like conductive adhesive 20. Is almost only weighted, and damage to the Al pad portion 12 is extremely small. Therefore, even when the bare chip 10 is an area wiring, there is no risk of damaging elements such as a transistor and a wiring formed directly below the Al pad portion 12 to destroy a circuit in the chip.

(5) Step S5: Next, the circuit board 1
An SMT component (not shown), such as a general electronic component or an odd-shaped electronic component, and a conductive adhesive 20 having the bare chip 10 mounted thereon are cured on the wiring electrodes 18 on the surface 6. In this way, batch reflow of SMT components (not shown) such as general electronic components and odd-shaped electronic components and the bare chip 10 becomes possible.

The curing conditions of the conductive adhesive 20 at this time are, for example, a curing temperature of 150 ° C. and a curing time of 30 minutes. When a conventional Pb / Sn-based solder is used, a curing temperature of 210 ° C. and a Pb-less solder are used. The temperature is considerably lower than the curing temperature of 250 ° C. when used.

(6) Step S6: Next, the circuit board 1
SMT components (not shown) such as general electronic components and odd-shaped electronic components via the conductive adhesive 20 on the wiring electrodes 18 on the surface 6
Then, an electrical inspection of the semiconductor device to which the bare chip 10 is connected is performed.

(7) Step S7: If the result of the electrical inspection in step S6 is good, the process proceeds to the next step. If the result of the inspection is not good, reheating and / or partial heating is performed. By washing, the Ni of the bare chip 10 is removed from the conductive adhesive 20 on the wiring electrodes 18 on the surface of the circuit board 16.
The plating bumps 14 are separated, and the process returns to step S4 to mount the bare chip 10 again. At this time, in some cases, mounting of SMT components such as general electronic components and odd-shaped electronic components may be performed again, and the process returns to step S2 to apply the conductive adhesive 20 onto the wiring electrodes 18 on the surface of the circuit board 16. Sometimes printing starts over.

(8) Step S8: If the result of the electric test in the above step S6 is good, FIG.
As shown in (2), after the sealing resin 28 is injected between the bare chip 10 and the circuit board 16, the sealing resin 28 is cured. At this time, as shown in FIG.
Ideally, the sealing resin 28 is the bare chip 10 and the circuit board 1.
It is desirable to be injected evenly between them.

However, depending on the degree of reliability required for the semiconductor device, the sealing resin 28 is not necessarily
It is not necessary to uniformly inject the resin between the bare chip 10 and the circuit board 16 in a grid pattern as shown in FIG. 10C, for example. For example, it is possible on a case-by-case basis to select an application pattern of the sealing resin within a range that satisfies the reliability required for the semiconductor device and to speed up the tact time.

It should be noted here that the sealing resin 2 is disposed between the bare chip 10 and the circuit board 16.
Even if 8 is implanted evenly, the reliability of the semiconductor device is rather reduced if a large number of voids are generated during the implantation or subsequent heating. For this reason, in this step, it can be said that it is better to provide an escape path for the void than to confine the void in the sealing resin 28 in a cured state.

As described above, according to the present embodiment, the Ni plating bumps 14 are formed on the Al pad portions 12 on the surface of the bare chip 10 by using, for example, the electroless plating method. Compared to the case where a stud bump is formed thereon, since stress due to ultrasonic waves, weighting, heat, etc. does not occur in the Al pad portion 12 when the Ni plating bump 14 is formed, even if the bare chip 10 is an area wiring, Since there is no danger of damaging elements such as transistors and wirings formed immediately below the Al pad portion 12 and destroying circuits in the chip, the bare chip 1
0 when flip-chip mounting the circuit chip 16 on the circuit board 16, especially when flip-chip mounting the bare chip 10 of the area wiring, which becomes more and more important as the semiconductor process becomes finer. Thus, a highly reliable semiconductor device can be realized.

Further, since the Ni-plated bumps 14 are formed on all the Al pad portions 12 on the surface of the bare chip 10 at one time, higher production can be achieved as compared with the case where the stud bumps are sequentially formed on the pad portions of the conventional chip. Sex can be obtained. For this reason, aside from the current situation, in the near future, it is expected that using a plating method, which is expected to rapidly develop infrastructure development, will be more cost-effective than the stud bump method.

Further, an Ag-based or AgPa-based conductive adhesive 20 is printed on the wiring electrodes 18 on the surface of the circuit board 16 by using, for example, a squeegee method, and the conductive adhesive 20 and the Al pad portion 12 on the surface of the bare chip 10 are printed. Ni plating bump on top 1
4, the particles of the Ag-based or AgPa-based conductive adhesive 20 are smaller than those in the case of connecting to the electrode portion of the circuit board using the solder bump formed on the pad portion of the conventional chip. Fine pitch printing is possible because it is usually smaller than the solder particles. In the prototype of the inventor, it was confirmed that fine printing up to a pitch of 20 μm was possible. Therefore, the fineness of the semiconductor process which enables the Al pad portion 12 to be finely pitched by being released from the restriction of the bump pitch when forming the solder bump is promoted. The ten integrated circuits can be further integrated with high density and high integration, and a high-density and high integration semiconductor device can be realized.

When the bare chip 10 is mounted, the Ni plating bump 14 on the Al pad 12 on the surface of the bare chip 10 is simply inserted into the upper surface of the paste-like conductive adhesive 20. Since almost no load is applied, damage to the Al pad portion 12 is extremely small, and even if the bare chip 10 is an area wiring, it damages elements such as transistors and wiring formed immediately below the bare chip 10 and causes a circuit in the chip to be damaged. Bare chip 1 of area wiring, which is becoming increasingly important as semiconductor processes become finer in the future, since there is no danger of breaking
Improve the reliability when flip chip mounting 0
A highly reliable semiconductor device can be realized.

Also, there are various problems when using solder bumps, such as an increase in cost due to the necessity of a cleaning step, the occurrence of environmental pollution due to the use of Pb, and an increase in the curing temperature when using Pb-less solder. Increased heat damage to bare chips due to prolonged cure time,
Since problems such as difficulty in responding to the fine process can be solved, costs can be reduced, environmental pollution can be prevented, the heat-resistant temperature of the bare chip 10 can be reduced, and the bare chip 1 can be reduced.
0 can improve the reliability of the semiconductor device mounted flip-chip on the circuit board 16.

Further, when printing the conductive adhesive 20 on the wiring electrodes 18 on the surface of the circuit board 16, not only the bare chip 10 but also SMT parts such as general electronic parts and odd-shaped electronic parts are required. Since the conductive adhesive 20 can be printed simultaneously and collectively, high productivity can be easily realized. Further, in-line with the current SMT line is also possible.

Further, compared with the conventional case where the conductive adhesive is transferred onto the stud bump formed on the pad portion on the chip surface, there is no waste that the conductive adhesive remaining after the transfer is discarded. Since it is eliminated, cost can be reduced.

When printing the conductive adhesive 20, the temperature and the humidity of the conductive adhesive 20 are controlled so that the conductive adhesive is formed on the stud bumps formed on the pads of the conventional chip. Compared to the case of transfer, the conductive adhesive 20 can be used without performing a troublesome operation such as taking out and transferring a small amount of conductive adhesive for quality control of the conductive adhesive whose quality is remarkably deteriorated. Since it is possible to control the deterioration of the quality to a minimum and maintain the quality, it is possible to realize high reliability, high productivity and a high production yield.

When printing the conductive adhesive 20, FIG.
As shown in (b), the shape of the conductive adhesive 20 is, for example, a truncated pyramid, and the conductive adhesive 20 is
When the Ni plating bump 14 of the bare chip 10 is inserted into the upper surface of the conductive adhesive 20 by making the area of the horizontal section above the upper surface smaller than the area of the bottom surface without protruding from the upper surface, FIG. As shown in (b), the conductive adhesive 20 can be prevented from protruding from the upper surface of the wiring electrode 18 and the upper surface of the conductive adhesive 20 from sagging. These wiring electrodes 1
The occurrence of connection failure due to the contact between the conductive adhesives 20 on the upper surface 8 can be prevented. Therefore, high reliability and high production yield can be realized.

In the above embodiment, FIG.
As shown in FIGS. 4B and 4C and FIGS. 4B and 4C, one Ni-plated bump 14 is formed on the entire surface of one Al pad 12. 1 (d), (e) and FIG.
As shown in (d) and (e), a plurality of, for example, two divided Ni-plated bumps 14a and 14b may be formed on one Al pad portion 12 as described above. It is. Then, as shown in comparison with FIGS. 11A and 11B, when two divided Ni plated bumps 14a and 14b are formed on one Al pad portion 12, the bare chip 10 is formed. Even if a stress due to thermal stress is generated at the connection portion due to a difference in linear expansion coefficient between the semiconductor device and the circuit board 16, one N pad is formed on the entire surface on one Al pad portion 12.
Compared with the case where the i-plated bump 14 is formed, the influence of the thermal stress is reduced, and the stress generated in the connection portion due to the thermal stress is reduced.

That is, as shown in FIG.
One Ni-plated bump 14 on one Al pad portion 12
11A and the wiring electrode 18 on the surface of the circuit board 16 are connected to each other, the stress due to the thermal stress is concentrated on the connecting portion, whereas the same Al pad portion as shown in FIG. 12, two Ni-plated bumps 14a, 14b
When the wiring is connected to the wiring electrode 18 on the surface of the circuit board 16, the influence of the thermal stress is reduced, and the stress generated at the connecting portion by the thermal stress is dispersed. For this reason, the entire stress generated in the connection portion is reduced, and high reliability and high production yield can be realized. Note that FIG.
In (a) and (b), to simplify the description,
Ni-plated bump 14 or Ni-plated bump 14a, 1
Although the illustration of the conductive adhesive 20 interposed between the wiring electrode 4b and the wiring electrode 18 on the surface of the circuit board 16 is omitted, even if the conductive adhesive 20 is interposed, the essential situation is not solved. Is not different from the above case.

However, in this case, the same Al pad portion 12
The contact area between the upper two Ni-plated bumps 14a and 14b and the wiring electrode 18 on the surface of the circuit board 16 via the conductive adhesive 20 is one Ni pad on the entire Al pad portion 12. It is also conceivable that the contact area becomes smaller than that when the plated bumps 14 are formed, and the die shear decreases. In the prototype of the inventor, only about 20 to 30 g of die share per two Ni-plated bumps 14a and 14b were obtained.

However, by performing resin sealing with the sealing resin 28, the connection strength between the Ni-plated bumps 14a and 14b and the wiring electrode 18 via the conductive adhesive 20 is secured to a sufficient level. The overall reliability evaluation was higher when the Ni plated bumps 14a and 14b divided into two on one Al pad portion 12 were formed.

[0083]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, the following effects can be obtained. In other words, according to the semiconductor device of the first aspect, the bump formed on the pad portion of the semiconductor chip is a plated bump, so that the case where the stud bump is formed on the pad portion of the conventional semiconductor chip is different. In comparison, since no stress is generated in the pad portion during the bump formation by ultrasonic waves, weighting, heat, etc., even if the semiconductor chip is a bare chip of area wiring, the transistor formed immediately below the pad portion Since there is no possibility that the elements in the chip and the wiring are damaged and the circuit in the chip is destroyed, a highly reliable semiconductor device can be realized.

Further, since a conductive adhesive printed on the electrode portion of the circuit board is used as a medium for connecting the plating bump on the pad portion of the semiconductor chip to the electrode portion of the circuit board, In comparison with the case where the pad portion of the semiconductor chip is connected to the electrode portion of the circuit board using the solder bump, the restriction on the bump pitch when forming the solder bump is released, and the fine pitch of the pad portion is advanced. Therefore, a semiconductor device in which a high-density and highly integrated semiconductor chip is flip-chip mounted on a circuit board, that is, a high-density and highly integrated semiconductor device can be realized.

According to the second aspect of the present invention, the plated bumps are formed on the same pad portion of the semiconductor chip by dividing into a plurality of parts, so that the coefficient of linear expansion between the semiconductor chip and the circuit board is increased. Due to the difference in the thermal stress caused by the thermal stress at the connection between the plating bump and the electrode part of the circuit board, the effect of the thermal stress is smaller than when only one plating bump is formed on the same pad part. Since the stress is alleviated and the stress generated in the connection part due to the thermal stress is dispersed and reduced, a highly reliable semiconductor device can be realized in addition to the effect of the first aspect.

According to the method of manufacturing a semiconductor device of the third aspect, a conductive adhesive is printed on the electrode portion of the circuit board, and the conductive adhesive and the bump formed on the pad portion of the semiconductor chip are printed. In general, the conductive adhesive has finer particles than solder when compared to the case of connecting to the electrode of the circuit board using solder bumps formed on the pads of the conventional semiconductor chip. High-density, high-density integration is possible because pitch printing is possible and semiconductor processes that allow finer pitches in pads are released from the constraints of bump pitch when forming solder bumps. This makes it possible to flip-chip mount the integrated semiconductor chip on a circuit board, thereby realizing high density and high integration of the semiconductor device.

When connecting the bump on the pad portion of the semiconductor chip and the conductive adhesive on the electrode portion of the circuit board,
Since the bumps are hardly weighted, the damage to the pad portion is extremely small, and even if the semiconductor chip is a bare chip of area wiring, it damages elements such as transistors and wiring formed immediately below the pad portion. Since there is no danger of destruction of the circuit inside the chip, when flip-chip mounting a semiconductor chip on a circuit board, in particular, the area wiring bare chip, which becomes increasingly important with the refinement of semiconductor processes in the future, flip chip Reliability at the time of mounting can be improved.

Also, there are various problems when using solder bumps, such as an increase in cost due to the necessity of a cleaning step, the generation of environmental pollution due to the use of Pb, an increase in the curing temperature when using Pb-less solder, and a cure. Increased heat damage to semiconductor chips due to longer time,
It is possible to solve problems such as difficulty in responding to fine processes, thereby reducing costs, preventing environmental pollution, reducing the heat resistance temperature of semiconductor chips, and improving the reliability of semiconductor devices. Can be.

Further, when printing the conductive adhesive on the electrode portion of the circuit board, the conductive adhesive necessary for mounting the general electronic component on the same circuit board may be printed simultaneously and collectively. Therefore, high-density mounting and high productivity can be easily realized. In addition, the current SMT
It is also possible to inline with the line.

Further, according to the method of manufacturing a semiconductor device of the present invention, by forming a plating bump on a pad portion of a semiconductor chip by using a plating method, a stud bump is formed on a pad portion of a conventional semiconductor chip. In comparison with the case of forming a bump, since stress due to ultrasonic waves, weighting, heat, etc. does not occur in the pad portion at the time of bump formation, even if the semiconductor chip is a bare chip of area wiring, it is formed immediately below the pad portion. In addition to the effects of claim 3, there is no possibility of damaging elements such as transistors and wiring and damaging the circuits in the chip. Improve the reliability of flip-chip mounting of bare chips for area wiring, which is becoming increasingly important as the process becomes finer. Door can be.

Further, since plating bumps can be formed at once on all the pad portions of the semiconductor chip by the plating method, compared with the case where stud bumps are sequentially formed on the pad portions of the conventional semiconductor chip. , High productivity can be obtained. For this reason, at the moment,
In the near future, it is expected that using the plating method, which is expected to rapidly develop infrastructure development, will be more cost-effective than the stud bump method.

According to the method of manufacturing a semiconductor device according to the fifth aspect, the bump is divided into a plurality of portions on the same pad portion of the semiconductor chip, so that the linear expansion between the semiconductor chip and the circuit board is achieved. Even if stress due to thermal stress occurs at the connection between the plating bump and the electrode part of the circuit board due to the difference in coefficient, the effect of the thermal stress is greater than when only one plating bump is formed on the same pad part. Is mitigated, and the stress generated in the connection part due to the thermal stress is dispersed and reduced. Therefore, in addition to the effect of the third aspect, high reliability and high production yield of the semiconductor device can be realized.

According to the method of manufacturing a semiconductor device of the sixth aspect, by controlling the temperature and humidity of the conductive adhesive when printing on the electrode portion of the circuit board,
Compared to the case where the conductive adhesive is transferred onto the stud bump formed on the pad portion of the conventional semiconductor chip, a small amount of conductive adhesive is issued for quality control of the conductive adhesive, which is remarkably degraded in quality. Even without performing a laborious operation such as transfer, the optimal temperature and humidity according to the conductive adhesive to be used are maintained, and the quality control of the conductive adhesive is easily performed. In addition to the effects of 3, the semiconductor device can achieve high reliability and high manufacturing yield.

According to the method of manufacturing a semiconductor device of the present invention, when printing the conductive adhesive on the electrode portion of the circuit board, the contact area of the conductive adhesive with the electrode portion is reduced. The area of the upper surface of the conductive adhesive is smaller than the area of contact with the electrode part, so that the bump on the pad part of the semiconductor chip and the conductive adhesive on the electrode part of the circuit board can be reduced. When connecting, the tip of the bump is inserted into the upper surface of the conductive adhesive, and even if the conductive adhesive is pushed and spread in the horizontal direction, the conductive adhesive protrudes from the electrode part or the conductive Since the adhesive does not drip and the occurrence of connection failure is prevented, high reliability and high production yield of the semiconductor device can be realized in addition to the effect of the third aspect.

[Brief description of the drawings]

FIG. 1A is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention, that is, a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board, and FIG. It is the elements on larger scale which expanded the plating bump part of the semiconductor device shown, and (c) is the schematic plan view which looked at (b) from the bottom. (D) is a schematic sectional view showing a plated bump portion of a semiconductor device according to a modification of the present embodiment, and (b) is
(E) is a schematic plan view of (d) seen from below, in which the plating bump shown in FIG.

FIG. 2 is a flowchart for explaining a method of manufacturing the semiconductor device shown in FIG. 1, that is, a mounting method of flip-chip mounting a semiconductor chip on a circuit board.

FIG. 3 is a process cross-sectional view (part 1) for describing a method for manufacturing the semiconductor device shown in FIG. 1, that is, a mounting method for flip-chip mounting a semiconductor chip on a circuit board.

FIG. 4A is a process sectional view (2) for explaining a method of manufacturing the semiconductor device shown in FIG. 1, that is, a method of flip-chip mounting a semiconductor chip on a circuit board, and FIG. FIG. 2 is a partially enlarged view in which a plated bump portion of the semiconductor device shown in FIG. 2A is enlarged, and FIG. 2C is a schematic plan view of FIG. (D) is a figure for explaining the mounting method of the semiconductor device concerning the modification of this embodiment, and is a schematic sectional view showing the case where the plating bump part shown in (b) is divided into two and formed. (E) is a schematic plan view of (d) as viewed from above.

FIG. 5 is a process sectional view (part 3) for describing a method for manufacturing the semiconductor device shown in FIG. 1, that is, a mounting method for flip-chip mounting a semiconductor chip on a circuit board.

FIG. 6 is a process sectional view (part 4) for describing the method for manufacturing the semiconductor device shown in FIG. 1, that is, the mounting method for flip-chip mounting a semiconductor chip on a circuit board.

FIG. 7A is a process sectional view (5) for explaining a method of manufacturing the semiconductor device shown in FIG. 1, that is, a mounting method of flip-chip mounting a semiconductor chip on a circuit board; FIG. 3 is a partially enlarged view of the conductive adhesive of the semiconductor device shown in FIG.

FIG. 8 is a process sectional view (part 6) for describing the method for manufacturing the semiconductor device shown in FIG. 1, that is, the mounting method for flip-chip mounting a semiconductor chip on a circuit board.

9A is a process sectional view (No. 7) for explaining the method of manufacturing the semiconductor device shown in FIG. 1, that is, the mounting method of flip-chip mounting a semiconductor chip on a circuit board, and FIG. FIG. 3 is an enlarged partial view of a contact portion between a plated bump and a conductive adhesive of the semiconductor device shown in FIG.

10A is a diagram showing a method for manufacturing the semiconductor device shown in FIG. 1,
That is, FIGS. 8A and 8B are process cross-sectional views for explaining a mounting method of flip-chip mounting a semiconductor chip on a circuit board, and FIG. 8B is a schematic plan view showing a state of resin sealing of the semiconductor device shown in FIG. It is a figure for explaining the mounting method of the semiconductor device concerning the modification of this embodiment, and is a figure of (c) and shows the state of resin sealing of the semiconductor device different from the case shown in (b). It is a schematic plan view.

FIG. 11 shows N divided into two parts on one Al pad part.
FIG. 7 is a schematic cross-sectional view for comparing and explaining stresses generated in connection portions when an i-plated bump is formed and when one Ni-plated bump is formed on one Al pad portion.

FIG. 12 is a schematic plan view for explaining the use of a masking tape when mounting SMT components such as general electronic components and odd-shaped electronic components in the conventional flip chip mounting of bare chips.

FIG. 13 is a schematic cross-sectional view for explaining the use of a projected COB screen mask when mounting SMT components such as general electronic components and odd-shaped electronic components later in flip chip mounting of a conventional bare chip.

[Explanation of symbols]

10: bare chip, 12: Al pad part, 14, 1
4a, 14b: Ni-plated bump, 16: circuit board, 18: wiring electrode, 20, 20a: conductive adhesive,
22 ... Screen mask, 24 ... Squeegee, 26 ...
... Mounting machine nozzle, 28 ... Seal resin, 30 ... Circuit board 30, 32 ... Bare chip mounting area, 34 ... Masking tape, 36 ... Bear chip, 38 ... Protrusion C
OB screen mask, 40... Opening, 42... Dead space region.

Claims (7)

[Claims] 1. A semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board, wherein a plated bump formed on a pad portion of the semiconductor chip and a conductive printed on an electrode portion of the circuit board. A semiconductor device, wherein the semiconductor device is connected to an adhesive. 2. The semiconductor device according to claim 1, wherein said plating bump is formed by dividing a plurality of portions on the same pad portion of said semiconductor chip. 3. A method of manufacturing a semiconductor device in which a semiconductor chip is flip-chip mounted on a circuit board, comprising: forming a bump on a pad portion of the semiconductor chip; A step of printing a conductive adhesive, placing the semiconductor chip face down on the circuit board, and mounting the bump on a pad of the semiconductor chip and an electrode on an electrode of the circuit board. A method of manufacturing a semiconductor device, comprising: 4. The method of manufacturing a semiconductor device according to claim 3, wherein when forming the bump on the pad portion of the semiconductor chip, a plating bump is formed on the pad portion of the semiconductor chip using a plating method. A method for manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 3, wherein, when the bump is formed on a pad portion of the semiconductor chip, a plurality of bumps are formed on the same pad portion of the semiconductor chip. A method for manufacturing a semiconductor device, wherein the method is divided and formed. 6. The method for manufacturing a semiconductor device according to claim 3, wherein when printing the conductive adhesive on the electrode portion of the circuit board, controlling the temperature and humidity of the conductive adhesive. A method for manufacturing a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 3, wherein when the conductive adhesive is printed on the electrode portion of the circuit board, a contact area of the conductive adhesive with the electrode portion is reduced. A method of manufacturing a semiconductor device, wherein the area of the upper surface of the conductive adhesive is smaller than the area of contact with the electrode portion, the area being smaller than the area of the electrode portion.