JP2001326761A - Image processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing apparatus provided with the clock generation part of simple constitution capable of supplying the system clock of a frequency matched with an operation clock respectively used by a series of image processing circuit parts in the operation of each image processing circuit part. SOLUTION: A clock from an oscillator (1) 11 is selected by a selector 13, an input image is processed by an image processing circuit (1) 15 in accordance with the clock and then an image for a frame is retained in an image memory 16. Next, the selector 13 is switched and the clock signal of an oscillation frequency for an image processing circuit (2) 17, that is for output processing, is inputted from an oscillator (2) 12 to an analog PLL 14. After the inputting, whether the analog PLL 14 is locked or not is determined with a LOCK signal and in accordance with a clock capable of securing normal operation, data is read from the memory 16 to perform output processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus such as a color copying machine, a scanner, a printer, a facsimile (FAX), and more particularly, to an operation used in a series of image processing units constituting an image processing apparatus. The present invention relates to an image processing apparatus including a clock control unit that supplies a different system clock according to each conversion / processing operation of an image processing unit when clocks are different.

[0002]

2. Description of the Related Art In an image processing apparatus such as a color copying machine, image forming data used in an image forming apparatus is created based on an image signal input from an input device such as a document reading apparatus. Requires a processing circuit. In each image processing circuit, processing proceeds in accordance with the system clock, and a system using the same frequency (a basic clock generated from a single oscillator) as the system clock has been conventionally used (Japanese Patent No. 2809398,
See).

[0003]

However, according to the system using the same frequency (basic clock generated from a single oscillator) as the system clock, the operating clock used in a part of the series of image processing circuits is not used. If different, additional circuitry is required to accommodate this, and the circuit may be complicated. Heretofore, there has been no proposal to solve such a problem by making it possible to supply a different clock frequency to each circuit unit on the system clock generation side, and it has not been realized. The present invention has been made in view of the above-described state of the art in an image processing apparatus including a series of image processing circuit units operated by a system clock, and an object of the present invention is to use each image processing circuit unit. It is an object of the present invention to provide an image processing apparatus including a clock generation unit having a simple configuration, which can supply a system clock having a frequency corresponding to an operation clock when each image processing circuit unit operates.

[0004]

According to the present invention, there is provided an image processing apparatus comprising: an image processing unit for converting and processing an input image signal; and a clock generating unit for generating a system clock for operating the image processing unit. In the image processing apparatus, the clock generation unit includes a clock control unit that supplies a different clock to each of the image processing units.

According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the clock control means is means for switching a clock from an oscillation source for generating a different clock. .

According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect, an analog PLL is provided on an output side of the clock control means.

According to a fourth aspect of the present invention, in the image processing apparatus according to the third aspect, the analog PLL is a circuit element having a built-in ASIC constituting the image processing means.

According to a fifth aspect of the present invention, there is provided the image processing apparatus as set forth in the third or fourth aspect, wherein the L of the analog PLL is
An OCK signal is detected, and the image processing means is operated based on the detection result.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described based on the following embodiments shown in the accompanying drawings. The image processing apparatus of the present embodiment has an image processing unit including a series of image processing circuits,
The image processing unit includes an image input device (copier, scanner, FA
In the case of X transmission or the like, it is a document image reading device, and in the case of a printer, an interface or the like that accepts print data sent from the outside through communication means corresponds to this.)
An output device (an image forming (printing) device in the case of a copying machine, a facsimile reception, a printer, etc.)
In the case of a scanner or facsimile transmission, an interface or the like for transmitting image data to an external device through a communication unit corresponds to the conversion and processing according to the characteristics. Normally, the converted and processed signal is temporarily stored in a memory. The following conversion and processing are performed on the image signal stored in the memory, and then the image signal finally matching the characteristics is sent to the output device. In such a conversion / processing process, depending on the conditions of the image processing circuits on the input side and the output side, a system clock of a signal written to the memory and a system clock at the time of reading from the memory may be different.

In the clock generator of this embodiment, when a system clock for writing to a memory and a system clock for reading are different, the respective clock oscillators are used so that conversion and processing can be executed with a system clock suitable for each. A clock oscillator that generates a clock having a frequency suitable for the operation of each image processing circuit is selected in accordance with the write and read timings. In this case, no matter which clock oscillator is used, since the system clock is supplied to each image processing circuit through a common signal line, the clock oscillator to be used is switched by a selector. In addition, it is necessary to prevent noise from appearing on the clock signal line at the time of switching, and the occurrence of noise is prevented by inserting an analog PLL on the output side of the selector.

The present embodiment will be described more specifically with reference to FIG. 1 showing a main part of an image processing apparatus using the above-described clock generation unit. As shown in FIG. 1, the clock generator includes an oscillator (1) 1 for generating clocks of different frequencies.
1. Two oscillators comprising an oscillator (2) 12 and an oscillator (1)
11, a selector 13 for selecting which clock of the oscillator (2) 12 is used, and an analog PLL 14 to which the clock selected by the selector 13 is input. An image processing circuit (1) 15 is connected to an image processing circuit via an image memory 16.
(2) Connect to 17, image processing circuit (1) 15, image processing circuit
(2) A system clock is input to each of 17 via the analog PLL 14. In this embodiment, the oscillator (1) 1
1. Oscillator (2) 12 is an image processing circuit (1) 15
(For example, an input device) and an image processing circuit (2) 17 (for example, an output device). The selector 13 is 2
One clock signal is selected and connected to the input of the analog PLL 14.

The operation of the circuit shown in FIG. 1 will be described. An image input signal is processed by an image processing circuit (1) 15 and input to an image memory 16. At this time, a clock having an oscillation frequency for the image processing circuit (1) 15 is selected from the oscillator (1) 11 as a system clock by the selector 13, and the processing by the image processing circuit (1) 15 and the data after the processing are performed according to this clock. Is stored in the image memory 16.
When the image for the frame has been input to the image memory 16,
Switch the selector 13 and use the oscillator as the system clock
(2) The output processing clock signal of the oscillation frequency for the image processing circuit (2) 17 from 12 is input to the analog PLL 14. Data is read from the image memory 16 according to the clock from the analog PLL 14, and the image processing circuit
(2) The processing (output processing) operation by 17 is performed, and is output to the next image processing circuit or the outside. At this time, the process is started with an interval of the time when the analog PLL 14 locks. This makes it possible to completely prevent the influence of noise generated when the selector 13 is switched. When the output for one frame is completed and the image input mode is set again, the selector 13 is switched to control the processing clock from the oscillator (1) 11 to be input to the analog PLL 14. As described above, when an image is input to the image memory 16 and when an image is output from the image memory 16, the selector 13 is controlled so that a clock frequency suitable for each is selected.

Here, an embodiment provided with a means for ensuring the normal operation of the clock generation unit used in the image processing apparatus shown in FIG. 1 will be described. When the clock to be used is switched by the selector 13 in the clock generation unit, the analog PLL 14
It takes a certain time (LOCK time) for the frequency of the clock output from the LOCK to (become the same with) the input frequency (oscillator frequency). In order to secure the operation margin of the circuit, it is better to perform the processing after the analog PLL 14 is locked. For this reason, whether or not LOCK
Judgment is made by detecting the signal (LOCK signal) at the LOCK terminal of the LL 14, and normal processing of the image processing circuits 15, 17 is ensured by starting the processing. This operation will be described in more detail with reference to the circuit of FIG. 1. An image input signal is processed by an image processing circuit (1) 15 and input to an image memory 16. At this time, a clock having an oscillation frequency for the image processing circuit (1) 15 is selected from the oscillator (1) 11 by the selector 13 as a system clock, and the data processed and processed by the image processing circuit (1) 15 are selected according to this clock. Is stored in the image memory 16.

When the image for the frame has been input to the image memory 16, the selector 13 is switched, and the clock signal of the oscillation frequency for the output processing from the oscillator (2) 12 to the image processing circuit (2) 17 is output as the system clock. Analog PLL14
To enter. After the input, whether or not the analog PLL 14 is locked is determined by detecting a signal (LOCK signal) at the LOCK terminal, and after confirming the LOCK, the output process is started. This makes it possible to secure a normal circuit operation in a minimum time, that is, to completely prevent the circuit from being affected by noise generated when the selector 13 is switched.
The data is read from the image memory 16 in accordance with the clock from the analog PLL 14, processed by the image processing circuit (2) 17 (output processing), and output to the next image processing circuit or to the outside. When outputting one frame of image from the image memory 16 and returning to the image input mode again, the selector 13 is switched and the oscillator (1) 1 is used as the system clock.
1 to the image processing circuit (1) 15, that is, a clock signal having an oscillation frequency for input processing is input to the analog PLL 14. Also at this time, whether or not the analog PLL 14 is locked is determined by detecting a signal (LOCK signal) at the LOCK terminal, and after confirming the LOCK, the input processing is started.

Next, another embodiment which differs from the above embodiment in the clock generation unit will be described. In the above embodiment, the analog PL is provided on the clock generation unit side separately from the image processing circuits 15 and 17.
L14 is provided, but in this embodiment, the image processing circuit is
Consists of parts consisting only of ASIC, ASIC is analog PLL
Built-in. In this case, an analog PLL for controlling the clock is not required on the clock generation unit side. Also in this embodiment, if necessary, the analog P of each ASIC
The execution timing of the process can be controlled by observing the LL LOCK signal. FIG. 2 shows a main part of the image processing apparatus of the present embodiment. FIG. 3 shows an ASIC which is a component of the image processing circuit in the image processing apparatus of FIG.
As shown in FIG. 2, the clock generator includes two oscillators including an oscillator (1) 11 and an oscillator (2) 12 that generate clocks of different frequencies, and one of the oscillator (1) 11 and the oscillator (2) 12. And a selector 13 for selecting whether to use the clock. The image processing circuit (1) 18 and the image processing circuit (2) 19, which are constituted only by the ASIC 20, are connected via the image memory 16, and the image processing circuit (1) 18 and the image processing circuit (2) 1
9 is input with the system clock selected by the selector 13. As shown in FIG.
(1) 18 and the ASIC 20 constituting the image processing circuit (2) 19
Each has a built-in analog PLL 21, and inputs a system clock selected by the selector 13 through the analog PLL 21. Further, the oscillator (1) 11 and the oscillator (2) 12
Each of the image processing circuits (1) 18 (for example, an input device)
And an image processing circuit (2) 19 (for example, an output device).

The operation of the circuit shown in FIG. 2 will be described. An image input signal is processed by an image processing circuit (1) 18 and input to an image memory 16. At this time, a clock having an oscillation frequency for the image processing circuit (1) 18 is selected by the selector 13 from the oscillator (1) 11 as a system clock, and the data processed and processed by the image processing circuit (1) 18 are selected according to this clock. Is stored in the image memory 16. Image memory 1
When the image of the frame has been inputted to 6, the selector 13 is switched, and a clock signal of the oscillation frequency for output processing from the oscillator (2) 12 to the ASIC 20 is inputted to each ASIC 20 as a system clock. . After input, each ASIC 20
Whether the built-in analog PLL 21 is locked or not is determined by detecting a signal at the LOCK terminal (LOCK signal), and after confirming the LOCK, the ASIC 20 starts processing the image signal. This makes it possible to secure a normal circuit operation in a minimum time, that is, to completely prevent the circuit from being affected by noise generated when the selector 13 is switched. The data is read from the image memory 16 in accordance with the clock from the analog PLL 21 and the image processing circuit (2) 19
(Output processing), and outputs the result to the next image processing circuit or the outside. When outputting one frame of image from the image memory 16 and returning to the image input mode again,
Switch the selector 13 and use the oscillator as the system clock
From (1) 11, an image processing circuit (1) 18 is input to each ASIC 20 with a clock signal having an oscillation frequency for input processing. Also at this time, whether or not the analog PLL 14 is locked is determined by detecting a signal (LOCK signal) at the LOCK terminal, and after confirming the LOCK, the input processing is started.

[0017]

According to the present invention, the circuit operates at different clock frequencies by providing clock control means for supplying different clocks in accordance with the conversion and processing operations of the image processing means. It is possible to realize conversion and processing under optimum conditions and with a simple circuit configuration. (2) Advantages Corresponding to the Invention of Claim 2 In addition to the effect of (1), the clock control means is means for switching a clock from an oscillation source for generating a different clock. It can be easily implemented. (3) Effects corresponding to the third aspect of the invention In addition to the effects of the above (1) and (2), noise is generated on the clock signal line by providing the analog PLL on the output side of the clock control means. Can be prevented. (4) Effects corresponding to the fourth aspect of the invention In addition to the effect of the above (3), by configuring the image processing means by an ASIC having an analog PLL as a circuit element, the circuit is further simplified and the number of parts is reduced. Can be reduced. (5) Effects corresponding to the invention of claim 5 In addition to the effects of the above (3) and (4),
By detecting the LOCK signal and operating the image processing means according to the detection result, the smallest analog PLL
The normal circuit operation can be performed in the LOCK time.

[Brief description of the drawings]

FIG. 1 shows a main part of an embodiment of an image processing apparatus according to the present invention having a clock generation unit for supplying a different system clock according to each conversion / processing operation.

FIG. 2 shows a main part of another embodiment of the image processing apparatus according to the present invention having a clock generation unit for supplying a different system clock according to each conversion / processing operation.

FIG. 3 shows an ASIC which is a component of an image processing circuit in the image processing apparatus of FIG.

[Explanation of symbols]

11 ... oscillator (1), 12 ... oscillator (2), 1
3: Selector, 14: Analog PL
L, 15: Image processing circuit (1), 16: Image memory, 17: Image processing circuit (2), 18: Image processing circuit (1), 19: Image processing circuit (2), 20: ASI
C, 21 ... analog PLL.

Claims (5)

[Claims] 1. An image processing apparatus comprising: image processing means for converting and processing an input image signal; and clock generation means for generating a system clock for operating the image processing means. An image processing apparatus comprising clock control means for supplying different clocks according to each means. 2. An image processing apparatus according to claim 1, wherein said clock control means is means for switching a clock from an oscillation source for generating a different clock. 3. The image processing apparatus according to claim 1, further comprising an analog PLL on an output side of said clock control means. 4. The image processing apparatus according to claim 3, wherein said analog PLL is a circuit element with a built-in ASIC constituting said image processing means. 5. The image processing apparatus according to claim 3, wherein a LOCK signal of said analog PLL is detected, and said image processing means is operated based on a detection result. apparatus.