JP3935308B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus such as a color copying machine, a scanner, a printer, and a facsimile (FAX), and more specifically, when an operation clock used in a series of image processing units constituting the image processing apparatus is different. The present invention relates to an image processing apparatus including clock control means for supplying a different system clock in accordance with each conversion / processing operation of a processing unit.
[0002]
[Prior art]
In an image processing apparatus such as a color copying machine, image forming data to be used in an image forming apparatus is created based on an image signal input by an input device such as a document reading apparatus. For this purpose, a series of image processing circuits are required. Yes. In each image processing circuit, processing proceeds in accordance with the system clock, and a method of using the same frequency (basic clock generated from a single oscillator) as the system clock has been conventionally used (see Japanese Patent No. 2809398).
[0003]
[Problems to be solved by the invention]
However, according to the system using the same frequency (basic clock generated from a single oscillator) as the system clock, if the operation clock used in some processing circuits of a series of image processing circuits is different, it is added to cope with it. Circuit is required, and the circuit may be complicated.
Until now, there has been no proposal to solve such a problem by making it possible to supply different clock frequencies to each circuit unit on the system clock generation side, and it has not been realized yet.
The present invention has been made in view of the above-described state of the art in an image processing apparatus including a series of image processing circuit units that operate according to a system clock, and the object thereof is used in each image processing circuit unit. An object of the present invention is to provide an image processing apparatus including a clock generation unit having a simple configuration capable of supplying a system clock having a frequency matched to an operation clock during operation of each image processing circuit unit.
[0004]
[Means for Solving the Problems]
The invention according to claim 1, a plurality of image processing unit for processing the input image signal, each having an oscillation source, and a plurality of clock generator for generating a system clock for operating the image processing unit, wherein met image processing apparatus and a clock selection unit for selecting and outputting outputs of a plurality of clock generating unit, the plurality of image processing units is connected via an image memory, the output of the clock selection unit Input to the plurality of image processing units, and the clock selection unit selects a system clock for operating the image processing unit when a certain image processing unit processes an image signal and writes it to the image memory; when another image processing unit reads and processes the image signal written in the image memory and selects the system clock to operate the image processing unit of said another An image processing apparatus.
[0005]
A second aspect of the present invention, in the image processing apparatus of claim 1, is characterized in that an analog PLL on the output side of the clock selection section.
[0006]
According to a third aspect of the present invention, in the image processing apparatus according to the second aspect, the analog PLL is a circuit element with a built-in ASIC constituting the image processing unit .
[0007]
According to a fourth aspect of the present invention, in the image processing apparatus according to the second or third aspect, the LOCK signal of the analog PLL is detected, and the image processing unit is operated according to the detection result. Is.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described based on the following examples shown with the accompanying drawings.
The image processing apparatus of this embodiment has an image processing unit composed of a series of image processing circuits. The image processing unit is an image input device (in the case of a copying machine, a scanner, a FAX transmission, etc., an original image reading device, and a printer. In the case of an image forming (printing) apparatus in the case of a copying machine, FAX reception, printer, etc., for a signal input from an interface that accepts print data sent from the outside through communication means. In addition, in the case of scanner and FAX transmission, an interface for sending image data to an external device through communication means corresponds to this).
Usually, the converted / processed signal is temporarily stored in a memory. The image signal stored in the memory is subjected to the following conversion and processing, and then finally the image signal matching the characteristics is sent to the output device. In such a conversion / processing process, depending on the conditions of the image processing circuits on the input side and the output side, the system clock of the signal to be written to the memory may differ from the system clock at the time of reading from the memory.
[0010]
In the clock generation unit of this embodiment, when the system clock at the time of writing is different from the system clock at the time of reading, each clock oscillator is provided so that conversion and processing can be executed with a system clock suitable for each. A clock oscillator that generates a clock having a frequency suitable for the operation of each image processing circuit is selected in accordance with the write and read timings. In this case, no matter which clock oscillator is used, the system clock is supplied to each image processing circuit through a common signal line, so that the clock oscillator to be used is switched by a selector. In addition, it is necessary to prevent noise from appearing on the clock signal line at the time of switching, and noise generation is prevented by inserting an analog PLL on the output side of the selector.
[0011]
The present embodiment will be described more specifically based on FIG. 1 showing a main part of an image processing apparatus using the clock generation unit as described above.
As shown in FIG. 1, the clock generation unit includes two oscillators including an oscillator (1) 11 and an oscillator (2) 12 that generate clocks having different frequencies, and any one of the oscillator (1) 11 and the oscillator (2) 12. A selector 13 for selecting whether to use the clock, and an analog PLL 14 to which the clock selected by the selector 13 is input.
An image processing circuit (1) 15 is connected to an image processing circuit (2) 17 via an image memory 16, and a system clock is input to each of the image processing circuit (1) 15 and the image processing circuit (2) 17 through an analog PLL 14. To do.
In this embodiment, the oscillator (1) 11 and the oscillator (2) 12 are oscillations for the image processing circuit (1) 15 (for example, an input device) and for the image processing circuit (2) 17 (for example, an output device), respectively. With frequency. The selector 13 selects two clock signals and connects them to the input of the analog PLL 14.
[0012]
The operation of the circuit of FIG. 1 will be described. The image input signal is processed by the image processing circuit (1) 15 and input to the image memory 16. At this time, a clock having an oscillation frequency for the image processing circuit (1) 15 is selected from the oscillator (1) 11 as the system clock by the selector 13, and the processing by the image processing circuit (1) 15 and the data after the processing are performed according to this clock. Is stored in the image memory 16.
When the image for the frame is input to the image memory 16, the selector 13 is switched, and the output processing clock signal of the oscillation frequency for the image processing circuit (2) 17 is input to the analog PLL 14 from the oscillator (2) 12 as the system clock. To be. Data is read from the image memory 16 in accordance with a clock from the analog PLL 14, a processing (output processing) operation is performed by the image processing circuit (2) 17, and is output to the next image processing circuit or the outside. At this time, the processing is started after an interval of time when the analog PLL 14 is locked. In this way, it is possible to completely prevent the influence of noise generated when the selector 13 is switched.
When the output for one frame is completed and the image input mode is set again, the selector 13 is switched so that the processing clock from the oscillator (1) 11 is input to the analog PLL 14.
As described above, when an image is input to the image memory 16, when an image is output from the image memory 16, the selector 13 is controlled so that an appropriate clock frequency is selected.
[0013]
Here, an embodiment provided with means for ensuring the normal operation of the clock generation unit used in the image processing apparatus shown in FIG.
When the clock to be used is switched by the selector 13 in the clock generation unit, a certain time (LOCK time) is required for the frequency of the clock output from the analog PLL 14 to be locked (same) to the input frequency (oscillator frequency). Take it. In order to secure the operation margin of the circuit, it is better to perform processing after the analog PLL 14 is locked. For this reason, it is determined by detecting the signal (LOCK signal) at the LOCK terminal of the analog PLL 14 that the LOCK has been established, and the normal operation of the image processing circuits 15 and 17 is ensured by starting the processing.
This operation will be described in more detail with the circuit of FIG. 1. The image input signal is processed by the image processing circuit (1) 15 and input to the image memory 16. At this time, the clock of the oscillation frequency for the image processing circuit (1) 15 is selected from the oscillator (1) 11 as the system clock by the selector 13, and the processing by the image processing circuit (1) 15 and the data after the processing are performed according to this clock. Is stored in the image memory 16.
[0014]
After inputting the image for the frame to the image memory 16, the selector 13 is switched, and the clock signal of the oscillation frequency for the output processing from the oscillator (2) 12 to the image processing circuit (2) 17 as the system clock is supplied to the analog PLL 14. input. After the input, it is determined whether or not the analog PLL 14 is locked by detecting a signal (LOCK signal) at the LOCK terminal. After confirming the LOCK, the output process is started. By doing so, it is possible to ensure normal circuit operation in the minimum time, that is, to completely prevent the influence of noise generated when the selector 13 is switched.
Data is read from the image memory 16 according to the clock from the analog PLL 14, processed (output processing) by the image processing circuit (2) 17, and output to the next image processing circuit or outside.
When the image memory 16 finishes outputting an image for one frame and again enters the image input mode, the selector 13 is switched, and the oscillator (1) 11 to the image processing circuit (1) 15 as the system clock, that is, the input processing A clock signal having an oscillation frequency is input to the analog PLL 14. Also at this time, whether or not the analog PLL 14 is locked is determined by detecting a signal (LOCK signal) at the LOCK terminal, and after confirming LOCK, the input processing is started.
[0015]
Next, another embodiment in which the clock generator is different from the above embodiment will be described.
In the above-described embodiment, the analog PLL 14 is provided on the clock generation unit side separately from the image processing circuits 15 and 17, but in this embodiment, the image processing circuit is constituted by components composed only of ASIC, and the ASIC incorporates the analog PLL. To do. In this case, an analog PLL for controlling the clock is not necessary on the clock generation unit side. Also in this embodiment, if necessary, the execution timing of processing can be controlled by observing the LOCK signal of the analog PLL of each ASIC.
FIG. 2 shows a main part of the image processing apparatus of this embodiment. FIG. 3 shows an ASIC that is a component of the image processing circuit in the image processing apparatus of FIG.
As shown in FIG. 2, the clock generation unit includes two oscillators including an oscillator (1) 11 and an oscillator (2) 12 that generate clocks having different frequencies, and one of the oscillator (1) 11 and the oscillator (2) 12. It comprises a selector 13 for selecting whether to use the clock.
An image processing circuit (1) 18 and an image processing circuit (2) 19 composed of components consisting only of the ASIC 20 are connected via an image memory 16, and the image processing circuit (1) 18 and the image processing circuit (2) 19 are connected to the image processing circuit (1) 18. The system clock selected by the selector 13 is input. As shown in FIG. 3, the ASIC 20 constituting the image processing circuit (1) 18 and the image processing circuit (2) 19 includes an analog PLL 21, and inputs the system clock selected by the selector 13 through the analog PLL 21. .
The oscillator (1) 11 and the oscillator (2) 12 have oscillation frequencies for the image processing circuit (1) 18 (for example, an input device) and for the image processing circuit (2) 19 (for example, an output device), respectively. .
[0016]
The operation of the circuit of FIG. 2 will be described. An image input signal is processed by an image processing circuit (1) 18 and input to the image memory 16. At this time, a clock having an oscillation frequency for the image processing circuit (1) 18 is selected from the oscillator (1) 11 as the system clock by the selector 13, and the processing by the image processing circuit (1) 18 and the data after the processing are performed according to this clock. Is stored in the image memory 16.
After inputting the image for the frame to the image memory 16, the selector 13 is switched, and the clock signal of the oscillation frequency for output processing from the oscillator (2) 12 to the ASIC 20 is supplied from the oscillator (2) 12 as the system clock. input. After the input, whether or not the analog PLL 21 built in each ASIC 20 is locked is determined by detecting a signal (LOCK signal) at the LOCK terminal, and after confirming the LOCK, the ASIC 20 starts processing the image signal. By doing so, it is possible to ensure normal circuit operation in the minimum time, that is, to completely prevent the influence of noise generated when the selector 13 is switched.
Data is read from the image memory 16 in accordance with the clock from the analog PLL 21, processed (output processing) by the image processing circuit (2) 19, and output to the next image processing circuit or outside.
When the image memory 16 finishes outputting an image for one frame and enters the image input mode again, the selector 13 is switched, and the oscillator (1) 11 to the image processing circuit (1) 18 as the system clock, ie, the input processing A clock signal having an oscillation frequency is input to each ASIC 20. Also at this time, whether or not the analog PLL 14 is locked is determined by detecting a signal (LOCK signal) at the LOCK terminal, and after confirming LOCK, the input processing is started.
[0017]
【The invention's effect】
(1) Effects corresponding to the invention of claim 1
When one image processing unit processes the image signal and writes it to the image memory, and when another image processing unit reads and processes the image signal from the image memory, a different clock is supplied in accordance with each image processing operation. , by providing a clock selection unit for switching the clock from the oscillation source for generating the different clock, it becomes possible to operate the certain image processing unit and a separate image processing unit at different clock frequencies, using the image memory Conversion and processing can be easily realized under optimum conditions and with a simple circuit configuration.
(2) The effect corresponding to the invention of claim 2 In addition to the effect of (1) above, by providing an analog PLL on the output side of the clock selection section , it is possible to prevent noise from being generated in the clock signal line. Can do.
(3) Effect corresponding to invention of claim 3 In addition to the effect of (2) above, the image processing unit is configured by an ASIC incorporating an analog PLL as a circuit element, thereby further simplifying the circuit and reducing the number of parts. Can be reduced.
(4) Effects corresponding to the invention of claim 4 In addition to the effects of (2) and (3) above, by detecting the LOCK signal of the analog PLL and operating the image processing unit according to the detection result Thus, normal circuit operation can be performed with the minimum analog PLL LOCK time.
[Brief description of the drawings]
FIG. 1 shows a main part of an embodiment of an image processing apparatus according to the present invention having a clock generation unit for supplying a different system clock in accordance with each conversion / processing operation.
FIG. 2 shows a main part of another embodiment of an image processing apparatus according to the present invention having a clock generation unit for supplying a different system clock in accordance with each conversion / processing operation.
3 shows an ASIC that is a component of an image processing circuit in the image processing apparatus of FIG. 2;
[Explanation of symbols]
11 ... Oscillator (1), 12 ... Oscillator (2),
13 ... Selector, 14 ... Analog PLL,
15 ... Image processing circuit (1), 16 ... Image memory,
17 ... Image processing circuit (2), 18 ... Image processing circuit (1),
19 ... Image processing circuit (2), 20 ... ASIC,
21: Analog PLL.

Claims (4)

A plurality of image processing unit for processing the input image signal, each having an oscillation source, and a plurality of clock generator for generating a system clock for operating the image processing unit, an output of said plurality of clock generation unit met image processing apparatus and a clock selection unit for selecting and outputting,
The plurality of image processing units are connected via an image memory,
The output of the clock selection unit is input to the plurality of image processing units, and the clock selection unit operates the image processing unit when a certain image processing unit processes an image signal and writes it to the image memory. And selecting a system clock for operating the other image processing unit when the other image processing unit reads and processes the image signal written in the image memory. apparatus. The image processing apparatus according to claim 1, further comprising an analog PLL on an output side of the clock selection unit . The image processing apparatus according to claim 2, the image processing apparatus, wherein the analog PLL is a circuit element of an ASIC that constitutes the image processing unit. 4. The image processing apparatus according to claim 2, wherein the LOCK signal of the analog PLL is detected, and the image processing unit is operated according to a detection result.

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