JPS6019358A - Picture overlay printer - Google Patents

Abstract

PURPOSE:To use only one output device to plural pieces of information and to attain the connection to various devices by designing the device to select, synthesize and replace partially plural picture signals independently of a binary value or half tone. CONSTITUTION:In selecting either binary or half tone picture signal through the mode setting 4, the signal is selected by a binary value selecting circuit 5 in the binary value output mode, the signal passes through a synthesizing circuit 6 and is transmitted as a digitized picture signal 7. Further, in the half tone output mode, the signal is selected by a half tone selection circuit 8, the signal passes through the synthesizing circuit 6 and is transmitted as the digitized picture signal 7. In case outputting two picture signals overlaied by the mode setting 4, when both two picture signals are in the binary value output mode, the binary value picture output is synthesized by a gate 9, selected by the binary value selection circuit 5 and transmitted as the digitized picture signal 7 through the synthesizing circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an image overlay printer that converts a plurality of image signals, whether binary or halftone, into one image signal that satisfies various conditions and prints the signal.

(Background Art) There has been a conventional image overlay printer that combines an electrostatic copying machine and a laser link.

Although this type of printer was able to overlay digital output from a computer or the like in addition to the original image, the degree of freedom in combining a plurality of image information was limited by simply overlaying the image information.

(Problem to be solved by the invention) The present invention selects, combines, and partially replaces a plurality of image signals.
It is characterized by being output as an image signal, and its purpose is to synthesize and replace image data and fixed data of terminals, etc., and to synthesize fixed data.

The present invention may be carried out together with a magnetic printing device (in particular, an overlay printer shown in FIG. 10) having a copying function as shown in Japanese Patent Application No. 6,195. The image signal is a document reading image signal based on (■■), and the other image signal is an image signal representing characters and figures output from a word processor or computer, and both are raster scanning image signals.

(Structure and operation of the invention) FIG. 1 is a block diagram of an embodiment of the invention, and shows the case of two input image signals. 1 is a control circuit, 2 is a digitized image signal 1' sending section, 3 is a digitized image signal 2 sending section, 4
is the mode setting, 5 is the binary selection circuit, 6 is the synthesis circuit,
7 is a digitized image signal, 8 is a halftone selection circuit, 9 is a gate, 10 is a comparison circuit, 11 is a selection setting circuit, 12 is a different mode overlay circuit, and 13 is an area setting circuit.

In this operation, the control circuit 1 sends a synchronization index and a sampling clock to the digitized image signal 1' sending unit 2 and the digitized image signal 2' sending unit 3, and synchronizes the image signal outputs. digitized image signal 1' sending unit 2;
From the digitized image signal 2' sending unit 3 to the control circuit 1,
Sends a binary, halftone mode identification signal. still,
It is assumed that the binary image signal shares the image signal line used in the halftone mode, and uses one bit of the image signal line. The processing form of the image signal is determined by the external mode setting 4, but part or all of the mode setting 4 may be sent from the digitized image signal 1' sending unit 2 and the digitized image signal 2' sending unit 3. . Furthermore, the configurations of the digitized image signal 1' sending unit 2 and the digitized image signal 2' sending unit 3 are in one form in which the signal is sent out within the same device as the circuit of the present invention, and in another form in which the signal is sent out from within an external device. Needless to say, there are cases where both are taken.

Here, when selecting either a binary image signal or a halftone image signal from the mode setting 4, in the case of a binary output mode, the image signal is selected in the binary select circuit 5, passes through the synthesis circuit 6, and is converted into a digitized image signal. Sent as 7. Further, when a halftone output format is used, it is selected by the halftone selection circuit 8, passes through the synthesis circuit 6, and is sent out as a digitized image signal 7.

In the case where two image signals are overlaid and output by mode setting 4, when both image signals are in binary output form, the binary image signal output is synthesized at gate 9, and
It is selected by the value selection circuit 5, passes through the synthesis circuit 6, and is sent out as a digitized image signal 7. Furthermore, when both of the two image signals are in the halftone output format, the image signals enter the halftone select circuit 8 and at the same time the comparison circuit 10
Enter. Here, the halftone density is compared and determined, and a signal is output to the select setting circuit 11. A selection signal is sent from the selection setting circuit 11 to the halftone selection circuit 8, and among the binary image signals, the signal with high density is selected in the halftone selection circuit 8, passes through the synthesis circuit 6, and is converted into a digitized image signal 7. Sent as . Furthermore, if one of the image signals is in the binary output format and the other is in the halftone output format, the binary output format image signal passes through the binary selection circuit 5, and the different mode overlay circuit 12 selects the halftone selection circuit. 8, and when the binary output is on the black side, the halftone output signal is forcibly set to the highest density. When the binary output is on the white side, the halftone output signal is output as is. This idea is to give priority to the dark signal among the two types of image signals. The processed image signal is output from the halftone selection circuit 8, passes through the synthesis circuit 6, and is sent out as a digitized image signal 7.

Further, when mode setting 4 is used to output the other image signal only within a designated area in the single image signal output mode, the area to be replaced is first inputted to area setting circuit 13 using mode setting 4. Then, a switching timing signal is sent from the area setting circuit 13 to the select setting circuit 11 to cause the control signal outputted from the select setting circuit 11 to be switched. When both image signals are in binary output format, the two image signals are output from the binary select circuit 5.
The signal is selected and switched in the necessary range, passes through the synthesis circuit 6, and is sent out as a digitized image signal 7.

When the two image signals are in the halftone output format, the two image signal outputs enter a halftone selection circuit 8, are selected and switched in a necessary range, pass through a synthesis circuit 6, and are sent out as a digitized image signal 7. If one image signal is in the binary output format and the other is in the halftone output format, the binary output image signal passes through the binary select circuit 5, and the halftone output image signal passes through the halftone select circuit 8. , are selected in the synthesis circuit 6, switched in a necessary range, and sent out as a digitized image signal 7. At this time, if necessary, a switching timing signal is sent from the area setting circuit 13.

The advantage of this circuit configuration is that serial processing and complex processing of various digitized image signals can be easily performed.

FIG. 2 is a circuit diagram of one embodiment of the present invention, and is an example of two inputs of a 4-bit digitized image signal.

101 is a part of a control circuit, 102 is a digitized image signal 1
'Sending unit, 103 is a digitized image signal 2' sending unit, 10
4 is a mode setting part, 105 is a binary selection circuit, 1
06 is a synthesis circuit, 107 is a digitized image signal, 108 is a halftone selection circuit, 109 is a gate, 110 is a comparison circuit, 111 is a selection setting circuit, 112 is a different mode overlay circuit, and 113 is an area setting circuit.

FIG. 2 is a more detailed circuit diagram of FIG. 1.

Reference numeral 101 represents a part of the control section, which generates control signals using a circuit including a CPU, I/O, and the like. Further, the mode setting 104 represents a part of the output section, and is a control signal based on a signal from a panel, interface equipment, etc. The area setting circuit 113 uses a latch circuit to set and hold each counter value before sending out the image signal, operates the counter circuit simultaneously with sending out the image signal, and generates an area signal.

In FIG. 2, for example, when outputting the other image signal only within an area specified in a single image signal output format, one image signal is in a binary output format (for example, a print signal representing characters or figures from a computer). and the other is half-tone
The output format (for example, a document reading signal from a CCD) will be explained.

Binary output from d of digitized image signal 1'102, halftone output from c, f, g, h of digitized image signal 2'103
There is an output. (hereinafter simply referred to as binary output or halftone output) On the other hand, depending on the mode setting, the control circuit 101
By the control signal and area setting circuit 113 output,
The select setting circuit 111 is controlled and a select signal is output to each of the halftone select circuit 108, binary select circuit 105, different mode overlay circuit 112, and synthesis circuit 106.

The binary output is selected by a binary selection circuit 105 and input to a synthesis circuit 106.

On the other hand, the halftone output is provided by the halftone select circuit 10.
The 3 bits selected by 8 become the digitized image signal 107, and the remaining 1 bit goes to the synthesis circuit 106.

The synthesis circuit 106 is switched across the area specified by the area setting circuit 113, and sends a binary output to one bit of the digitized image signal 107 outside the area.

In addition, within the area, all 4 of the digitized image signals 107
Sends halftone output to bit. At this time, the area setting circuit 113 sends out a switching timing signal.

Here, the area setting circuit 113 will be explained in detail.

The operation is to input each counter value into a latch circuit before sending out an image signal. To explain this specifically, the counter 201 is initial reset,
Start counting by the clock. Decoder 2
Decode with 02. This decode signal becomes a latch timing signal for the latch circuit groups 203, 204, 205, 206, 207, and 208. On the other hand, the latch data 209 changes in synchronization with the counter clock signal. Data is latched into latch circuit groups 203, 204, 205, 206, 207, and 208 by the decoder 202 and latch data 209. At this time, the counter circuit groups 210, 211, 212, which determine the start of image signal switching, and the counter circuit groups 213, 214, 215, which determine the end of image signal switching, maintain a loaded state, take in the latch data by the counter clock of the gate 216, and wait. It has become a state.

At the same time as the image signal is sent out, a load release signal is output from the gate 217, and the flip-flop groups 218, 219 and 22
0 and 221, the counter groups 210 and 211
, 212, 213, 214, and 215 are started. Here, counter groups 210, 211, 212
When underflow occurs, the flip-flop 218 is operated, the flip-flop 222 is changed, and at the same time, the counter groups 210, 211, and 212 are kept in a loaded state. On the other hand, when the counter groups 213, 214, and 215 similarly underflow, the flip-flop 220 is operated, the flip-flop 222 is changed, and at the same time, the counter groups 213, 214, and 215 are kept in the loaded state. In order to set the output of the flip-flop 222 in the switching region to H level, the latch circuit groups 203, 204, 2
05 latch data to latch circuit groups 206, 207, 2
It is sufficient to set it to a value smaller than the latch data of 08.

When specifying an area from four sides on the document surface, the area specifying block 223 is operated in the same manner as described above, and the flip-flop 224 generates an output signal.

The flip-flop 222 and the flip-flop 2
The output signals from 24 are combined at a gate 225 and used as a control signal for the select setting circuit 111. This operation is shown in the timing chart of FIG.

The composite image signal created in this manner is used, for example, in a magnetic printing device as shown in FIG.

The composite image signals 1 to 4 enter a recording pulse generator (A) 120. Here, special public service No. 56-33, 707 (A1966)
As shown in , a low frequency pulse is generated for a dark image and a high frequency pulse is generated for a light image depending on the halftone information. The composite image signal 4 is also generated by a recording pulse generator (
B) Also included in 121. Here, the special public service is Sho 55-34, 43.
As shown in No. 1 (A2007), a pulse with a predetermined constant frequency is generated for a binary image signal. Based on the signal from the area setting circuit 113, the select setting circuit 111 operates to enable the output of either of the generators (A) or (B) and apply it to the head driver 122. is formed. In this way, as shown in FIG. 3, image signal 1 is recorded as a binary signal in areas A and C, and image signal 2 is recorded as a halftone signal in area 13.

In FIG. 2, as another example, a case will be described in which two image signals are in the halftone output format.

Halftone output from a, b, c, d of digitized image signal 1'102, similarly digitized image signal 2'103
A halftone output is output from e, f, g, and h.

The two halftone outputs enter comparator 110 at the same time as they enter halftone select circuit 108 .

Here, the halftone density is compared and determined, and a signal is output to the select setting circuit 111.

In one-way mode setting, the control signal output from the control circuit 101 is sent to the select setting circuit 111.

Under these controls, the select setting circuit outputs a select signal to each of the halftone select circuit 108 and the synthesis circuit 106.

According to the above procedure, among the halftone outputs, the number with the higher halftone density is output.

(Effects of the Invention) As explained above, since multiple image signals, regardless of binary or halftone, can be selected, combined, and partially replaced, there is an advantage that only one output device is required for multiple input information. Moreover, since the binary output format image signal and the halftone output format image signal can also be combined and replaced, there is an advantage that a wide variety of devices can be connected.

[Brief explanation of the drawing]

Figure 1 is a block diagram of one embodiment of the circuit of the present invention, Figure 2 is a more detailed circuit diagram of Figure 1, and Figure 3 is a block diagram of one embodiment of the circuit of the present invention.
A timing chart diagram showing an example of operation. FIG. 4 is a diagram showing an example of a recording circuit using the present invention. 4: Mode setting circuit, 8: Halftone select, 5: Binary select circuit, Patent applicant: Iwasaki Tsushinki Co., Ltd. Patent application agent: Keiichi Yamamoto, patent attorney

Claims (1)

[Claims] In an image overlay printer that prints one composite image signal synthesized from a plurality of image signals, means for specifying and setting a screen area, and a means for specifying and setting a screen area from the plurality of image signals for the set area. An image overlay printer comprising means for outputting one image signal selected according to predetermined conditions as a composite image signal.