JP2001326570A - Level conversion circuit and liquid crystal driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level conversion circuit having reduced power consumption. SOLUTION: An input signal is level-converted in order by two stages of level shifters LS1 and LS2, and its output is waveformed and outputted by an output circuit OC1. In this case, since the edge of the output signal LS2OUT of the level shifter LS2 becomes dull compared with the output signal LS1OUT of the level shifter LS1, an element in an output circuit OC1 on/off-controlled by this signal LS2OUT generates an entirely ON period to generate through current. However, since a cut off element COT on/off-controlled by the signal LS1OUT with a sharper edge is included in the output circuit OC1, the through current is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a level conversion circuit,
The present invention also relates to a liquid crystal driving circuit that outputs a liquid crystal driving voltage using the level conversion circuit.

[0002]

2. Description of the Related Art A level conversion circuit is used to receive two input signals having a very small potential difference and to output the potential difference while expanding it. This is also applied to, for example, generation of a liquid crystal driving voltage.

As shown in FIG. 7, a conventional level conversion circuit includes level shifters LS1 and LS2 and an inverter I.
N11 and IN12 were provided. Here, the input signal IN input to the level shifter LS1 and the inverted input signal / I
N potential differences GND to V1 (V1> GND), power supply voltages V1, V2 (V2 <GN) supplied to the level shifter LS1.
D), level shifter LS2, inverters IN11 and I
Power supply voltages V2 and V3 supplied to N12 (V3> V2)
FIG. 3 shows the relationship between the levels.

The level shifter LS1 has input signals IN,
An inverted input signal / IN is input, and an output signal LS having a voltage range V2 to V1 corresponding to the relative potential difference therebetween.
1OUT and / LS1OUT are output.

The level shifter LS2 includes a level shifter L
The S1 output signals LS1OUT and / LS1OUT are input, and corresponding to the relative potential difference between them, the voltage range V2
An output signal LS2OUT having V3 is output.

The output signal LS2OUT is shaped by two-stage inverters IN11 and IN12 and output as an output signal OUT.

[0007]

However, the conventional level conversion circuit has the following problems. Inverter IN
Until the signal LS2OUT is input to 11, the signal 11 goes through the two-stage level shifters LS1 and LS2. Therefore, the output signal LS2OUT of the level shifter LS2 has a sharper edge than the output signal LS1OUT of the level shifter LS1. In particular, the signal LS2OUT
At the time of falling from the high level (V3) to the low level (V2) in FIG.

When the signal LS2OUT is input to the inverter IN11, a period occurs in which both the P-channel MOS transistor P41 and the N-channel MOS transistor N41 are turned on, and a through current flows. As a result, the current consumption of the entire circuit increases. In particular, in a liquid crystal driving circuit that requires low power consumption such as a portable terminal, this becomes a serious problem.

The present invention has been made in view of the above circumstances, and has as its object to provide a level conversion circuit and a liquid crystal drive circuit capable of reducing power consumption.

[0010]

According to the present invention, there is provided a level conversion circuit which receives an input signal, performs a level shift according to the supplied first and second power supply voltages, and outputs a first signal. A first level shifter, a second level shifter receiving the first signal, performing a level shift according to the supplied second and third power supply voltages, and outputting a second signal; An output circuit for receiving a signal, receiving second and third power supply voltages, performing waveform shaping processing and outputting a third signal, wherein the output circuit includes a second and third power supply voltage. An element which is connected in series in a path between terminals and which is supplied with the first signal and controlled on / off is included.

The output circuit includes a first P-channel MOS transistor having a source connected to a third power supply voltage terminal and having the gate receiving the second signal, and a first P-channel MOS transistor. A second P-channel MOS transistor having a source connected to the drain thereof, a gate receiving the second signal, and a drain connected to an output terminal for outputting the third signal; and a drain connected to the output terminal. Are connected, the first signal is input to the gate, a first N-channel MOS transistor as the element, the drain is connected to the source of the first N-channel MOS transistor, and the gate is connected to the gate. Second
And a second N-channel MOS transistor having a source connected to the second power supply voltage terminal.

A liquid crystal drive circuit according to the present invention is provided with a plurality of shift registers which are supplied with a clock, sequentially transfer predetermined signals supplied to an initial stage to a subsequent stage, and generate and output the input signals, respectively. A plurality of the level conversion circuits provided corresponding to the plurality of shift registers, and a plurality of buffers each receiving the third signal output from the plurality of level conversion circuits, and amplifying and outputting the same. It is characterized by having.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

The level conversion circuit according to the first embodiment of the present invention has the configuration shown in FIG. The voltage used here includes V2 <GN as shown in FIG.
It is assumed that there is a relation of D <V1 <V3.

The level conversion circuit according to the present embodiment
Stage level shifters LS1 and LS2 and an output circuit OC1
And

The level shifter LS1 includes power supply voltages V2 and V1.
, And an input signal IN having a voltage range from the ground voltage GND to the power supply voltage V1, and an inverted input signal / IN are input. Then, a signal LS1OUT that is level-shifted so as to expand the relative potential difference between the input signal IN and the inverted input signal / IN to the potential difference between V1 and V2 is output.

The level shifter LS2 has power supply voltages V2 and V3.
And the output signal LS1OUT of the level shifter LS1 having a voltage range of V1 to V2 is input. Then, a signal LS2OUT which is level-shifted so as to expand the potential difference of the signal LS1OUT to the potential difference of V2 to V3 is output.

The output circuit OC1 is supplied with the power supply voltages V2 and V3, amplifies the waveform of the signal LS2OUT, and outputs the amplified signal.

Here, the power supply voltage V is applied to the output circuit OC1.
A cut-off element COT connected in series is provided in a path between the two terminals and the power supply voltage V3 terminal. The other elements included in the output circuit OC1 are controlled on / off by the output signal LS2OUT of the level shifter LS2. This output signal LS2OUT is a two-stage level shifter LS
1. The edge is dull because it is generated through LS2. In particular, the edge falling from the high level (V3) to the low level (V2) is dull. Thereby, the element connected to the power supply voltage V3 terminal and the power supply voltage V3
The elements connected to the two terminals are simultaneously turned on, and the power supply voltage V
A through current is generated from the three terminals to the power supply voltage V2 terminal.

However, the cut-off element COT here
Is turned on / off by an output signal LS1OUT of the level shifter LS1. The output signal LS1OUT of the level shifter LS1 is equal to the output signal LS of the level shifter LS2.
The edge is steeper than 2OUT. Therefore, a path through which a through current flows from the power supply voltage V3 terminal to the power supply voltage V2 terminal is cut off, and power consumption is reduced.

A level conversion circuit according to a second embodiment of the present invention embodies the circuit configuration of the level shifters LS1 and LS2 and the output circuit OC1 in the first embodiment, and an inverter as an output circuit. IN2
Is further added, and has a configuration shown in FIG.

This embodiment includes level shifters LS1 and LS2 and inverters IN1 and IN2.

The level shifter LS1 has a source connected to the power supply voltage V1 terminal and an input signal I
N, P-channel type MO to which inverted input signal / IN is input
The drains are connected to the respective drains of the S transistors P1 and P2 and the transistors P1 and P2, and the drains are connected to the sources of the N-channel MOS transistors N1 and N2 and the transistors N1 and N2 whose gates are connected to the drains of the transistors P2 and P1, respectively. Are connected, the gates are connected to the gates of the transistors P1 and P2, respectively, and the sources are N-channel MOS transistors N3 and N4 both connected to the power supply voltage V2 terminal. Then, the inverted output signal / LS1OUT is output from the drain of the transistor P1, and the output signal LS1OUT is output from the drain of the transistor P2.

The level shifter LS2 has a source connected to the power supply voltage V3 terminal and a gate connected to the level shifter LS1.
Output signal LS1OUT, inverted output signal / LS1OUT
Is input, a P-channel MOS transistor P11,
P12, P-channel MOS transistors P13, P14, a transistor P1 having a source connected to the drain of each of the transistors P11, P12 and a gate connected to the drains of the transistors P12, P11, respectively.
3. The drain is connected to the drain of P14, respectively.
Gates are connected to the gates of the transistors P11 and N12, respectively, and sources are N-channel MOS transistors N11 and N12 both connected to the power supply voltage V2 terminal. Then, the output signal LS2OUT is output from the drain of the transistor P14.

The source and drain of the P-channel MOS transistors P21 and P22 and the drain and source of the N-channel MOS transistors N21 and N22 are connected in series between the power supply voltage V3 terminal and the power supply voltage V2 terminal. Have been. Here, the transistor P
21, P22 and N22 have level shifters LS2
Output signal LS2OUT of the transistor N2
The output signal LS1O of the level shifter LS1 is connected to the gate of No. 1.
UT is input. From the drain of the transistor P22 and the drain of the transistor N21, the inverter IN1
Is output.

The inverter IN2 has a power supply voltage V3 terminal,
A P-channel MOS transistor P31 is provided between the V2 terminals.
, The drain and source of the N-channel MOS transistor N31 are connected in series, the output signal of the inverter IN1 is input to both gates, and the output signal OUT is output from each drain.

For example, when the input signal IN is GND and the inverted input signal / IN is V1, in the level shifter LS1, the transistor P1 turns on and P2 turns off. The drain of the transistor P1 rises to the voltage V1 and becomes higher in level than the drain of the transistor P2, so that the transistor N2 turns on and N1 turns off. Since the transistor N4 is turned on and the transistor N3 is turned off, a low-level (V2) output signal LS1OUT and a high-level (V1) output signal / LS1OUT are output.

In the level shifter LS2, the transistor P11 in which the low-level signal LS1OUT is input to the gate turns on, the transistor N11 turns off, and the transistor P12 in which the high-level signal / LS1OUT is input to the gate turns off. N12 turns on. Further, the transistor P13 whose gate receives the drain voltage of the low-level transistor N12 is turned on, and the transistor P14 whose gate receives the drain voltage of the high-level transistor N11 is turned off. As a result, the low-level (V2) output signal LS2O
The UT is output.

The transistor P21 of the inverter IN1,
A low level signal LS2O is applied to the gates of P22 and N22.
The UT is input, a low-level signal LS1OUT is input to the gate of the transistor N21, and an inverted high-level (V3) signal is output.

When this signal is input to the inverter IN2, an inverted low level (V2) output signal OUT is output.

The input signal IN is V1, the inverted input signal / IN
Is GND, the polarity is opposite to this, and the description is omitted.

Here, the input signal IN and the level shifter LS
1, the output signal LS1OUT of the level shifter LS2, the output signal OUT of the inverter IN2.
And the current consumption LS1 of the level shifter LS1
CT, consumption current LS2CT of the level shifter LS2, consumption current IN1CT of the inverter IN1, and inverter IN2
And the respective current waveforms of the consumed current IN2CT are shown in the time chart of FIG.

As described above, the output signal LS2OUT of the level shifter LS2 has a duller edge than the output signal LS1OUT of the level shifter LS1. In particular, the signal L
The falling edge EDGE2 of S2OUT is the signal LS
It is much slower than the falling edge EDGE1 of 1OUT.

Therefore, the output signal L of the level shifter LS2
The transistor P21 having S2OUT input to its gate,
In P22 and N22, the period during which all of them are turned on at the falling edge EDGE2 becomes long. However, the output signal LS
The transistor N21 having 1OUT input to its gate is:
Since the falling edge EDGE1 is steeper, an action of cutting off a path through which a current flows from the power supply voltage V3 terminal to the power supply voltage V2 terminal in a shorter time occurs.

For this reason, the current consumption of the inverter IN1 is reduced as shown by the arrow, which can contribute to the power consumption of the entire circuit.

The liquid crystal drive circuit according to the third embodiment of the present invention has the level conversion circuit according to the first or second embodiment built in a liquid crystal drive circuit.

FIG. 5 shows a liquid crystal panel LCDP, gate drivers GD1 to GDp (p is an integer of 1 or more) as liquid crystal driving circuits, and source drivers SD1 to SDq (q is
(An integer of 1 or more).

The gate drivers GD1 to GDp are supplied with a clock CLK1 output from the controller CTRL and an enable signal as an input signal DIO1, and supply a voltage for controlling scanning of gate lines arranged in the row direction of the liquid crystal panel LCDP. Output. Source driver SD1-S
Dq is supplied with a clock CLK2 output from the controller CTRL and data of a predetermined number of bits as an input signal DIO2, and outputs a video signal to be supplied to a signal line wired in the column direction of the liquid crystal panel LCDP.

The gate drivers GD1 to GD1 each have a configuration as shown in FIG. 6, for example. Here, the gate driver GD1 will be described as an example.

The shift register S, the level conversion circuit LC,
Pre-buffer PB, block having buffer B is n
(N is an integer of 2 or more). The clock CLK1 is input to the shift registers S1 to Sn of each block via the input buffer BF. The enable signal is input to the shift register S1 of the first-stage block as the input signal DIO1.

The shift register S1 has a clock CLK1.
At the same time, the enable signal is transferred to the subsequent shift register S2, and the input signal IN having the potential difference between V1 and GND and the inverted input signal / IN are output to the level conversion circuit LC1.

The output signal D0I1 of the shift register Sn will be described with reference to FIG.

The level conversion circuit LCL1 has V1 to GND
Signal IN and inverted input signal / IN having a potential difference of
Is converted into a signal having a potential difference between V2 and V3 expanded in the positive and negative directions, respectively, and output.

The output signal of the level conversion circuit LC1 is amplified by the pre-buffer PB1 and the buffer B1, and is output as a liquid crystal driving signal LCD1, and is output from the liquid crystal panel LC1.
It is applied to the DP scan line.

The sequentially shifted signal is output as an output signal DOI1 from the last-stage shift register Sn, and the gate driver GD shown in FIG.
2 as an input signal DIO2.

Here, the shift registers S1 to Sn are of a low volt (LV) type and operate in a voltage range of V1 to GND.

The level conversion circuits LC1 to LCn, the pre-buffers PB1 to PBn, and the buffers B1 to Bn are of a high volt (HV) type and operate in a voltage range of V2 to V3.

By applying the level conversion circuit according to the first or second embodiment to the level conversion circuits LC1 to LSn in the liquid crystal driving circuit having such a configuration, a through current generated in this portion is reduced. And the power consumption of the entire circuit is reduced.

The above embodiment is merely an example and does not limit the present invention. For example, although the second embodiment has a configuration in which two stages of inverters are connected in series as an output circuit, it is sufficient that at least one output circuit including a cutoff element is provided. Further, the configurations of the level shifter and the output circuit are not limited to those shown in FIG. 2, and various modifications such as omitting the transistor P22 in the inverter IN1 in FIG. 2 are possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a level conversion circuit according to a second embodiment of the present invention.

FIG. 3 shows voltages V2, GND,
FIG. 4 is an explanatory diagram showing a level relationship between V1 and V3.

FIG. 4 is a time chart showing an operation waveform of each signal in the level conversion circuit.

FIG. 5 is a block diagram showing a liquid crystal driving circuit, a liquid crystal panel, and a controller to which the level conversion circuits according to the first and second embodiments can be applied.

FIG. 6 is a block diagram showing a circuit configuration of a gate driver in the liquid crystal driving circuit.

FIG. 7 is a circuit diagram showing a configuration of a conventional level conversion circuit.

[Explanation of symbols]

LS1 level shifter LS2 level shifter IN input signal / IN inverted input signal LS1OUT, LS2OUT output signal OC1, OC2 output circuit V1, V2, V3 power supply voltage P1, P2, P11, P12, P21 to P22, P31
P-channel MOS transistors N1 to N4, N11 to N14, N21, N22, N31
N-channel MOS transistor COT Cut-off device

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H03K 17/16 H04N 5/66 102B 5J056 17/687 H03K 19/00 101E H04N 5/66 102 17 / 687F (72) Inventor Tsuyoshi Nakajo 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture F-term in Toshiba Microelectronics Co., Ltd. (reference) FF09 GG02 JJ02 JJ03 JJ04 5J055 AX27 AX55 AX64 BX16 CX30 DX22 DX56 DX72 DX83 EX07 EX21 EY21 EZ07 EZ20 FX12 FX17 FX35 GX01 GX04 5J056 AA00 AA11 BB19 CC21 DD13 DD29 EE07 EE11 FF00 KK

Claims (3)

[Claims] A first level shifter receiving an input signal, performing a level shift according to the supplied first and second power supply voltages, and outputting a first signal; and providing the first signal. A second level shifter that performs a level shift according to the supplied second and third power supply voltages and outputs a second signal; and a second and third power supply that is supplied with the second signal. An output circuit that is supplied with a voltage, performs a waveform shaping process, and outputs a third signal. The output circuit is connected in series in a path between second and third power supply voltage terminals, A level conversion circuit comprising an element which is supplied with the first signal and controlled to be turned on / off. 2. The output circuit includes a first P-channel MOS transistor having a source connected to a third power supply voltage terminal and a gate receiving the second signal, and a first P-channel MOS transistor. A second P-channel MOS transistor having a source connected to a drain of the MOS transistor, a gate receiving the second signal, and a drain connected to an output terminal for outputting the third signal; A first N-channel MOS transistor as the element, the drain of which is connected to the gate of the first N-channel MOS transistor and the gate of which the first signal is input; The second
2. The level conversion circuit according to claim 1, further comprising: a second N-channel MOS transistor having a source connected to a second power supply voltage terminal. 3. A plurality of shift registers that are supplied with a clock and sequentially transfer predetermined signals supplied to an initial stage to a subsequent stage, and generate and output the input signals, respectively. 3. A plurality of level conversion circuits according to claim 1 or 2, provided correspondingly, a plurality of buffers each receiving, amplifying and outputting the third signal output from the plurality of level conversion circuits, A liquid crystal drive circuit comprising: