KR100295648B1 - Driver circuit for thin film transistor-liquid crystal display gate - Google Patents

Abstract

PURPOSE: A TFT-LCD gate driver circuit is provided to prevent final outputs from being overlapped by reducing a width with regard to an output waveform of a level shifter. CONSTITUTION: A shift register(10) receives a pulse(STV) and outputs the first and second shifting signals(IN1, IN2) in synchronization with an external clock signal(CPV). The first and second level shifters(11, 12) receive and shift the first shifting signals from the shift register(10), respectively. The first and second schmitt trigger parts(20, 21) receive the first and second level shifting signals(LVSFT_01, LVSFT_02) from the level shifters(11, 12) and remove the pulse width of the received signals by a predetermined pulse width, respectively. The first and second inverter parts(13, 14) receive and invert trigger signals(SCH_01, SCH_02) from the first and second schmitt trigger parts(20, 21), respectively. The first and second output buffers(15, 16) receive and output the first and second inverted amplified signals(INV1_01, INV1_02), respectively.

Description

TF-LC gate driving circuit {DRIVER CIRCUIT FOR THIN FILM TRANSISTOR-LIQUID CRYSTAL DISPLAY GATE}

The present invention relates to a TFT-CD gate driving circuit, and more particularly, to a TFT-CD gate driving circuit which can prevent overlapping of the final output signal by reducing the width of the level shifter output waveform by using a Schmitt trigger. will be.

FIG. 1 is a block diagram showing an embodiment of a conventional TFT-PCD gate driving circuit. As shown in FIG. 1, a pulse STV is input and synchronized with an external clock signal CPV. A shift register 10 for outputting first and second shifting signals IN1 and IN2; First and second level shifters (11) and (12) receiving the first and second shifting signals (IN1) and (IN2) of the shift register (10), respectively, and shifting them to a predetermined level; First and second inverter units 13 for receiving the first and second level shifting signals LVSFT_01 and LVSFT_02 of the first and second level shifters 11 and 12, respectively, and inverting and amplifying them. (14); The first and second inverted amplifier signals INVI_01 and INVI_02 of the first and second inverter units 13 and 14 are respectively input, and the first and second inverted amplifier signals INVI_01 and INVI_02 are respectively input. The first and second output buffers 15 and 16 which are output to the outside according to the level of) are described with reference to the timing diagram of FIG. 2.

First, the shift register 10 receives a predetermined pulse signal STV and synchronizes it with an external clock signal CPV, so that the first and second shifting signals IN1 and IN2 as shown in FIG. ) Are applied to the first and second level shifters 11 and 12, respectively.

Accordingly, the first and second level shifters 11 and 12 input first and second shifting signals IN1 and IN2 as shown in FIG. 2A of the shift register 10. It receives the shifted to a predetermined level and outputs the first and second level shifting signals LVSFT_01 and LVSFT_02 as shown in FIG. 2B. At this time, the first and second inverter units 13 and 14 are output. ) Receives the first and second level shifting signals LVSFT_01 and LVSFT_02 as shown in FIG. 2B of the first and second level shifters 11 and 12, and inverts and amplifies them. It is applied to the first and second output buffers 15 and 16.

Accordingly, the first and second output buffers 15 and 16 may include the first and second inverted amplification signals (c) of FIG. 2 from the first and second inverters 13 and 14. When the level of the first and second inverted amplification signals INVI_01 and INVI_02 is greater than or equal to a predetermined level, the signals OUT1 and OUT2 as shown in FIG. Will output

That is, the shift register 10 transfers the externally input pulse signal STV by one channel in synchronization with the external clock signal CPV, and the first and second level shifters 11 and 12 are described above. The low voltage signals IN1 and IN2 output from the shift register 10 are converted into the high voltage signals LVSFT_01 and LVSFT_02 required to drive the gate lines, and are output. The first and second level shifters 11 are outputted. The output signals LVSFT_01 and LVSFT_02 of (12) are inverted and amplified through the first and second inverter units 13 and 14 so that the first and second output buffers 15 and 16 are turned on. The first and second inverters 13 and 14 and the first and second output buffers 15 and 16 control gate lines that act as very large capacitive loads. Drive.

However, the conventional apparatus operating as described above has a problem in that the waveforms of adjacent output signals are overlapped, so that the adjacent gate lines are turned on at the same time, thereby causing charge sharing, thereby degrading image quality.

Therefore, the present invention devised in view of the above-described problems is to reduce the width of the level shifter output waveform by using the Schmitt trigger circuit to prevent the overlapping of the final output TF-LC gate drive circuit The purpose is to provide.

1 is a block diagram showing a configuration of a conventional TFT-CD gate driving circuit.

FIG. 2 is an output waveform diagram of each part in FIG. 1; FIG.

Figure 3 is a block diagram showing the configuration of the TFT-PCD gate driving circuit of the present invention.

FIG. 4 is a circuit diagram showing the structure of the Schmitt trigger unit in FIG.

FIG. 5 is an output waveform diagram of each part in FIG. 3; FIG.

Figure 6 shows the transmission characteristics of the Schmitt trigger unit.

* Description of the symbols for the main parts of the drawings *

10: shift register 11, 12: level shifter

13, 14: inverter section 15, 16: output buffer

20, 21: Schmitt trigger part

The present invention for achieving the above object is a shift register for receiving a pulse and synchronizing it with an external clock signal and outputs a plurality of shifting signals accordingly; A plurality of level shifters which receive a plurality of shifting signals of the shift register and shift them to a predetermined level; A plurality of inverter units receiving a plurality of level shifting signals respectively output from the plurality of level shifters and inverting and amplifying them; In the TFT-LC gate driving circuit comprising a plurality of output buffers respectively receiving a plurality of inverted amplification signals outputted from the plurality of inverter units and outputting the plurality of inverted amplification signals to the outside according to the levels of the plurality of inverted amplification signals. A plurality of shift trigger unit for receiving a plurality of level shifting signals outputted from the level shifter to remove the pulse width of the plurality of level shifting signal by a predetermined width, respectively, and then inputs to the plurality of inverters, respectively. It is characterized by the configuration.

The Schmitt trigger unit connects the drain of the PMOS transistor to which the power is applied to the source with the drain of the first NMOS transistor, and the drain of the second NMOS transistor whose source is grounded to the source of the first NMOS transistor. An input signal is applied to the gates of the first and second NMOS transistors and a PMOS transistor, and a power supply voltage is applied to a drain at a common connection point of the drain of the PMOS transistor and the drain of the first NMOS transistor. Connected to the gate of the third enMOS transistor, and the source of the third enMOS transistor is connected to a common connection point of the source of the first enMOS transistor and the drain of the second enMOS transistor, and A signal may be generated at a common connection point between a drain and a drain of the first NMOS transistor.

Hereinafter, with reference to the accompanying drawings, the operation and effects of an embodiment of the TFT-CD gate driving circuit according to the present invention will be described in detail.

FIG. 3 is a block diagram showing an embodiment of the TFT-CD gate driving circuit of the present invention. As shown in FIG. 3, a pulse STV is input and synchronized with an external clock signal CPV. A shift register 10 for outputting second shifting signals IN1 and IN2; First and second level shifters (11) and (12) receiving the first and second shifting signals (IN1) and (IN2) of the shift register (10), respectively, and shifting them to a predetermined level; The first and second level shifting signals LVSFT_01 and LVSFT_02 of the first and second level shifters 11 and 12 are received, and pulse widths of the two signals LVSFT_01 and LVSFT_02 are predetermined. First and second Schmitt triggers 20 and 21 for removing the width; First and second inverter units 13 and 14 which receive the trigger signals SCH_01 and SCH_02 from the first and second Schmitt trigger units 20 and 21, respectively, and invert amplify them. ; The first and second inverted amplifier signals INVI_01 and INVI_02 of the first and second inverter units 13 and 14 are respectively input, and the first and second inverted amplifier signals INVI_01 and INVI_02 are respectively input. And the first and second output buffers 15 and 16 output to the outside according to the level of?).

FIG. 4 is a circuit diagram showing the configuration of the first and second Schmitt trigger units 20 and 21. As shown in FIG. 4, the drain of the PMOS transistor P123 to which the power supply VDD is applied to the source is shown. The drain of the first NMOS transistor N126 is connected, and the drain of the second NMOS transistor N124 whose source is grounded is connected to the source of the first NMOS transistor N126. An input signal IN is applied to the gates of the NMOS transistors N126, N124, and the PMOS transistor P123, and a drain of the PMOS transistor P123 and a drain of the first NMOS transistor N126 are provided. A common connection point of the first NMOS transistor N125 is connected to a gate of a third NMOS transistor N125 to which a power supply voltage VDD is applied to a drain, and a source of the third NMOS transistor N125 is connected to the first NMOS transistor N126. Is connected to the common connection point of the source of the and the drain of the second NMOS transistor (N124) And a signal OUT is generated at a common connection point of the drain of the PMOS transistor P123 and the drain of the first NMOS transistor N126, respectively, and thus illustrates an operation of the embodiment of the present invention. A detailed description will be given with reference to the timing chart of 5.

First, the shift register 10 receives a predetermined pulse signal STV and synchronizes it with an external clock signal CPV to form the first and second shifting signals IN1 and IN2 as shown in FIG. ) Are applied to the first and second level shifters 11 and 12, respectively.

Accordingly, the first and second level shifters 11 and 12 input first and second shifting signals IN1 and IN2 as shown in FIG. 5A of the shift register 10. And shifts it to a predetermined level and outputs the first and second level shifting signals LVSFT_01 and LVSFT_02 as shown in FIG. 5 (b), and at this time, the first and second Schmitt trigger unit 20, (21) receives the first and second level shifting signals LVSFT_01 and LVSFT_02 of the first and second level shifters 11 and 12, and then triggers the two signals LVSFT_01. ), The pulse widths of (LVSFT_02) are removed by a predetermined width, and the signals SCH_01 and (SCH_02) shown in FIG. 5C are applied to the first and second inverter units 13 and 14.

Here, the first and second Schmitt trigger unit 20, 21 has a transmission characteristic as shown in FIG. Is Has a value of, The first and second level shifting signals LVSFT_01 are equal to the threshold voltages of general inverters, and the rising edge times of the first and second Schmitt trigger units 20 and 21 having such transfer characteristics are very large. When the LVSFT_02 is applied, the widths of the output pulses SCH_01 and SCH_02 of the first and second Schmitt trigger units 20 and 21 are substantially greater than the widths of the input pulses LVSFT_01 and LVSFT_02. It is shortened by the rising edge time.

Next, the first and second inverter units 13 and 14 may include the trigger signals SCH_01 as shown in FIG. 5C of the first and second Schmitt trigger units 20 and 21, The SCH_02 is received and inverted and amplified and applied to the first and second output buffers 15 and 16, respectively.

Accordingly, the first and second output buffers 15 and 16 may receive the first and second inverted amplifier signals INVI_11 and INVI_12 from the first and second inverter units 13 and 14. When the first and second inverted amplification signals INVI_11 and INVI_12 have a predetermined level or more, the signals OUT10 and OUT20 as shown in FIG. 5D are externally output.

In other words, the first and second level shift signals LVSFT_01 and (LVSFT_02) of the first and second level shifters 11 and 12 may be applied to the first and second Schmitt trigger units 20 and ( Reducing the pulse width by using 21) reduces overlap of the final output signals OUT10 and OUT20 of adjacent channels.

As described in detail above, the present invention has an effect of improving the image quality by preventing the overlapping of the final output by reducing the width of the output waveform of the level shifter using the Schmitt trigger circuit.

Claims (2)

A shift register which receives a pulse and synchronizes it with an external clock signal and outputs a plurality of shifting signals accordingly; A plurality of level shifters which receive a plurality of shifting signals of the shift register and shift them to a predetermined level; A plurality of inverter units receiving a plurality of level shifting signals respectively output from the plurality of level shifters and inverting and amplifying them; In the TFT-LC gate driving circuit comprising a plurality of output buffers respectively receiving a plurality of inverted amplification signals outputted from the plurality of inverter units and outputting the plurality of inverted amplification signals to the outside according to the levels of the plurality of inverted amplification signals. By receiving a plurality of level shifting signals outputted from the level shifter, respectively, by triggering a shift, the plurality of level shifts are respectively input to the plurality of inverters after removing the pulse widths of the plurality of level shifting signals by a predetermined width. The TFT-LC gate driving circuit comprising a trigger unit. 2. The system of claim 1, wherein the Schmitt trigger unit connects a PMOS transistor in which an input signal is commonly applied to a gate, and first and second NMOS transistors in series between a power supply and a ground. A common connection point of the drain of the first enMOS transistor is connected to the output terminal, and a gate of the third enMOS transistor to which a power voltage is applied to the drain is connected, and a source of the third enMOS transistor is connected to the first enMOS transistor. And a TFT-PCD gate driving circuit configured to be connected to a common connection point of a source of the second transistor and a drain of the second NMOS transistor.