JP4353759B2 - Driving circuit - Google Patents

Description

  The present invention relates to a drive circuit, and more particularly, to a drive circuit that can be suitably used as an amplifier circuit for driving a capacitive load such as a liquid crystal display panel.

  In recent years, liquid-crystal displays (LCDs) using thin-film transistors (TFTs) as switching elements are becoming larger and larger. That is, an LCD having a 20-inch or larger screen has begun to be used for television (Television, TV) applications, and is replacing the conventional CRT (Cathode-Ray Tube). However, since the data line load of the TFT becomes heavier with the increase in size, there arises a problem that data cannot be written to the farthest end of the data line within one horizontal synchronization period. In order to cope with this problem, conventionally, a countermeasure (this is called a “double-side drive” method) in which source drivers (horizontal drivers) are arranged on the upper and lower sides of the liquid crystal panel and driven simultaneously is performed. It was. However, the “double-sided drive” method requires two horizontal drivers, which greatly increases the cost. Therefore, various improvements have been made over the prior art in order to ensure that data can be written to the farthest end of the drain line while maintaining the “one-side drive” method in which the source driver is arranged only on the upper or lower side of the liquid crystal panel. I came. An example is shown in FIGS.

(Conventional example 1)
FIG. 9 shows a schematic configuration of a conventional liquid crystal display device using the “single-side drive” method. As shown in FIG. 9, the liquid crystal display device 100 is a liquid crystal display device of a type that applies an analog data signal generated from digital video data to a liquid crystal panel, and includes a color liquid crystal panel 101, a control circuit 102, The gradation power source 103, a data electrode driving circuit (source driver) 104, and a scanning electrode driving circuit (gate driver) 105 are configured.

  The color liquid crystal panel 101 is an active matrix drive type color liquid crystal panel using TFTs as switching elements. The color liquid crystal panel 101 is provided with n scanning electrodes (gate lines) 106-1 to 106-n (n is a natural number of 2 or more) provided at predetermined intervals in the row direction and at predetermined intervals in the column direction. m (m is a natural number greater than or equal to 2) data electrodes (source lines) 107-1 to 107-m, and includes scan electrodes 106-1 to 106-n and data electrodes 107-1 to 107-m. A region in the vicinity of each intersection is referred to as a “pixel”. The number of pixels on the entire display screen is (n × m). The color liquid crystal panel 101 includes, for each pixel, a liquid crystal capacitor 108 that is equivalently a capacitive load, a common electrode 109, a TFT 110 for driving the corresponding liquid crystal capacitor 108, and data charges for one vertical synchronization period. An auxiliary capacitor (not shown) that accumulates during the period is arranged. At the time of driving, with the common potential Vcom applied to the common electrode 109, the analog data red signal, data green signal and data blue signal generated based on the red data, green data and blue data in the digital video data respectively In addition to being applied to the electrodes 107-1 to 107-m, a gate pulse (scanning signal) generated based on a horizontal synchronizing signal and a vertical synchronizing signal is applied to the scanning electrodes 106-1 to 106-n. As a result, characters, images, and the like are displayed in color on the display screen of the color liquid crystal panel 101.

  The control circuit 102 is composed of, for example, an ASIC (Application Specific Integrated Circuit), and a strobe signal, a dot clock, a horizontal scanning pulse based on an externally supplied clock, a horizontal synchronization signal and a vertical synchronization signal, a data enable signal, and the like. A polarity signal, a vertical scanning pulse, and the like are generated and supplied to the source driver 104 and the gate driver 105. The strobe signal is a signal having the same cycle as the horizontal synchronization signal. The dot clock has the same frequency as the clock or a frequency different from the clock, and is used to generate a sampling pulse from a horizontal scanning pulse in a shift register constituting the source driver 104, as will be described later. The horizontal scanning pulse is a signal having the same cycle as the horizontal synchronizing signal, but delayed by several clock pulses from the strobe signal. The polarity signal is a signal whose polarity is inverted every horizontal synchronization period (that is, every line), and is used for AC driving of the color liquid crystal panel 101. The polarity of the polarity signal is inverted every vertical synchronization period. The vertical scanning pulse is a signal having the same cycle as the vertical synchronizing signal.

  The gradation power source 103 includes a plurality of resistors connected in cascade between a reference voltage line and a ground line, and a plurality of voltage followers in which each input terminal is connected to a connection point of adjacent resistors. ing. The gradation power supply 103 amplifies and buffers the gradation voltage set for gamma conversion that appears at the connection point of the adjacent resistors, and supplies the amplified voltage to the source driver 104. Therefore, it is necessary to correct the analog video signal or the digital video data in order to obtain a reproduction image with good gradation with the gamma of the entire system being 1. This is called “gamma conversion”. In general, an analog video signal or digital video data is subjected to gamma conversion in order to match the characteristics (gamma characteristics) of the CRT display, that is, to have compatibility. Here, FIG. 10 shows an example of the relationship (gamma conversion characteristics) between 6-bit input data (displayed in hexadecimal (HEX)) and gradation voltages V0 to V4 and V5 to V9.

  As shown in FIG. 9, the source driver 104 is roughly composed of a video data processing circuit 111, a digital / analog converter (DAC) 112, and m output circuits 113-1 to 113-m. Although not shown, the video data processing circuit 111 is generally composed of a shift register, a data register, a latch, and a level shifter. The shift register is a serial-in / parallel-out shift register composed of a plurality of delay flip-flops. The shift register performs a shift operation for shifting the horizontal scanning pulse supplied from the control circuit 2 in synchronization with the dot clock supplied from the control circuit 2 and outputs a parallel sampling pulse of a plurality of bits. The data register takes in red data, green data, and blue data of digital video data supplied from the outside as display data in synchronization with the sampling pulse supplied from the shift register, and supplies it to the latch. The latch captures the display data supplied from the data register in synchronization with the rise of the strobe signal supplied from the control circuit 2, and then captures until the strobe signal is supplied next, that is, for one horizontal synchronization period. Hold display data. The level shifter converts the voltage of the output data of the latch and outputs it as voltage conversion display data.

  For the voltage conversion display data supplied from the video data processing circuit 111, the D / A converter 112 applies a set of gradation voltages V0 to V4 or a set of gradation voltages V5 to V9 ( By applying the above gamma correction based on FIG. Then, the corrected red data, corrected green data, and corrected blue data subjected to gamma correction are converted into analog data red signals, data green signals, and data blue signals and supplied to the corresponding output circuits 113-1 to 113-m. To do.

  Since all of the output circuits 113-1 to 113-m have the same configuration, the configuration of the output circuit 113-1 is shown in FIG. 11. As is apparent from FIG. 11, the output circuit 113-1 includes voltage followers 114a and 114b and switches 115a and 115b.

  As shown in FIG. 12, the voltage follower 114a includes N-channel MOS transistors MN11 and MN12, P-channel MOS transistors MP11, MP12 and MP13, constant current sources CI11 and CI12, and a capacitor C11. The amplifier is configured by an amplifier, and a positive data signal supplied from the D / A converter 112 is amplified and buffered and output. As shown in FIG. 13, the voltage follower 114b includes P-channel MOS transistors MP14 and MP15, N-channel MOS transistors MN13, MN14 and MN15, constant current sources CI13 and CI14, and a capacitor A12. An amplifier is used to amplify and buffer the negative data signal supplied from the D / A converter 112 and output it.

  The switch 115 a is turned on when the polarity signal POL supplied from the control circuit 102 is “H” level, and the positive polarity data signal S supplied from the voltage follower 114 a is supplied to the corresponding data electrode of the color liquid crystal panel 101. Applied to 107-1. The switch 115b is turned ON when the polarity signal POL supplied from the control circuit 102 is at "L" level, and the negative polarity data signal S supplied from the voltage follower 114b is applied to the corresponding data electrode of the color liquid crystal panel 101. Applied to 107-1.

  The gate driver 105 sequentially generates gate pulses in synchronization with the timing of the vertical scanning pulses supplied from the control circuit 102, and sequentially applies them to the corresponding scanning electrodes 106-1 to 106-n of the color liquid crystal panel 101. Scan electrodes 106-1 to 106-n are scanned once within one vertical synchronization period.

  Next, the operation of the conventional liquid crystal display device 100 having the above configuration will be described with reference to the timing chart shown in FIG.

  In FIG. 14, TF indicates one frame period, and TH indicates one horizontal synchronization period. Here, the “dot inversion driving method” is adopted as a driving method for driving the color liquid crystal panel 101. In the “dot inversion driving method”, the data electrodes 107-1 to 107-1 are arranged so that the potential (polarity) to be applied to the display electrode can be inverted for each dot with reference to the common potential Vcom applied to the common electrode 109. The polarity of the data signal applied to 107-m is controlled. In the “dot inversion driving method”, in general, when a voltage of the same polarity is continuously applied to the liquid crystal cell of the liquid crystal panel 101, a phenomenon of “burn-in”, in which characters and the like remain on the screen even when the power is turned off, occurs. Therefore, it is conventionally employed to prevent the “burn-in”. Even if the polarity of the voltage applied to the liquid crystal cell of the liquid crystal panel 101 is reversed, the transmittance characteristic of the liquid crystal cell is hardly changed. Therefore, a gradation voltage having the same voltage value is applied in both cases of positive polarity and negative polarity. Generally adopted.

  A clock VCK shown in FIG. 14 (1) is a clock used in the gate driver 105. The gate driver 5 synchronizes with each pulse P1, P2,..., Pn of the clock VCK, as shown in FIGS. 14 (2), (3) and (4). ) VG1, VG2,..., VGn are sequentially generated and sequentially applied to the corresponding scanning electrodes 106-1 to 106-n of the color liquid crystal panel 101. As shown in FIGS. 14 (5) and (6), the source driver 104 receives data red signals from the output circuits 113-1 to 113-n several μsec after the generation of the gate pulses VG1, VG2,. Data green signal and data blue signal are output. 14 (5) shows the voltage waveform of the data signal output from the even-numbered output circuit from the left in FIG. 9, and FIG. 14 (6) is output from the odd-numbered output circuit from the left in FIG. It is a voltage waveform of a data signal.

(Conventional example 2)
Instead of the circuit configurations shown in FIGS. 12 and 13 for the voltage followers 114a and 114b in FIG. 11, the circuit configuration shown in FIG. 15 may be used. FIG. 15 is substantially equivalent to the circuit configuration disclosed in Japanese Patent Laid-Open No. 2000-338461.

  The circuit shown in FIG. 15 includes a PMOS source follower output circuit 116a, an NMOS source follower output circuit 116b, a precharge circuit 117, and switches S21 and S22. The PMOS source follower output circuit 116a includes P-channel MOS transistors (PMOS transistors) MP26 and MP27, and constant current sources CI21, CI22 and CI23. The NMOS source follower output circuit 116b includes N-channel MOS transistors (NMOS transistors) MN26 and MN27, and constant current sources CI24, CI25 and CI26. The precharge circuit 117 includes precharge drive switches S23 and S24. The switches S21 and S22 are used to switch between the PMOS source follower output circuit 116a and the NMOS source follower output circuit 116b.

  Next, the operation of the voltage follower shown in FIG. 15 will be described with reference to FIG. FIG. 16A shows the output waveform during the positive polarity period, and is when the PMOS source follower output circuit 116a is used by the switches S21 and S22. FIG. 16B shows an output waveform during a negative polarity period, and is when the NMOS source follower output circuit 116b is used by the switches S21 and S22.

  In general, a source follower circuit has only a one-way driving capability. For example, the source follower circuit constituted by the PMOS transistor MP27 in the PMOS source follower output circuit 116a has a sufficient capacity to sink current, but does not have a capacity to discharge current, and the constant current source CI23 connected to the PMOS transistor MP27. There is only the ability to discharge the current. Usually, since the current value of the constant current source CI23 is set to be very small, the current discharge driving capability is very small. Similarly, the source follower circuit constituted by the NMOS transistor MN27 in the NMOS source follower output circuit 116b has a sufficient capacity to discharge current, but does not have a capacity to absorb current, and the constant current source CI26 connected to the NMOS transistor MN27. It has only the ability to absorb a small current. For these reasons, in the voltage follower shown in FIG. 15, as shown in FIG. 16, precharge is performed using the first part of one horizontal synchronization period, and thereafter the capability of the source follower output circuit 116 a or 116 b. The operation of returning to the desired potential is performed.

  When the precharge is not performed, the load is driven with a constant current having a small value, so that the rising characteristic is extremely deteriorated in the case of the source follower output circuit 116a, and the falling characteristic is extremely deteriorated in the case of the source follower output circuit 116b. Therefore, this problem is avoided by combining the source follower circuits 116a and 116b with the precharge circuit 117.

(Conventional example 3)
Further, a development of the circuit of FIG. 15 is disclosed in the aforementioned Japanese Patent Laid-Open Nos. 2000-338461 and 20003-22055 (not shown). These are connected in one source follower type with one conductivity type transistor between one power supply line and the output terminal, and another conductivity type transistor between the other power supply line and the same output terminal. A switch is provided for each of the transistors, and one source follower circuit is activated according to the polarity of the input signal.

JP 2000-338461 A JP 2003-22055 A

  The conventional example 1 shown in FIGS. 9 to 14 has the following problems.

  That is, since there is usually a difference in offset voltage between the voltage follower 114a of FIG. 12 that operates at the positive polarity and the voltage follower 114b of FIG. 13 that operates at the negative polarity, a so-called output deviation occurs. There is a problem that image quality deterioration phenomenon such as “vertical stripes” occurs.

  In the conventional example 2 shown in FIGS. 15 to 16, the PMOS source follower output circuit 116 a and the NMOS source follower output circuit 116 b are switched and used in accordance with the polarity of the input signal. There is a problem that image quality deteriorates due to output deviation. Further, as described above, when the precharge is not performed, the load is driven with a constant current having a small value, so that the rising characteristics and the falling characteristics are extremely deteriorated. Therefore, the conventional example 2 also has a problem that it does not operate normally if there is no precharge operation at any output level.

  The drive circuit of Conventional Example 3 also has a problem that the current drive capability is very small and does not operate normally unless precharged. In addition, since the two source follower circuits are selectively operated using the switches, there is a problem that an output deviation caused by the offset voltage is generated and the image quality is deteriorated.

  A main object of the present invention is to provide a drive circuit having an increased drive capability while reducing an output deviation.

(1) The drive circuit of the present invention
An amplifier circuit for receiving an input signal;
Second power sources of different conductivity types are connected in series between the two power supply terminals in a form in which the respective sources are connected to the output point, and push-pull drive the output point in response to the output signal of the amplifier circuit. A first and a second transistor ;
A first switch provided in parallel with the first transistor between one of the two power supply terminals and the output point;
A second switch provided in parallel with the second transistor between the other of the two power supply terminals and the output point;
Provided in a path connecting the output terminal of the drive circuit and the output point, and when the precharge is performed on the output point, the path is blocked, and when the precharge is not performed, the path is connected. A third switch controlled by
The first and second transistors are push-pull driven based on a class B operation, and a signal at the output point is fed back to the amplifier circuit.

  (2) In the drive circuit according to the present invention, the output side of the amplifier circuit is connected in series between two power supply terminals in a form in which the sources are connected to the output point, and responds to the output signal of the amplifier circuit. Thus, the first and second transistors of different conductivity types that push-pull drive the output point. Therefore, on the output side of the amplifier circuit, the first transistor of one conductivity type has a source follower configuration, and the second transistor of the other conductivity type has the same source follower configuration. The first and second transistors push-pull drive the output point in response to the output signal of the amplifier circuit. For this reason, the output deviation resulting from an offset voltage can be reduced. In addition, the risk of image quality degradation due to output deviation is reduced.

  Furthermore, since the signal at the output point is fed back to the amplifier circuit, the driving capability of the first and second transistors can be used effectively. Therefore, the driving capability can be increased.

In the driving circuit of the present invention , the first and second transistors are push-pull driven based on the class B operation, so that power consumption can be reduced .

Also, the between the other and the output point of the first switch that is provided in parallel with the first transistor, the two power supply terminals between one and the output point of the two power supply terminals And a second switch provided in parallel with the second transistor, so that the first or second switch is selectively selected within a range in which the first and second transistors cannot perform a source follower operation. By turning it ON, precharging is performed on the output point. As a result, it expands the range of high driving ability can be obtained, which enables high speed operation.

Also, provided in a path connecting the output terminal of the drive circuit and the output point, the path is cut off when the output point is precharged, and the path is connected when the precharge is not performed. Since the third switch controlled to do so is provided, the output point can be separated from the output terminal of the drive circuit by the third switch when precharging is performed . Therefore, it is possible to prevent the pre-charge affects the output point.

(3) In a preferred example of the drive circuit of the present invention, the drive circuit further includes a determination circuit that examines the input signal and determines whether precharge is necessary. In this example, there is an advantage that the precharge operation can be surely performed when necessary. This determination circuit preferably determines the upper n bits (n is a positive integer) of the input signal to determine whether precharge is necessary. For example, when the upper n bits of the input signal are determined and it is determined that the input signal has a predetermined gradation, it is determined that precharge is necessary.

In another preferable example of the drive circuit of the present invention, a fourth switch and a first constant current source connected in series with each other are connected in parallel with the first transistor between one of the two power supply terminals and the output point. in conjunction provided, the fifth switch and the second constant current source connected in series with each other is provided in parallel with the second transistor between the other and the output point of the two power supply terminals , the fourth switch, the is oN · OFF controlled in almost synchronism with the oN · OFF of the first transistor, the fifth switch is oN · OFF controlled in almost synchronism with the oN · OFF of the second transistor The In this example, there is an advantage that the output dynamic range can be further expanded and the driving capability can be further improved. In this example, it is preferable that the fourth switch, the first constant current source, the fifth switch, and the second constant current source are used for flowing an output idling current. This has the advantage that the gate potential of the first and second transistors can be stabilized when the class B push-pull operation is performed and the output current becomes zero.

  According to the drive circuit of the present invention, it is possible to increase the drive capability while reducing the output deviation.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a driving circuit according to the invention will be described in detail with reference to the accompanying drawings. In this embodiment, the present invention is applied to an LCD driving amplifier circuit.

  FIG. 1 is a circuit diagram showing a configuration of an LCD driving amplifier circuit 10 according to an embodiment of the present invention. FIG. 2 is a functional block diagram showing the configuration of the LCD drive circuit 20 configured using the LCD drive amplifier circuit 10.

  In FIG. 1, an LCD drive amplifier circuit 10 according to an embodiment of the present invention includes a differential amplifier 11, an output unit 12, an input terminal Tin, and an output terminal Tout. A load (liquid crystal capacitance of the liquid crystal panel) 60 is connected to the output terminal Tout.

The differential amplifying unit 11 is composed of an operational amplifier (op-amp), receives the analog input signal voltage Vin applied from the input terminal Tin at the non-inverted (+ side) input terminal, and feeds back the output voltage. Vout is received at the inverting (-side) input terminal, and both signal voltages are differentially amplified and output. The output signal Vina of the differential amplifying unit 11 is supplied to the output unit 12. Since the configuration and operation of the differential amplifying unit 11 are well known and do not have a direct relationship with the present invention, a detailed description thereof will be omitted.

  The output unit 12 includes an N-channel MOS transistor M1 having a source follower configuration, a P-channel MOS transistor M2 having a source follower configuration, and a constant current source CI3. The gates of both transistors M1 and M2 are connected in common to the output terminal of the differential amplifier 11. The sources of both transistors M1 and M2 are commonly connected to a node (output point) P. Since the output point P is connected to the inverting input terminal of the differential amplifier 11, the signal (Vout) at the output point P is fed back to the inverting input terminal of the differential amplifier 11. The drain of the transistor M1 is connected to a power supply line (power supply terminal) to which the power supply voltage VDD is applied, and the drain of the transistor M2 is connected to a ground line (ground terminal) held at the ground potential GND. . The constant current source CI3 is connected between the power supply line and the gate of the transistor M1 (and M2). The constant current source CI13 is a current source for controlling the output current of the differential amplifying unit 11.

  Needless to say, instead of the ground line (ground terminal) held at the ground potential GND, another power line (power terminal) to which the power supply voltage VSS is applied may be used.

  As described above, in the circuit configuration of FIG. 1, the two transistors M1 and M2 having different conductivity types are each configured as a source follower that performs class B operation, and the transistors M1 and M2 are connected to the power supply line and the ground line. They are connected in series with each other. Then, the output signal of the differential amplifier 11 is applied in common to the gates of the transistors M1 and M2, and the output of the source follower circuit block is extracted from the sources (output points P) of the transistors M1 and M2. In other words, two transistors M1 and M2 having different conductivity types are connected in series between two power supply terminals (that is, between a power supply line and a ground line) as a source follower configuration, and both transistors M1 And M2 are connected in common (ie, the output point P) with class B push-pull drive. Therefore, the source follower block performs class B push-pull amplification and constitutes a complementary output. As a result, sufficient current discharging / sucking capability can be obtained. Further, since it has a source follower configuration, the output impedance is relatively low, and since feedback is further applied, the output impedance is further reduced, and excellent characteristics as this type of amplifier (buffer) can be obtained.

  The output unit 12 further includes two constant current sources CI1 and CI2 and five switches S1, S2, S3, S4 and S5. The switch S1 is provided between the node Q and the node R, and opens and closes a path between the node (that is, the output point of the source follower circuit block) P and the output terminal Tout. The constant current source CI1 is a discharge type, and one end thereof is connected to the power supply line, and the other end is connected to one end of the switch S2. The other end of the switch S2 is connected to the node Q. Therefore, the current from the constant current source CI1 is supplied to the node Q only when the switch S2 is turned on. On the other hand, the constant current source CI2 is a suction type, and one end thereof is connected to the ground line, and the other end is connected to one end of the switch S3. The other end of the switch S3 is connected to the node Q. Therefore, current is sucked from the node Q into the constant current source CI2 only when the switch S3 is turned on. The constant current sources CI1 and CI2 and the switches S3 and S4 serve to widen the output dynamic range of the LCD driving amplifier circuit 10.

  The switch S4 is connected between the power supply line and the node R. The switch S5 is connected between the ground line and the node R. Both switches S4 and S5 are for precharge control, and are turned on when necessary to precharge (overdrive) the output terminal Tout.

  The output obtaining terminal Tout is connected to the inverting input terminal of the differential amplifier 11 via the node R, the switch S1, the node Q, and the node (output point) P, and the output signal voltage Vout (the signal at the output point P). Voltage) is fed back to the input side of the LCD driving amplifier circuit 10.

  FIG. 2 shows a configuration of the LCD drive circuit 20 according to the present embodiment using the LCD drive amplifier circuit 10 having the above configuration.

  As is apparent from FIG. 2, a D / A converter 21 for converting the digital input signal voltage Vdin into an analog signal to generate the analog input signal voltage Vin is provided on the input side of the LCD driving amplifier circuit 10 in FIG. Yes. In addition, an upper n-bit determination circuit 22 and a switch control circuit 23 are provided to control the opening and closing of the switches S1 to S5.

  The upper n-bit determination circuit 22 checks the upper n bits of the digital input signal Vdin to determine whether precharge (overdrive) is necessary, and sends a signal corresponding to the determination result to the switch control circuit 23. For example, by examining the upper 3 bits of the digital input signal Vdin, it can be determined whether or not it is within the precharge (overdrive) necessary range shown in FIG. Further, for example, the precharge is performed only when the gradation output is in the range of 0 to 1 volt or in the range of (VDD-1) to VDD volt, and otherwise, the normal operation without precharge is performed. Can be.

  The switch control circuit 23 controls the opening and closing of the switches S1 to S5 so as to obtain the waveforms shown in FIGS. 5 and 6 according to the content of the determination result signal sent from the upper n-bit determination circuit 22.

  As can be understood from the above description, in the configuration of the LCD driving amplifier circuit 10 shown in FIG. 1, the differential amplifier 11 that receives the input signal Vin and the output point P are connected to each other in the form of two. Transistors M1 and M2 having different conductivity types are connected in series between the two power supply terminals VDD and GND and push-pull drive the output point P in response to the output signal Vina of the differential amplifier 11. ing. The signal at the output point P is fed back to the differential amplifying unit 11. Therefore, in this amplifier circuit 11, on the output side of the differential amplifier 11, the one-conductivity type transistor M1 has a source follower configuration, and the other-conductivity type transistor M2 also has a source follower configuration. The transistors M1 and M2 push-pull drive the output point P in response to the output signal Vina of the differential amplifying unit 11. For this reason, the output deviation resulting from an offset voltage can be reduced. In addition, the risk of image quality degradation due to output deviation is reduced.

  Furthermore, since the signal at the output point P is fed back to the differential amplifier 11, the driving capability of the two transistors M1 and M2 can be used effectively. Therefore, the driving capability of the LCD driving amplifier circuit 10 can be increased.

  Transistors M1 and M2 are preferably push-pull driven based on class B operation. This is because the power consumption can be reduced by performing the class B operation. However, the present invention can be practiced otherwise.

  The switches S4 and S5 are precharge switches, which are turned on when it is determined that precharging is required for the output terminal Tout, and are turned off when it is determined that precharging is not necessary. The switches S4 and S5 are not necessarily required for the implementation of the present invention. However, since precharge is necessary in actual use situations, both switches S4 and S5 are usually provided together as in this embodiment. The switches S4 and S5 are precharged to the output point P (that is, the output terminal Tout) by selectively turning on the switches S4 and S5 within a range where the transistors M1 and M2 cannot perform the source follower operation. Is called. For this reason, there is an advantage that the range in which high driving capability can be obtained can be expanded and the operation speed can be increased.

  Since the switches S2 and S3 and the constant current sources CI1 and CI2 are for expanding the output dynamic range, they are not necessarily required to implement the present invention. However, in an actual usage situation, it is preferable that the output dynamic range is as wide as possible. Therefore, it is preferable to provide the output dynamic range as in this embodiment.

  The switch S1 is provided in a path connecting the output terminal Tout of the LCD driving amplifier circuit 10 and the output point P. When the precharge is performed on the output point P, the switch S1 is cut off and the precharge is performed. It is controlled to connect the path when it is not performed. The switch S1 is not always necessary for the implementation of the present invention. However, it is preferably provided as in this embodiment. This is because the output point P is separated from the output terminal Tout of the drive circuit 10 by the switch S1 when precharging is performed, so that the precharge can be prevented from affecting the output point P.

  Next, operations of the LCD driving amplifier circuit 10 having the configuration of FIG. 1 and the LCD driving circuit 20 having the configuration of FIG. 2 will be described.

  In the LCD driving amplifier circuit 10, since the two source follower circuits composed of the transistors M1 and M2 are in the feedback loop, the voltage at the output point P always operates to be equal to the input voltage Vin. As a result, the amplified output voltage Vina of the differential amplifying unit 11 obtained by amplifying the input signal voltage Vin is (Vin + VGS1) or (Vin−VGS2). However, VGS1 is a gate-source voltage of the transistor M1, and VGS2 is a gate-source voltage of the transistor M2. In other words, the inverting input terminal (that is, the output point P) of the differential amplifier circuit 10 and the input terminal Tin are in an imaginary short-circuit relationship, and therefore the circuit 10 is configured such that the voltage at the output point P is always equal to the input voltage Vin. It works to be.

  In the AC drive for the liquid crystal capacitance 60 of the liquid crystal panel as a load, the transistor M1 is turned off (cut off) and the transistor M2 is turned on (active) when the polarity of the input signal voltage Vin is positive, and the potential at the output point P Becomes equal to the input voltage Vin. As a result, the amplified output voltage Vina of the differential amplifier 11 is (Vin−VGS2). In the period when the polarity of the input signal voltage Vin is negative, this is reversed, the transistor M1 is turned on (active state), the transistor M2 is turned off (cut off state), and the potential at the point P becomes equal to the input voltage Vin. As a result, the amplified output voltage Vina of the differential amplifier 11 is (Vin + VGS1). The source follower circuit block (transistors M1 and M2 and current source CI3) of the LCD driving amplifier circuit 10 thus performs a source follower operation in a push-pull manner.

  If the amplified input signal voltage Vina is within a range in which the source follower circuit block including the transistors M1 and M2 can be driven, class B push-pull amplification is performed as described above. For this reason, high drive capability is obtained with low output impedance.

Specifically speaking, the range in which the source follower circuit block can be driven is as follows:
VDD- (VGS1 + VDS (sat)) to VGS2 + VDS (sat)
It is. Here, VDS (sat) is a boundary voltage between the triode region and the pentode region of the transistor constituting the previous stage or current source CI3.

  Outside this range, the source follower circuit block cannot perform the source follower operation, so that the load 60 can be driven by precharging the output terminal Tout. That is, in the range close to the power supply voltage VDD, the potential of the output portion 12 of the LCD driving amplifier circuit 10, that is, the output point P, is once raised to the power supply voltage VDD by precharging, whereby the P-channel transistor M2 can be operated. . This is possible because the transistor M2 has no ability to discharge current but has the ability to draw current. The same applies to a range close to the ground potential GND. In other words, the N channel transistor M1 can be operated by once reducing the potential of the output portion 12, that is, the point P of the LCD driving amplifier circuit 10 to the ground potential GND by precharging. This is possible because the transistor M1 has no ability to sink current but has the ability to discharge current. In this way, it is possible to drive in the entire range from the power supply voltage VDD to the ground potential GND. 3 and 4 conceptually illustrate this situation.

  Next, the above operation will be described in more detail with reference to FIGS.

  Hereinafter, the case where precharge is not required and the case where precharge is required will be described separately, but whether or not precharge is required is determined by the upper n-bit determination circuit 22.

(When precharge is not required)
When the precharge is not required, as shown in FIG. 5, the switch S1 is always turned on (closed) in order to enable the output voltage Vout to be output, and the switches S4 and S5 are prevented from being precharged. Is always OFF (open). In addition, since the LCD driving amplifier circuit 10 performs class B push-pull amplification, in order to stabilize the gate potential of the transistors M1 and M2 of the source follower circuit block when the output current becomes zero, the switch S2 or It is preferable that S3 is selectively turned on to pass an output idling current. This will be described with reference to the timing chart of FIG. 5. During the period in which the polarity of the input voltage Vin is positive (time t1 to t2) (ie, one horizontal synchronization period = 1H), the switch S2 is turned on, the switch S3 is turned off, and the switch S1 Is turned ON, and a constant current from the constant current source CI1 is caused to flow toward the output terminal Tout. During a period in which the polarity of the input voltage Vin is negative (time t2 to t3) (that is, the next one horizontal synchronization period), the switch S2 is turned off, the switch S3 is turned on, and the switch S1 is turned on. Suction is performed from the output terminal Tout. The waveform of the output voltage Vout in this case is as shown in FIG. In FIG. 3B, the solid line is the load near-end waveform, that is, the waveform at the end close to the load 60, and the broken line is the load far-end waveform, that is, the waveform at the end far from the load 60.

  Even when the precharge is not required, the precharge may be performed in order to increase the data writing speed to the liquid crystal panel. Further, VDD2 in FIG. 5 is an amplitude of a control voltage for controlling each switch.

(When precharge is required)
Even when the precharge is required, the LCD drive amplifier circuit 10 performs the class B push-pull amplification as in the case where the precharge is not required, so that the source follower circuit block when the output current becomes zero In order to stabilize the gate potentials of the transistors M1 and M2, it is necessary to selectively turn on the switch S2 or S3 to allow the output idling current to flow. However, since precharging is performed for a limited time, a little ingenuity is required for the control method when precharging is required.

  In the present embodiment, in order to perform precharge with a limited time, precharge is performed using the first part of the time of each horizontal synchronization period. This will be explained with reference to the timing chart of FIG. 6. The first part of the period in which the polarity of the input voltage Vin is positive (time t11 to t12) (that is, the first part of one horizontal synchronization period) is output with the switch S1 turned OFF. The terminal Tout is disconnected from the source follower circuit block (output point P), and the switch S4 is turned on to apply the power supply voltage VDD to the output terminal Tout, thereby precharging the output terminal Tout. Thereby, since the power supply voltage VDD is directly applied to the output terminal Tout, the output voltage Vout is raised to VDD. After that, at time t12, the switch S4 is turned off to stop precharging, and the switch S1 is turned on to connect the output terminal Tout to the source follower circuit block (output point P). Signal voltage) appears at the output terminal Tout. As a result, the output voltage of the block is output to the output terminal Tout (that is, returned to a desired voltage). This return operation is performed by the P-channel transistor M2 having a source follower configuration, and is continued during the remaining portion (time t12 to t13) of the positive period of the input voltage Vin.

  During the period when the polarity of the input voltage Vin is positive (time t11 to t13), the switch S2 is held ON (the switch S3 is held OFF). This is because the transistor M2 is biased by the constant current source CI1 so that the output voltage recovery operation is sufficiently performed.

  On the other hand, during the first precharge period (time t13 to t14) in which the polarity of the input voltage Vin is negative (that is, the next one horizontal synchronization period), the switch S1 is turned OFF and the output terminal Tout is connected to the source follower circuit block (output point In addition to being disconnected from P), the switch S5 is turned ON and the ground potential GND is applied to the output terminal Tout, thereby precharging the output terminal Tout. As a result, since the ground potential GND is directly applied to the output terminal Tout, the output voltage Vout is lowered to GND. After that, at time t14, the switch S5 is turned off to stop precharging, and the switch S1 is turned on to connect the output terminal Tout to the source follower circuit block (output point P). Signal voltage) appears at the output terminal Tout. As a result, the output voltage of the block is output to the output terminal Tout (that is, returned to a desired voltage). This return operation is performed by the N-channel transistor M1 having the source follower configuration, and is continued during the remaining portion (time t14 to t15) of the negative period of the input voltage Vin.

  During a period in which the polarity of the input voltage Vin is negative (time t13 to t15), the switch S2 is held OFF (the switch S3 is held ON). This is because the transistor M1 is biased by the constant current source CI2 so that the output voltage recovery operation is sufficiently performed. The waveform of the output voltage Vout in this case is as shown in FIG. In FIG. 3A, the solid line is the load near end waveform, and the broken line is the load far end waveform.

  As can be seen from the waveform in FIG. 3A, the waveform at the near end, that is, at a location close to the LCD driving amplifier circuit 10 (shown by a solid line) appears to have a protrusion at the beginning of each horizontal synchronization period. The final value arrival time is shorter than before, and higher speed writing can be realized. Further, the waveform (indicated by a broken line) at the far end, that is, at a location far from the LCD driving amplifier circuit 10 is dull according to the time constant of the data line. However, even in this case, the final value arrival time is shorter than before, and higher speed writing can be realized.

  As can be seen from FIG. 5, the strobe signal STB falls at times t1, t2, and t3, and the polarity of the switch S2 in the horizontal synchronization period starting from these times is opposite to the polarity of the polarity signal POL at those times. It has become. In addition, the polarity of the switch S3 in the horizontal synchronization period is the same as the polarity of the polarity signal POL at those times. The same applies to FIG.

  The above-described control of the switches S1 to S5 is performed by the switch control circuit 23 (see FIG. 2). An example of a circuit configuration for realizing the control of the switches S2 and S3 is shown in FIG.

  7 includes a flip-flop circuit 31 that takes in the polarity signal POL at the falling edge of the strobe signal STB, an inverter circuit 32 that inverts the polarity of the output of the flip-flop (F / F) circuit 31, and an inverter circuit. A level shifter (L / S) circuit 33 that shifts the voltage level of the output of 32 and a level shifter circuit 34 that shifts the voltage level of the output of the flip-flop circuit 31 are provided. The level shifter circuits 33 and 34 are circuits for transmitting a signal from a low-voltage system logic voltage (for example, 3.3 V) to a high-voltage system voltage (for example, 10 V). It is obvious that the operation of the switches S2 and S3 according to the waveform diagrams shown in FIGS.

  Another configuration example of the switch control circuit 23 (see FIG. 2) is shown in FIG. FIG. 8 is a configuration diagram of the switch control circuit 40 that controls ON and OFF of the switches S1 to S5. In this example, an n-input AND gate 46 is used as the upper n-bit determination circuit 22 (see FIG. 2).

The polarity signal POL and the inverted signal of the strobe signal STB are input to the data terminal D and the latch terminal φ of the D flip-flop 41, respectively. The output signals output from the two data terminals Q and Q bar of the D flip-flop 41 are output via the level shifters 43 and 42 and become control signals for the switches S3 and S2, respectively. Referring to FIG. 5, the D flip-flop 41 holds the logical state (L) of the polarity signal POL at the falling edge (time t1) of the strobe signal STB until the next falling edge (time t2) of the strobe signal STB. Subsequently, the logic state (H) of the polarity signal POL at the fall of the strobe signal STB (time t2) is held until the next fall (time t3) of the strobe signal STB. Therefore, the waveforms of the control signals for the switches S2 and S3 are as shown in FIG. (The same applies to FIG. 6.)
The strobe signal STB is input to the set terminal S of the flip-flop 51 and the data terminal P of the down counter 53. The output signal of the two-input AND gate 52 is input to the clock terminal CL of the down counter 53. An output signal output from the output terminal BL of the down counter 53 is input to the reset terminal R of the flip-flop 51. The output signal output from the output terminal Q of the flip-flop 51 is input to one input terminal of the two-input AND gate 52 and also input to the three-input AND gates 47 and 48, respectively. A dot clock is input to the other input terminal of the two-input AND gate 52. Output signals output from the two data terminals Q and Q of the D flip-flop 41 are input to the other two input terminals of the three-input AND gates 47 and 48, respectively. Output signals output from the output terminals of the three-input AND gates 47 and 48 are output via level shifters 49 and 50, and become control signals for the switches S4 and S5, respectively.

  The preset value input circuit 54 is used to input a preset value to the down counter 53. The down counter 53 counts down the input signal to the data input terminal P from the preset value to 0 in synchronization with the input signal to the clock input terminal CL, and outputs a signal in the logic state corresponding to the count value. Output sequentially. The preset value is set so that a desired precharge period can be obtained when all the upper n bits of the digital input signal are 1.

  Referring to FIG. 6, the output signals output from the data terminals Q and Q bar of the D flip-flop 41 have the same waveforms as the control signals of the switches S2 and S3, respectively. That is, the output signal output from the data terminal Q is in the logic state H during the time t11 to t13 and is in the logic state L during the time t13 to t15. The output signal output from the data terminal Q bar is in the logic state L during the time t11 to t13 and is in the logic state H during the time t13 to t15. On the other hand, the output signal output from the output terminal Q of the flip-flop 51 is in a logic state obtained by inverting the logic state of the strobe signal STB until the signal of the logic state H is input from the down counter 53 to the reset terminal R. Retained. That is, the logic state H is until a time t11 slightly before the time t11, and the logic state L is between the time t11 and the time t13 thereafter. The output signal output from the output terminal of the n-input AND gate 46 is in the logic state H when the upper n bits of the digital input signal are all 1. As a result, the waveforms of the control signals for the switches S4 and S5 are as shown in FIG.

  That is, if the upper n bits of the digital input signal are all 1 and the output signal of the n-input AND gate 46 is in the logic state H between times t11 and t12, the data terminal Q bar of the D flip-flop 41 is The output signal output from the output terminal Q of the flip-flop 51 is the strobe signal STB until the signal of the logic state H is input from the down counter 53 to the reset terminal R. Therefore, the logic state is H. Therefore, the output signal of the three-input AND gate 43 is in the logic state H at times t11 to t12. If all the higher-order n bits of the digital input signal are not 1 during the time t12 to t13, the output signal of the three-input AND gate 43 becomes the logic state L. As a result, the waveform of the control signal of the switch S4 between times t11 and t13 is as shown in FIG.

  Since the output signal output from the data terminal Q of the D flip-flop 41 is held in the logic state L during times t11 to t13, the output signal of the three-input AND gate 43 is held in the logic state L during this time. . Therefore, the waveform of the control signal of the switch S5 is as shown in FIG.

  The control signal of the switch S5 between times t11 and t15 has the waveform shown in FIG. 6 for the same reason as in the case of the switch S4.

  The output signals of the three-input AND gates 47 and 48 have the same waveforms as the control signals of the switches S4 and S5, respectively. Since the output signal of the NOR circuit 44 taken out via the level shifter 45 is the control signal for the switch S1, the control signal for the switch S1 when one of the logical states of the control signals for the switches S4 and S5 is H. Becomes the logic state L. Therefore, the waveform is as shown in FIG.

  As described above in detail, in the LCD drive amplifier circuit 10 according to the present embodiment, the N-channel transistor M1 and the P-channel M2 arranged on the output side of the differential amplifier 11 are connected to each other at the output point P. Connected in series between two power supply terminals (here, between a power supply terminal and a ground terminal) and push-pull drive the output point P in response to the output signal Vina of the differential amplifier 11. . On the output side of the differential amplifier 11, each of the transistors M1 and M2 has a source follower configuration. The transistors M1 and M2 push-pull drive the output point P in response to the output signal Vina of the differential amplifying unit 11. Therefore, the output deviation due to the offset voltage can be reduced, and the risk of image quality degradation caused thereby is reduced. In this embodiment, the transistors M1 and M2 perform a push-pull operation based on the class B operation, so that power consumption can be reduced.

  Furthermore, since the signal at the output point P is fed back to the inverting input terminal of the differential amplifier 11, the driving capability of the transistors M1 and M2 can be used effectively. Therefore, the driving capability can be increased.

  Further, the upper n-bit determination circuit 22 checks the upper n bits of the digital input signal Vdin to determine whether precharge (overdrive) is necessary, and sends a signal corresponding to the determination result to the switch control circuit 23. Since the switch control circuit 23 controls ON / OFF (open / close) of the switches S1 to S5 according to the signal, the precharge operation can be performed only for a necessary time.

  Further, the precharge period is limited to the first part of each horizontal synchronization period, and the output terminal Tout is precharged using the switches S4 and S5, whereby the output voltage Vout appearing at the output terminal Tout is supplied to the power supply. Since the voltage is raised to the voltage VDD or lowered to the ground potential GND, the capacitive load 60 such as an LCD can be driven at a high speed.

  The present invention can also be applied to so-called “2H” driving in which the polarity of the data signal is inverted every two horizontal synchronization periods. If the precharge is always performed regardless of the digital input signal Vdin, a so-called overdrive function can be realized by the present invention. As a result, there is an advantage that the writing time can be shortened. In this case, it is preferable to optimize the overdrive period according to the output voltage Vout.

(Modification)
The embodiments described above show examples embodying the present invention. Therefore, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say. For example, in the above embodiment, the upper n bits determination circuit 22 checks the upper n bits of the digital input signal Vdin to determine whether or not precharge is necessary. However, it is possible to determine whether or not precharge is necessary. If so, determination methods other than these can also be used.

It is a circuit diagram which shows the structure of the amplifier circuit for LCD drive used for the LCD drive circuit which concerns on one Embodiment of this invention. It is a functional block diagram which shows the structure of the LCD drive circuit based on one Embodiment of this invention. It is a wave form diagram which shows an example of the output waveform of the LCD drive circuit which concerns on one Embodiment of this invention. It is explanatory drawing which shows the division | segmentation of the operating range of the LCD drive circuit which concerns on one Embodiment of this invention. 4 is a timing chart showing an operation when the LCD drive circuit according to the embodiment of the present invention is not precharged. 6 is a timing chart showing an operation when precharging an LCD driving circuit according to an embodiment of the present invention. It is a functional block diagram which shows the structural example of the switch control circuit of the LCD drive circuit which concerns on one Embodiment of this invention. It is a block diagram of the switch control circuit which controls ON and OFF of switches S1-S5. It is a figure which shows schematic structure of the conventional liquid crystal display device (conventional example 1) using a "one side drive" system. 6 is a graph showing the relationship between 6-bit input data and gradation voltages V0 to V4 and V5 to V9. FIG. 10 is a circuit diagram showing a configuration of an output circuit used in the conventional liquid crystal display device shown in FIG. 9. FIG. 10 is a circuit diagram showing an example of a voltage follower constituting an output circuit used in the conventional liquid crystal display device shown in FIG. 9. FIG. 10 is a circuit diagram showing another example of a voltage follower that constitutes an output circuit used in the conventional liquid crystal display device shown in FIG. 9. 10 is a timing chart showing the operation of the conventional liquid crystal display device shown in FIG. FIG. 12 is a circuit diagram showing another configuration example (conventional example 2) that can be used for the voltage follower of FIG. 11. It is a wave form diagram which shows the output waveform in the voltage follower of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 LCD drive amplifier circuit 11 Differential amplifier part 12 Output part of differential amplifier part 21 D / A converter 22 Upper n bit determination circuit 23 Switch control circuit 30 Switch control circuit 31 Flip-flop circuit 32 Inverter 33, 34 Level shifter ( L / S)
40 Switch control circuit 41 D flip-flop 42, 43, 45, 49, 50 Level shifter (L / S)
44 NOR gate 46 n-input AND gate 47, 48 3-input AND gate 52 2-input AND gate 51 flip-flop 53 down counter 54 preset value input circuit 60 load (liquid crystal capacity of liquid crystal panel)
Tin input terminal Tout output terminal M1 N channel MOS transistor M2 P channel MOS transistor CI1, CI2, CI3 Constant current source S1, S2, S3, S4, S5 switch

Claims (6)

An amplifier circuit for receiving an input signal;
Second power sources of different conductivity types are connected in series between the two power supply terminals in a form in which the respective sources are connected to the output point, and push-pull drive the output point in response to the output signal of the amplifier circuit. A first and a second transistor ;
A first switch provided in parallel with the first transistor between one of the two power supply terminals and the output point;
A second switch provided in parallel with the second transistor between the other of the two power supply terminals and the output point;
Provided in a path connecting the output terminal of the drive circuit and the output point, and when the precharge is performed on the output point, the path is blocked, and when the precharge is not performed, the path is connected. A third switch controlled by
The drive circuit, wherein the first and second transistors are push-pull driven based on a class B operation, and a signal at the output point is fed back to the amplifier circuit. The drive circuit according to claim 1, further comprising a determination circuit that examines the input signal and determines whether precharge is necessary . The drive circuit according to claim 2 , wherein the determination circuit determines whether or not precharge is necessary by determining upper n bits (n is a positive integer) of the input signal . The drive circuit according to claim 3 , wherein the determination circuit is configured by an n-input AND circuit. A fourth switch and a first constant current source connected in series with each other are provided in parallel with the first transistor between one of the two power supply terminals and the output point, and are connected in series with each other. A fifth switch and a second constant current source are provided in parallel with the second transistor between the other of the two power supply terminals and the output point;
The fourth switch is ON / OFF controlled almost synchronously with the ON / OFF of the first transistor, and the fifth switch is ON / OFF controlled almost synchronously with the ON / OFF of the second transistor. The drive circuit according to claim 1. 6. The drive circuit according to claim 5, wherein the fourth switch, the first constant current source, the fifth switch, and the second constant current source are used for flowing an output idling current .

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