JP2019144548A - Display driver, display device, and method for driving display panel - Google Patents

Abstract

To accelerate driving of an input terminal of a source amplifier.SOLUTION: A display driver comprises: a DA converter configured to output a grayscale voltage corresponding to an image data; a source amplifier configured to drive a source line of a display panel; and a buffer connected between the DA converter and the output amplifier. The buffer comprises an NMOS transistor having a gate supplied with the grayscale voltage and a drain connected to a power supply, and is configured to supply a current depending on a current flowing through the NMOS transistor to an input terminal of the source amplifier.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a display driver, a display device, and a display panel driving method.

  A display driver that drives a display panel such as a liquid crystal display panel or an organic light emitting diode (OLED) display panel may be configured to drive a source line, also called a signal line or a data line. Display drivers are often designed to support image display at high refresh rates.

  In one embodiment, the display driver is configured to output a gradation voltage corresponding to image data, a DA converter configured to drive a source line of the display panel, a DA converter, and a source And a buffer connected between the amplifiers. The buffer includes an NMOS transistor in which the grayscale voltage is supplied to the gate and the drain is connected to the power supply, and a current depending on the current flowing through the NMOS transistor is supplied to the input terminal of the source amplifier. It is configured.

  In one embodiment, a display device includes a display panel including source lines and a display driver that drives the display panel. The display driver is connected between the DA converter configured to output the gradation voltage corresponding to the image data, the source amplifier configured to drive the source line of the display panel, and the DA converter and the source amplifier. Buffer. The buffer includes the NMOS transistor having a gradation voltage supplied to the gate and a drain connected to the power supply, and supplies a current dependent on the current flowing through the NMOS transistor to the input terminal of the source amplifier. It is configured.

  In one embodiment, the driving method of the display panel depends on outputting a gradation voltage corresponding to image data, and a current flowing through an NMOS transistor whose gradation voltage is supplied to the gate and whose drain is connected to the power source. Supplying current to the input terminal of the source amplifier and driving the source line of the display panel by the source amplifier.

It is a block diagram which shows the structure of the display apparatus in one Embodiment. It is a circuit diagram which shows the structure of the source driver circuit part in one Embodiment. It is a circuit diagram which shows the structure of the source amplifier in one Embodiment. It is a circuit diagram which shows the structure of the buffer in one Embodiment. It is a timing chart which shows operation | movement of the buffer in one Embodiment. It is a circuit diagram which shows the structure of the buffer in one Embodiment. It is a circuit diagram which shows the structure of the buffer in one Embodiment. It is a circuit diagram which shows the structure of the buffer in one Embodiment.

  Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the same or similar components may be referred to with the same or corresponding reference numerals. Further, when distinguishing a plurality of the same components, a suffix may be added to the reference symbol.

In one embodiment, as shown in FIG. 1, the display device 100 includes a display panel 1 and a display driver 2. Display device 100 is configured to display an image on the display panel 1 in accordance with the image data D _IN received from the host 3.

  In one embodiment, the display panel 1 includes a gate line 4, a source line 5, a pixel circuit 6, and a gate driver circuit unit 7 that drives the gate line 4. In one embodiment, each pixel circuit 6 is provided at a position where the corresponding gate line 4 and source line 5 intersect and is used as a sub-pixel of the pixel of the display panel 1. When a liquid crystal display panel is used as the display panel 1, the pixel circuit 6 may include a pixel electrode, a selection transistor, and a storage capacitor. When an OLED display panel is used as the display panel 1, the pixel circuit 6 may include a light emitting element, a selection transistor, and a storage capacitor. Various wirings other than the gate lines 4 and the source lines 5 can be provided in the display panel 1 depending on the configuration of the pixel circuit 6.

Source In one embodiment, the display driver 2 has a source connected to output S1~S each source line 5 of the display panel 1 (2n), in accordance with the image data D _IN received from the host 3 Drive line 5. In one embodiment, the display driver 2 may include an interface 11, an image IP core 12, and a source driver circuit unit 13. In one embodiment, the interface 11 transfers the images IP core 12 receives the image data _{D IN} from the host 3. In one embodiment, the image IP core 12 performs desired image processing on the image data _DIN . The source driver circuit unit 13 drives the source line 5 of the display panel 1 according to the image data output from the image IP core 12.

As illustrated in FIG. 2, in one embodiment, the source driver circuit unit 13 includes a gradation voltage generation circuit 21, gradation voltage wirings 22 _{1 to} 22 _m , DA converters 23 ₁ to 23 _2n, and a source amplifier 24. _{1 to} 24 _2n . In FIG. 2, symbols D _{1 to} D _2n indicate image data corresponding to the source outputs S1 to S (2n), respectively.

In one embodiment, the gradation voltage generation circuit 21 generates gradation voltages V _{1 to} V _m corresponding to the gradation values allowed for the image data D _{1 to} D _2n , and the generated gradation voltage V ₁ ~V _m to be supplied to the DA converter ₂₃ 1 _{~ 23 2n,} respectively via the gradation voltage line ₂₂ 1 through 22 _m. In one embodiment, the grayscale voltages V _{1 to} V _m have different voltage levels.

In one embodiment, the DA converters 23 ₁ to 23 _2n receive the gradation voltage V ₁ received via the gradation voltage wirings 22 _{1 to} 22 _m according to the gradation values described in the image data D _{1 to} D _2n. select ~V _m, and outputs the gray scale voltage selected. In one embodiment, each DA converter 23 _i selects two gradation voltage wirings 22 from the gradation voltage wirings 22 _{1 to} 22 _m in accordance with the gradation values described in the image data D _i , It operates as a selector that connects the two selected gradation voltage wirings 22 to the output terminal. In one embodiment, each DA converter 23 _i does not have its own driving capability.

In one embodiment, the source amplifiers 24 _{1 to} 24 _2n drive the source outputs S1 to S (2n) according to the grayscale voltages selected by the DA converters 23 ₁ to 23 _2n . In one embodiment, each source amplifier 24 _i has two inputs, and drives the source outputs S1 to S (2n) according to the voltages input to the two inputs, respectively.

As shown in FIG. 3, in one embodiment, each source amplifier 24 _i includes two input terminals 31 and 32, two input stages 33 and 34, an intermediate stage and an output stage, and an output terminal 36. May be. In FIG. 3, the intermediate stage and the output stage are collectively referred to by reference numeral 35.

  In one embodiment, the input stage 33 includes PMOS transistors MP11 and MP12, NMOS transistors MN11 and MN12, and constant current sources 37 and 38. In one embodiment, the sources of the PMOS transistors MP11 and MP12 are commonly connected to the constant current source 37, and the drains of the PMOS transistors MP11 and MP12 are connected to the intermediate stage. In one embodiment, the gate of the PMOS transistor MP11 is connected to the input terminal 31, and the gate of the PMOS transistor MP12 is connected to the output terminal. In one embodiment, the input stage 34 is configured similarly to the input stage 33 except that the PMOS transistor MP11 and the NMOS transistor MN11 are connected to the input terminal 32.

In one embodiment, the intermediate stage and the output stage 35 output the output voltage V _OUT according to the input voltages V _IN1 and V _IN2 and the lower bits D _{i_low} of the image data D _i input to the input terminals 31 and 32, respectively. It is configured to output. In one embodiment, the input voltage V _IN2 input to the input terminal 32 is higher than the input voltage V _IN1 input to the input terminal 31, and the intermediate stage and the output stage 35 are set to the lower bits D _{i_low} of the image data D _i. Accordingly, the output voltage V _OUT from the input voltage V _IN1 to the input voltage V _IN2 may be output.

As understood from FIG. 3, the capacitance of the input terminals 31 and 32 of each source amplifier 24 _i is approximately the sum of the gate capacitances Cp and Cn of the PMOS transistors MP11 and NMOS transistors MN11 of the input stages 33 and 34, respectively. . In one embodiment, the gate capacitance Cp of the PMOS transistor MP11, NMOS transistors MN11, Cn is reduced, the capacity of the input terminals 31 and 32 of the source amplifier 24 _i is compared with the capacity of gradation voltage lines ₂₂ 1 through 22 _m Therefore, it is suppressed considerably small.

In one embodiment, the refresh rate of the display device 100 is increased by reducing the rise and fall delays of the input voltages of the source amplifiers 24 _{1 to} 24 _2n . For example, in one embodiment, to reduce the effective input capacitance of the source amplifier ₂₄ 1 _{to 24 2n,} delay of the rise and fall of the source amplifier ₂₄ 1 _{to 24 2n} of the input voltage _{V IN1, V IN2} is reduced As a result, the refresh rate of the display device 100 is increased.

In one embodiment, the effective input capacitance of the source amplifier ₂₄ 1 _{to 24 2n} is reduced by reducing the influence of the mirror (Miller) Effect on the source amplifier ₂₄ 1 _{to 24 2n.} The Miller effect can increase the capacitance of each input terminal of each of the source amplifiers 24 _{1 to} 24 _2n by (1 + A) times. Here, A is the amplification factor of each of the source amplifiers 24 _{1 to} 24 ₂ .

In one embodiment, the source driver circuit 13 speeds up the rising and falling of the input voltage of the source amplifiers 24 _{1 to} 24 _2n by at least reducing the mirror effect of each of the source amplifiers 24 _{1 to} 24 _2. Increase the refresh rate of 100. For example, by reducing the Miller effect of the source amplifier ₂₄ 1 _{to 24 2n,} and reduce the effective input capacitance of the source amplifier ₂₄ 1 _{to 24 2n,} the source amplifier ₂₄ 1 _{to 24 2n} of the input voltage _{V IN1,} to reduce the delay of the rise and fall of the V _IN2.

In one embodiment, in order to reduce the effective input capacity of the source amplifiers 24 _{1 to} 24 _2n viewed from the gradation voltage wirings 22 _{1 to} 22 _m , the buffers 25 _{1 to} 25 _2n and 26 _{1 to} 26 _2n are It is inserted between the DA converters 23 ₁ to 23 _2n and the source amplifiers 24 _{1 to} 24 _2n .

FIG. 4 is a circuit diagram showing an example of the configuration of the buffer 25 _i connected to the input terminal 31 of the source amplifier 24 _i . In FIG. 4, reference numerals 41 and 42 indicate two output terminals of the DA converter 23 _i . In one embodiment, the DA converter 23 _i connects two of the gradation voltage wirings 22 _{1 to} 22 _m to the output terminals 41 and 42 according to the gradation value described in the image data D _i. Composed. In one embodiment, the buffer 25 _i has its input node N _IN connected to the output terminal 41 of the DA converter 23 _i and its output node N _OUT connected to the input terminal 31 of the source amplifier 24 _i . In one embodiment, the buffer 26 _i connected to the input terminal 32 of the source amplifier 24 _i has the same configuration as the buffer 25 _i and operates in the same manner. The circuit configuration of the buffer 26 _i is not shown in FIG.

In one embodiment, the buffer 25 _i includes an NMOS transistor MN1, a PMOS transistor MP1, and a switch 43.

In one embodiment, NMOS transistor MN1 and PMOS transistor MP1 drives the input terminal 31 of the source amplifier 24 _i by the source follower operation. In one embodiment, the gate of the NMOS transistor MN1 and PMOS transistor MP1 is connected in common to the input node _{N IN,} receives a gray scale voltage _{PV IN1} from the output terminal 41. In one embodiment, the NMOS transistor MN1 has a drain connected to the power supply that supplies the power supply voltage VDD, and a source connected to the output node _NOUT . In one embodiment, the PMOS transistor MP1 has a drain connected to circuit ground and a source connected to the output node N _OUT . In one embodiment, NMOS transistors MN1 operate as a pull-up transistor for pulling up the input terminal 31 of the source amplifier 24 _i, PMOS transistor MP1 operates as a pull-down transistor for pulling down the input terminal 31.

In one embodiment, the current I _N1 corresponding to the gradation voltage PV _IN1 input to the gate flows through the NMOS transistor MN1, and the NMOS transistor MN1 supplies the current I _N1 to the input terminal 31 of the source amplifier 24 _i . In one embodiment, the current I _P1 corresponding to the gradation voltage PV _IN1 input to the gate flows through the PMOS transistor MP1, and the PMOS transistor MP1 draws the current I _P1 from the input terminal 31 of the source amplifier 24 _i .

In one embodiment, the switch 43 includes an NMOS transistor MN2 and a PMOS transistor MP2. The NMOS transistor MN2 and the PMOS transistor MP2 constitute a transmission gate connected between the input node _NIN and the output node _NOUT . In one embodiment, the NMOS transistor MN2 has a drain connected to the input node N _IN and a source connected to the output node N _OUT . In one embodiment, the PMOS transistor MP2 has a source connected to the input node N _IN and a drain connected to the output node N _OUT . In one embodiment, the control signal VG1 is supplied to the gate of the PMOS transistor MP2, and the control signal VG2 is supplied to the gate of the NMOS transistor MN2. In one embodiment, the switch 43 electrically connects or disconnects the input node N _IN to the output node N _OUT under the control of the control signals VG1, VG2.

FIG. 5 shows an example of the operation of the buffer 25 _i in one embodiment. In one embodiment, at time t ₀ , the gradation voltage PV _IN1 is Vmin, and the switch 43 is set to the on state. In one embodiment, the input voltage V _IN1 supplied to the input terminal 31 of the source amplifier 24 _i at time t ₀ is Vmin. Here, Vmin is the lowest gradation voltage.

In one embodiment, when the image data _{D i} to be supplied to the DA converter 23 _i is changed at time _{t 1,} the gradation voltage _{PV IN1} supplied from the DA converter 23 _i into the buffer 25 _i also changes. FIG 5, the operation is illustrated when the gray voltage _{PV IN1} changes from Vmin to Vmax at time _{t 1.} Here, Vmax is the highest gradation voltage.

In one embodiment, in synchronization with the change of the image data _{D i,} switch 43 is set to the OFF state by the control signals VG1, VG2 at time _{t 1.}

In one embodiment, when the switch 43 is turned off, the NMOS transistor MN1 operates as a source follower and supplies a current I _N1 to the input terminal 31 of the source amplifier 24 _i . As a result, the potential of the input terminal 31 increases. In one embodiment, a threshold voltage _{V TH_N} of NMOS transistors MN1, in this case, NMOS transistors MN1 can pull up the input terminal 31 of the source amplifier 24 _i to _{Vmax-V TH_N.}

In one embodiment, then, at time _{t 2, the} switch 43 is set to the ON state by the control signals VG1, VG2. When the switch 43 is turned on, the output terminal 41 of the DA converter 23 _i is electrically connected to the input terminal 31 of the source amplifier 24 _i, an input terminal 31 of the source amplifier 24 _i is pulled up to Vmax.

In one embodiment, when the image data D _i supplied to the DA converter 23 _i subsequently changes at time t ₃ , the gradation voltage PV _IN1 supplied from the DA converter 23 _i to the buffer 25 _i also changes. FIG. 5 shows operation in the case of changes from Vmax to Vmin is shown in gray scale voltage _{PV IN1} the time _{t 3.}

In one embodiment, in synchronization with the change of the image data _{D i,} switch 43 is set to the OFF state by the control signals VG1, VG2 at time _{t 3.}

In one embodiment, when the switch 43 is turned off, PMOS transistor MP1 operates as a source follower, drawing current _{I P2} from the input terminal 31 of the source amplifier 24 _i. Thereby, the electric potential of the input terminal 31 falls. When the threshold voltage of the PMOS transistor MP1 is −V _{TH_P} , the PMOS transistor MP1 can pull down the input terminal 31 of the source amplifier 24 _i to Vmin + V _{TH_P} .

In one embodiment, then, at time _{t 4,} switch 43 is set to the ON state by the control signals VG1, VG2. In one embodiment, when the switch 43 is turned on, the output terminal 41 of the DA converter 23 _i is electrically connected to the input terminal 31 of the source amplifier 24 _i, an input terminal 31 of the source amplifier 24 _i is pulled down to Vmin The

When the buffer 25 _i is not provided and the output terminal 41 of the DA converter 23 _i is directly connected to the input terminal 31 of the source amplifier 24 _i , the effective input capacity of the buffer 25 _i viewed from the DA converter 23 _i is increases, the change in the input voltage _{V IN1} supplied to the input terminal 31 of the source amplifier 24 _i to changes in the image data _{D i} is delayed. In FIG. 5, the waveforms of the input voltage V _IN1 and the input current I _IN1 when the output terminal 41 of the DA converter 23 _i is directly connected to the input terminal 31 of the source amplifier 24 _i are indicated by broken lines.

In the circuit configuration shown in FIG. 5, by the action of the buffer 25 _i, the delay of the rise and fall of the input voltage V _IN1 supplied to the input terminal 31 of the source amplifier 24 _i is reduced. In one embodiment, when the buffer 25 _i is provided, the mirror effect is remarkably reduced because the buffer 25 _i does not have a voltage amplification function. In one embodiment, when the buffer 25 _i is provided, the buffer 25 _i does not have a voltage amplification function, so that the mirror effect does not appear. As a result, the effective input capacitance of the buffer 25 viewed from the DA converter 23 _i is reduced, and the voltage of the gate of the NMOS transistor MN1 of the buffer 25 _i quickly changes to the desired gradation voltage PV _IN1 . In NMOS transistors MN1, PMOS transistors MP1, can not be driven input terminal 31 of the source amplifier 24 _i to gray scale voltage _{PV IN1,} by turning on the switch 43, the gradation of the input terminal 31 of the source amplifier 24 _i It can be driven to a voltage PV _IN1 . By appropriately adjusting the timing at which the switch 43 is turned on, the input voltage V _IN1 input to the input terminal 31 of the source amplifier 24 _i can be quickly driven to the gradation voltage PV _IN1 .

In one embodiment, the action of the buffer 26 _i reduces the rise and fall delays of the input voltage _VIN2 supplied to the input terminal 32 of the source amplifier 24 _i as well.

In one embodiment shown in FIG. 6, the buffer 25 _i includes current mirrors 44 and 45 in addition to the NMOS transistor MN1, the PMOS transistor MP1, and the switch 43. In one embodiment, the drain of the source and the PMOS transistor MP1 of the NMOS transistor MN1, to the output terminal 36 of the source amplifier 24 _i, are connected in common.

In one embodiment, the current mirror 44 includes PMOS transistors MP3 and MP4. The sources of the PMOS transistors MP3 and MP4 are commonly connected to the power supply, and the gates are commonly connected to the drain of the PMOS transistor MP3. In one embodiment, the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN1, and the drain of the PMOS transistor MP4 is connected to the output node N _OUT . In one embodiment, the current mirror 44 generates a current I _N2 that depends on, and more specifically proportional to, the current I _N1 flowing through the NMOS transistor MN1, and supplies the current I _N2 to the input terminal 31 of the source amplifier 24 _i. To do.

In one embodiment, the current mirror 45 includes NMOS transistors MN3 and MN4. In one embodiment, the sources of the NMOS transistors MN3 and MN4 are commonly connected to circuit ground, and the gates are commonly connected to the drain of the NMOS transistor MN3. In one embodiment, the drain of the NMOS transistor MN3 is connected to the drain of the PMOS transistor MP1, and the drain of the NMOS transistor MN4 is connected to the output node N _OUT . In one embodiment, the current mirror 45 generates a current I _O2 that depends on the current I _P1 flowing through the PMOS transistor MP1, and more specifically is proportional, and draws the current I _P2 from the input terminal 31 of the source amplifier 24 _i. .

In one embodiment, buffer 26 _i is configured similarly to buffer 25 _i .

In one embodiment, buffer 25 _i shown in FIG. 6 operates in substantially the same manner as buffer 25 _i shown in FIG.

Buffer 25 _i shown in FIG. 6, in one embodiment, when pulling up the input terminal 31 of the source amplifier 24 _i, the input terminals 31 and 32 of the source amplifier 24 _i to a potential higher than _VP IN1 _{-V TH_N} Pull up. Here, PV _IN1 is a gradation voltage supplied from the DA converter 23 _i , and V _{TH_N} is a threshold voltage of the NMOS transistor MN1. Since the delay of the source amplifier 24 _i exists, the output voltage V _OUT of the source amplifier 24 _i does not change for a while after the image data D _i input to the DA converter 23 _i changes. Accordingly, after the image data _{D i} is changed, for a while, the gate of the NMOS transistor MN1 - source voltage becomes sufficiently large, the ON state of the NMOS transistor MN1 is maintained. While the on state of the NMOS transistor MN1 is maintained, since the current _{I N2} continues to be supplied from the current mirror 44 to the input terminal 31 of the source amplifier 24 _{i, VP} IN1 the potential of the input terminal 31 of the source amplifier 24 _{i -V TH_N} Can be pulled up to a higher potential.

The same principle, in one embodiment, the buffer 25 _i shown in FIG. 6, when pulling down the input terminals 31 and 32 of the source amplifier 24 _i, than the input terminal 31 of the source amplifier 24 _{i VP} IN1 _{+ V TH_P} Pull down to a lower potential. Here, V _{TH_P} is an absolute value of the threshold voltage of the PMOS transistor MP1. As described above, the output voltage V _OUT of the source amplifier 24 _i does not change for a while after the image data D _i input to the DA converter 23 _i changes. Accordingly, after the image data _{D i} is changed, for a while, the gate of the PMOS transistor MP1 - source voltage becomes sufficiently large, the ON state of the PMOS transistor MP1 is maintained. While the on state of the PMOS transistor MP1 is maintained, since the current mirror 45 continues draw current _{I P2} from the input terminal 31 of the source amplifier 24 _i, than the potential of the input terminal 31 of the source amplifier 24 _{i VP} IN1 _{+ V TH_P} It can be pulled down to a lower potential.

In one embodiment shown in FIG. 7, the buffer 25 _i has a configuration similar to the configuration shown in FIG. 6, but further includes NMOS transistors MN5 and MN6 and PMOS transistors MP5 and MP6. In one embodiment, the buffer 26 _i is configured similarly to the buffer 25 _i .

In one embodiment, the gates of the NMOS transistor MN5 and the PMOS transistor MP5 are commonly connected to the input node N _IN and receive the gradation voltage PV _IN1 from the output terminal 41 of the DA converter 23 _i . In one embodiment, the NMOS transistor MN5 has a drain connected to the power supply that supplies the power supply voltage VDD, and a source connected to the output node _NOUT . In one embodiment, the PMOS transistor MP6 has a drain connected to circuit ground and a source connected to the output node _NOUT .

In one embodiment, the PMOS transistor MP6 is connected in series with the current mirror 44 between the power supply and the output node N _OUT and operates as a switch that operates in response to the control signal VG2. In one embodiment, the PMOS transistor MP6 has a source connected to the power supply, a drain connected to the source of the PMOS transistor MP4 of the current mirror 44, and a gate supplied with the control signal VG2. Incidentally, PMOS transistor MP6 may be connected between the output node _{N OUT} and the current mirror 44.

In one embodiment, the NMOS transistor MN6 is connected in series with the current mirror 45 between the power supply and the output node N _OUT and operates as a switch that operates in response to the control signal VG1. In one embodiment, the NMOS transistor MN6 has a source connected to circuit ground, a drain connected to the source of the NMOS transistor MN4 of the current mirror 45, and a gate supplied with the control signal VG1. Incidentally, NMOS transistor MN6 may be connected between the output node _{N OUT} and the current mirror 45.

The buffer 25 _i shown in FIG. 7 operates in substantially the same manner as the buffer 25 _i shown in FIG. 6 in one embodiment, but the potential of the input terminal 31 of the source amplifier 24 _{i is controlled} by the operation of the NMOS transistor MN5 and the PMOS transistor MP5. Overshoot and undershoot can be suppressed. The structure of the buffer 25 _i shown in FIG. 6, in the operation to pull up the input terminal 31 of the source amplifier 24 _i, the source amplifier 24 _i from the current mirror 44 to the potential of the output terminal 36 of the source amplifier 24 _i is pulled up Since the current I _N2 is continuously supplied to the input terminal 31, the potential of the input terminal 31 of the source amplifier 24 _i may overshoot. In the configuration of the buffer 25 _i shown in FIG. 7, when the potential of the input terminal 31 of the source amplifier 24 _i rises excessively, the PMOS transistor MP5 is turned on, and the overshoot of the potential of the input terminal 31 of the source amplifier 24 _i is prevented. Can be suppressed. Similarly, in the operation to pull down the input terminal 31 of the source amplifier 24 _i, when the potential of the input terminal 31 of the source amplifier 24 _i is excessively lowered, NMOS transistor MN5 is turned on, the input terminal of the source amplifier 24 _i The undershoot of the potential of 31 can be suppressed.

  In one embodiment, in addition, during the period in which the switch 43 is set to the on state, the PMOS transistor MP6 and the NMOS transistor MN6 are set to the off state, and the operations of the current mirrors 44 and 45 are stopped. Such an operation is effective in reducing the power consumption by shortening the time for the current to flow from the power supply to the circuit ground through the current mirrors 44 and 45.

In one embodiment shown in FIG. 8, buffer 25 _i corresponds to an “overdrive” operation. In one embodiment, "overdrive" operation, the time to change significantly the output voltage V _OUT of the source amplifier 24 _i, to rapidly pull up or pull down the output terminal 36 of the source amplifier 24 _i.

In one embodiment, the buffer 25 _i performs an overdrive operation in response to the overdrive control signals SON and SOP. In one embodiment, the overdrive control signal SON is a low active signal and the overdrive control signal SOP is a high active signal. In one embodiment, the buffer 25 _i is configured to pull up the input terminal 31 of the source amplifier 24 _i to the power supply voltage VDD or a voltage close thereto when the overdrive control signal SON is activated. As a result, the output terminal 36 of the source amplifier 24 _i can be pulled up rapidly. In one embodiment, the buffer 25 _i is configured to pull down the input terminal 31 of the source amplifier 24 _i to a circuit ground voltage or a voltage close thereto when the overdrive control signal SOP is activated. Thereby, the output terminal 36 of the source amplifier 24 _i can be pulled down rapidly.

In one embodiment, the buffer 25 _{i includes} an NMOS differential input stage 51, a PMOS differential input stage 52, an active load circuit unit 53, and a switch 54.

In one embodiment, the NMOS differential input stage 51 includes NMOS transistors MN1, MN7, MN8. In one embodiment, the source of the NMOS transistor MN1, MN7 are connected in common to the node _{N 1.} In one embodiment, the drain of the NMOS transistor MN 1 is connected to the node N ₃ of the active load circuit unit 53, and the drain of the NMOS transistor MN ₇ is connected to the node N ₄ of the active load circuit unit 53. In one embodiment, the gate of the NMOS transistor MN1 is connected to the input node _{N IN,} the gate of the NMOS transistor MN7 are connected to the output node _{N OUT} which is connected to an input terminal 31 of the source amplifier 24 _i. In one embodiment, NMOS transistors MN8 operates as a constant current source to draw a constant current from the node _{N 1.} In one embodiment, the drain of the NMOS transistor MN8 is connected to the node N _1, a source connected to circuit ground, the bias voltage V _BN1 is supplied to the gate.

In one embodiment, the PMOS differential input stage 52 includes PMOS transistors MP1, MP7, MP8. In one embodiment, the source of the PMOS transistor MP1, MP7 are connected in common to the node _{N 2.} In one embodiment, the drain of the PMOS transistor MP 1 is connected to the node N ₅ of the active load circuit unit 53, and the drain of the PMOS transistor MP 7 is connected to the node N ₆ of the active load circuit unit 53. In one embodiment, the gate of the PMOS transistor MP1 is connected to the input node N _IN and the gate of the PMOS transistor MP7 is connected to the output node N _OUT . In one embodiment, PMOS transistor MP8 operates as a constant current source for supplying a constant current to node _{N 2.} In one embodiment, is connected the drain of the PMOS transistor MP8 to node N _2, a source connected to the power supply, the bias voltage V _BP1 is supplied to the gate.

  In one embodiment, the active load circuit unit 53 is connected to the drains of the NMOS transistors MN1 and MN7 and the drains of the PMOS transistors MP1 and MP7. In one embodiment, the active load circuit unit 53 includes current mirrors 55 and 56, a floating constant current source 57, PMOS transistors MP6, MP10, and MP11, and NMOS transistors MN6, MN10, and MN11.

  In one embodiment, PMOS transistor MP6 and NMOS transistor MN6 are configured to enable current mirrors 55 and 56 in response to control signals VG1 and VG2 that are also used to control switch 54. In one embodiment, the source of the PMOS transistor MP6 is connected to the power supply, the drain is connected to the current mirror 55, and the control signal VG2 is supplied to the gate. In one embodiment, the source of the NMOS transistor MN6 is connected to circuit ground, the drain is connected to the current mirror 56, and the control signal VG1 is supplied to the gate.

In one embodiment, a current mirror 55 is connected between the drain of the PMOS transistor MP6 and the nodes N ₃ and N ₄ . In one embodiment, the current mirror 55 includes PMOS transistors MP3 and MP4. In one embodiment, the sources of the PMOS transistors MP3 and MP4 are commonly connected to the drain of the PMOS transistor MP6, and the gates of the PMOS transistors MP3 and MP4 are commonly connected to the drain of the PMOS transistor MP3. In one embodiment, the drains of PMOS transistors MP3 and MP4 are connected to nodes N ₃ and N ₄ , respectively.

In one embodiment, a current mirror 56 is connected between the NMOS transistor MN6 and the nodes N ₅ and N ₆ . In one embodiment, the current mirror 56 includes NMOS transistors MN3 and MN4. In one embodiment, the sources of the NMOS transistors MN3 and MN4 are commonly connected to the drain of the NMOS transistor MN6, and the gates of the NMOS transistors MN3 and MN4 are commonly connected to the drain of the NMOS transistor MN3. In one embodiment, the drain of the NMOS transistor MN3, MN4, respectively, are connected to the node _N 5, _{N 6.}

In one embodiment, the floating constant current source 57 draws a constant current from the node N _3, and is configured to supply a constant current to node N _5. In one embodiment, the floating constant current source 57 includes an NMOS transistor MN9 and a PMOS transistor MP9. In one embodiment, it is connected to the common drain and source of the PMOS transistor MP9 of the NMOS transistor MN9 is the node _{N 3,} the source and the drain of the PMOS transistor MP9 of the NMOS transistor MN9 is connected in common to the node _{N 5.} In one embodiment, the bias voltage V _BN2 is supplied to the gate of the NMOS transistor MN9, and the bias voltage V _BP2 is supplied to the gate of the PMOS transistor MP9.

In one embodiment, switch 54 is connected between input node N _IN and output node N _OUT . In one embodiment, the switch 54 is configured to electrically connect or disconnect the input node N _IN and the output node N _OUT in response to the control signals VG1, VG2. In one embodiment, the switch 54 includes an NMOS transistor MN2 and a PMOS transistor MP2 that constitute a transmission gate. In one embodiment, the drain of NMOS transistor MN2 is connected to input node N _IN and the source is connected to output node N _OUT . In one embodiment, the source of the PMOS transistor MP2 is connected to the input node N _IN and the drain is connected to the output node N _OUT . In one embodiment, the control signal VG1 is supplied to the gate of the PMOS transistor MP2, and the control signal VG2 is supplied to the gate of the NMOS transistor MN2.

In one embodiment, PMOS transistors MP10 and MP11 and NMOS transistors MN10 and MN11 are used to perform an overdrive operation in response to overdrive control signals SON and SOP. In one embodiment, PMOS transistors MP10, MP11 are connected in series between the drain and the output node _{N OUT} of the PMOS transistor MP6. In one embodiment, the source of the PMOS transistor MP10 is connected to the drain of the PMOS transistor MP6, and the gate is commonly connected to the gates of the PMOS transistors MP3 and MP4. In one embodiment, the source of the PMOS transistor MP11 is connected to the drain of the PMOS transistor MP10, and the drain is connected to the output node _NOUT . In one embodiment, the overdrive control signal SON is supplied to the gate of the PMOS transistor MP11. The PMOS transistor MP11 functions as a switch that operates in response to the overdrive control signal SON. In one embodiment, NMOS transistors MN 10, MN11 are connected in series between the drain and the output node _{N OUT} of the NMOS transistor MN6. In one embodiment, the source of the NMOS transistor MN10 is connected to the drain of the NMOS transistor MN6, and the gate is commonly connected to the gates of the NMOS transistors MN3 and MN4. In one embodiment, the source of the NMOS transistor MN11 is connected to the drain of the NMOS transistor MN10, the drain is connected to the output node _NOUT , and the overdrive control signal SOP is supplied to the gate. The NMOS transistor MN11 functions as a switch that operates according to the overdrive control signal SOP.

In one embodiment, the buffer 25 _i shown in FIG. 8 drives the input terminal 31 of the source amplifier 24 _i by the source follower operation when both the overdrive control signals SON and SOP are deactivated. Is configured to do.

In one embodiment, when the gray scale voltage PV _IN1 supplied to the gate of the NMOS transistor MN1 is pulled up, a current I _N1 flowing through the NMOS transistor MN1 is generated depending on the gray scale voltage PV _IN1 , and the current mirror 55 supplies a current I _N2 corresponding to the current I _N1 to the input terminal 31 of the source amplifier 24 _i to increase the input voltage V _IN1 . In one embodiment, subsequently, the switch 54 is set to the ON state by the control signals VG1 and VG2. In one embodiment, the switch 54 is turned on, the output terminal 41 of the DA converter 23 _i is electrically connected to the input terminal 31 of the source amplifier 24 _i, thereby, an input terminal 31 of the source amplifier 24 _i is floors _Pulled up to regulated voltage PV _IN1 .

In one embodiment, when the gray scale voltage PV _IN1 supplied to the gate of the PMOS transistor MP1 is _pulled down, a current I _P1 flowing through the PMOS transistor MP1 is generated depending on the gray scale voltage PV _IN1 , and the current mirror 56 is The current I _P2 corresponding to the current I _P1 is drawn from the input terminal 31 of the source amplifier 24 _i to reduce the input voltage V _IN1 . In one embodiment, subsequently, the switch 54 is set to the ON state by the control signals VG1 and VG2. In one embodiment, the switch 54 is turned on, the output terminal 41 of the DA converter 23 _i is electrically connected to the input terminal 31 of the source amplifier 24 _i, thereby, an input terminal 31 of the source amplifier 24 _i is floors _Pulled down to regulated voltage PV _IN1 .

As shown in FIG. 8, the use of the NMOS differential input stage 51 and the PMOS differential input stage 52 is effective for reducing or eliminating the dead band in which both the NMOS transistor MN1 and the PMOS transistor MP1 do not operate as source followers. It is. In one embodiment, for the entire allowable range of the grayscale voltage PV _IN1 , at least one of the NMOS transistor MN1 and the PMOS transistor MP1 operates as a source follower, and controls the current I _N2 and / or the current I _P2 .

In one embodiment, when one of the overdrive control signals SON, SOP is activated, the buffer 25 _i operates to perform the overdrive operation. In one embodiment, when the overdrive control signal SON is activated, the PMOS transistor MP11 is turned on. In one embodiment, this drives the input terminal 31 of the source amplifier 24 _i to the power supply voltage VDD or a voltage close thereto regardless of the grayscale voltage PV _IN1 . In one embodiment, the NMOS transistor MN11 is turned on when the overdrive control signal SOP is activated. In one embodiment, this drives the input terminal 31 of the source amplifier 24 _i to a circuit ground voltage or a voltage close thereto, regardless of the grayscale voltage PV _IN1 .

Although various embodiments of the present disclosure are specifically described above, the technology described in the present disclosure can be implemented with various modifications. For example, in the above-described embodiment, a configuration in which each source amplifier 24 _i has two input terminals 31 and 32 is described, but the number of input terminals of each source amplifier 24 _i is not limited to two. Each source amplifier 24 _i may have one input terminal or three or more input terminals. In this case, a buffer having the same configuration as the above-described buffer 25 _i is connected to each input terminal of the source amplifier 24 _i .

100: Display device 1: Display panel 2: Display driver 3: Host 4: Gate line 5: Source line 6: Pixel circuit 7: Gate driver circuit unit 11: Interface 12: Image IP core 13: Source driver circuit unit 21: Floor Voltage regulation circuit 22: gradation voltage wiring 23: DA converter 24: source amplifier 25, 26: buffer 31, 32: input terminal 33, 34: input stage 35: intermediate stage and output stage 36: output terminals 37, 38: Constant current sources 41, 42: output terminal 43: switches 44, 45: current mirror 51: NMOS differential input stage 52: PMOS differential input stage 53: active load circuit section 54: switches 55, 56: current mirror 57: floating Constant current sources MN1 to MN6, MN9 to MN12: NMOS transistors MP1 to MP6, MP9 to MP12: PMO Transistor

Claims (22)

A DA converter configured to output a gradation voltage corresponding to image data;
A source amplifier configured to drive the source line of the display panel;
A buffer connected between the DA converter and the source amplifier;
The buffer includes a first NMOS transistor in which the gray scale voltage is supplied to a gate and a drain is connected to a power source, and a current dependent on a first current flowing through the first NMOS transistor is input to the source amplifier. A display driver configured to supply a terminal. The buffer further includes a first PMOS transistor in which the grayscale voltage is supplied to a gate and a drain is connected to circuit ground, and a current dependent on a second current flowing in the first PMOS transistor is supplied to the source. The display driver according to claim 1, wherein the display driver is configured to be pulled out from the input terminal of the amplifier. The display driver according to claim 1, wherein the buffer further includes a first switch connected between an output terminal of the DA converter and the input terminal of the source amplifier. An output terminal of the source amplifier is connected to a source of the first NMOS transistor;
The buffer further comprises a first current mirror configured to generate a third current corresponding to the first current and supply the third current to the input terminal of the source amplifier. 4. The display driver according to any one of 3 above. A source of the first NMOS transistor and a source of the first PMOS transistor are commonly connected to an output terminal of the source amplifier;
The buffer further comprises:
A first current mirror configured to generate a third current corresponding to the first current and supply the third current to the input terminal of the source amplifier;
The display driver according to claim 2, further comprising: a second current mirror configured to generate a fourth current corresponding to the second current and draw the fourth current from the input terminal of the source amplifier. The display driver according to claim 4, wherein the buffer further includes a first switch connected between an output terminal of the DA converter and the input terminal of the source amplifier. The buffer further comprises:
A second NMOS transistor in which the gradation voltage is supplied to a gate, a drain is connected to a power source, and a source is connected to the input terminal of the source amplifier;
The display driver according to claim 5, further comprising: a second PMOS transistor in which the gradation voltage is supplied to a gate, a drain is connected to circuit ground, and a source is connected to the input terminal of the source amplifier. The display driver according to claim 4, wherein the buffer further includes a second switch connected in series to the first current mirror between the input terminal of the source amplifier and a power source. . The buffer further comprises:
A second switch connected in series with the first current mirror between the input terminal of the source amplifier and a power source;
The display driver according to claim 5, further comprising a third switch connected in series to the second current mirror between the input terminal of the source amplifier and circuit ground. The buffer further includes a first switch connected between the output terminal of the DA converter and the input terminal of the source amplifier;
The display driver according to claim 9, wherein when the first switch is in an on state, the second switch and the third switch are set in an off state. The buffer further comprises:
A second NMOS transistor in which the gradation voltage is supplied to a gate, a drain is connected to a power source, and a source is connected to the input terminal of the source amplifier;
The display driver according to claim 9, further comprising: a second PMOS transistor in which the gradation voltage is supplied to a gate, a drain is connected to circuit ground, and a source is connected to the input terminal of the source amplifier. The buffer further comprises:
A third NMOS transistor having a source connected to the source of the first NMOS transistor and a gate connected to the input terminal of the source amplifier;
The display driver according to claim 2, further comprising: a third PMOS transistor having a source connected to the source of the first PMOS transistor and a gate connected to the input terminal of the source amplifier. The buffer further comprises:
A first constant current source for extracting a first constant current from the sources of the first NMOS transistor and the third NMOS transistor;
The display driver according to claim 12, further comprising: a second constant current source that supplies a second constant current to sources of the first PMOS transistor and the third PMOS transistor. The buffer further comprises an active load circuit connected to the drains of the first NMOS transistor and the third NMOS transistor and to the drains of the first PMOS transistor and the third PMOS transistor;
The active load circuit supplies a third current corresponding to the first current to the input terminal of the source amplifier, and draws a fourth current corresponding to the second current from the input terminal of the source amplifier. The display driver according to claim 12 or 13, wherein the display driver is configured. The buffer further comprises:
A fourth switch connected between a power source and the input terminal of the source amplifier and operating in response to a first overdrive control signal;
The display driver according to claim 1, further comprising: a fifth switch connected between circuit ground and the input terminal of the source amplifier and operating in response to a second overdrive control signal. Furthermore,
A gradation voltage generation circuit that generates a plurality of gradation voltages in a plurality of gradation voltage wirings,
The DA converter is configured to select any one of the plurality of gradation voltage wirings according to the image data, and to connect the selected gradation voltage wiring to the buffer. The display driver according to item 1. A display panel with source lines;
A display driver for driving the display panel;
The display driver is
A DA converter configured to output a gradation voltage corresponding to image data;
A source amplifier configured to drive the source line of the display panel;
A buffer connected between the DA converter and the source amplifier;
The buffer includes a first NMOS transistor in which the gray scale voltage is supplied to a gate and a drain is connected to a power source, and a current dependent on a first current flowing through the first NMOS transistor is input to the source amplifier. A display device configured to supply terminals. The buffer further includes a first PMOS transistor in which the grayscale voltage is supplied to a gate and a drain is connected to circuit ground, and a current dependent on a second current flowing in the first PMOS transistor is supplied to the source. The display device according to claim 17, wherein the display device is configured to be drawn from the input terminal of the amplifier. The display device according to claim 17 or 18, wherein the buffer further includes a first switch connected between an output terminal of the DA converter and the input terminal of the source amplifier. Outputting a gradation voltage corresponding to the image data;
Supplying to the input terminal of the source amplifier a current dependent on a first current flowing through the NMOS transistor having the grayscale voltage supplied to the gate and the drain connected to the power supply;
Driving a source line of the display panel by the source amplifier. Furthermore,
21. The driving method according to claim 20, further comprising: extracting from the input terminal of the source amplifier a current that depends on a second current that flows through a PMOS transistor having the grayscale voltage supplied to a gate and a drain connected to circuit ground. . Furthermore,
The driving method according to claim 20 or 21, further comprising electrically connecting an output terminal of the DA converter that outputs the gradation voltage and the input terminal of the source amplifier.

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