JP2001324540A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit(IC) incorporating a functional test circuit capable of testing a complicated logical process with a small circuit scale. SOLUTION: The pattern data PTN of the output expected values corresponding to input signals IN1-INm are inputted in series from a test input terminal 9, converted into parallel data by a S/P converter 7, and fed to a first input side of a comparator 5. A prescribed logical arithmetic process is applied to the input signals IN1-INm by a logic section 2, and the processed results are fed to a second input side of the comparator 5. The processed results by the logic section 2 are compared with the pattern data PTN of the output expected values, and the compared results are outputted from a test output terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit (hereinafter, referred to as "IC") having a built-in circuit for functional test.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional IC. This IC includes input signals IN1, IN2,.
Input terminals ₁ 1 Nm is _given, 1 2, ..., it has a _{1 m,} the logic unit 2 connected to these input terminals ₁ 1 to 1 _m. The logic unit 2 includes input signals IN1 to INm
., OUTn as a result of the processing. The output sides of the logic unit 2 are output terminals 3 ₁ , 3
_2, ..., are connected to _{3 n,} these outputs ₃ 1 to 3 _n
Output signals OUT1 to OUTn.

Further, this IC has a read-only memory (hereinafter referred to as "ROM") 4 as a function test circuit,
A comparator 5 is provided. The address terminals of the ROM 4
Input terminals ₁ 1 to 1 _m is connected, the input signal IN1~IN
m is given as an address signal.
A data terminal of the ROM 4 is connected to a first input side of a comparator 5, and a second input side of the comparator 5 has a logic unit 2.
Output side is connected. The comparator 5 outputs a coincidence signal when the signals supplied to the first and second input sides coincide, and the output side of the comparator 5 is connected to the test output terminal 6.

In this IC, the expected output values of the output signals OUT1 to OUTn to be output from the logic unit 2 are calculated in advance for each combination of the input signals IN1 to INm. It is stored in a corresponding storage location of the ROM 4 having the address of INm. When testing the function of the the IC, with an inputting input signals IN1~INm for testing by connecting the test apparatus to the input terminal 1 ₁ to 1 _m, for monitoring the coincidence signal is output to the test output terminal 6.

[0005] Input signals IN1~INm supplied to the input terminal ₁ 1 to 1 _m, the predetermined logical operation is performed in the logic unit 2, the output signal of the processing result OUT1~OUTn
Together but is output to the output terminal 3 ₁ to 3 _n, applied to the second input of the comparator 5. Also, the input signals IN1 to I1
Nm is given as an address signal for the ROM 4. Thereby, the input signal I stored in the ROM 4 in advance
The expected output values corresponding to N1 to INm are output from the data terminals of the ROM 4 and supplied to the first input side of the comparator 5.

In the comparator 5, output signals OUT1 to OUTn of the processing result given from the logic unit 2 and the ROM 4
Is compared with the expected output value given by the test output terminal 6. If the two match, the test output terminal 6 outputs a match signal. The input signals IN1 to INm are sequentially switched, the coincidence signal of the terminal 6 is monitored for all combinations, and the function of the logic unit 2 is tested.

[0007] As described above, this IC uses the input signal IN1.
R that stores the expected output value for each combination of
Since the OM 4 is provided, a functional test can be easily performed even for an IC that performs complicated logical processing without requiring a test apparatus having a special function.

[0008]

However, in the conventional IC, since the ROM 4 in which the expected output value is stored in advance for each combination of all the input signals IN1 to INm must be built in, the cost increases and the cost increases. However, there is a problem that the chip size becomes large.

An object of the present invention is to solve the problems of the prior art and to provide an IC having a built-in function test circuit capable of testing complicated logic processing with a small circuit scale.

[0010]

According to a first aspect of the present invention, a plurality of input terminals to which input signals are supplied in parallel, and an input signal supplied to the input terminals are provided. The following test input terminal and serial-parallel converter (IC) are provided in an IC provided with a logic unit for performing a predetermined logical operation process based on the above, and a plurality of output terminals for outputting processing results of the logic unit in parallel. Hereinafter, referred to as “S / P converter”), a comparator, and a test output terminal.

[0011] The test input terminal is a terminal to which an expected output value of a logical operation process performed in the logic section based on the input signal is given in series. The S / P converter converts the expected output value given to the test input terminal into parallel data. The comparator compares the output expected value converted into parallel data by the S / P converter with the processing result of the logic unit. The test output terminal outputs a signal indicating the result of comparison by the comparator.

According to the first aspect, since the IC is configured as described above, the following operation is performed. The input signals applied in parallel to the plurality of input terminals are applied to a logic unit to perform predetermined logical operation processing, and the processing results are output to output terminals in parallel. On the other hand, the expected output value of the logical operation performed by the logic unit based on the input signal is given to the test input terminal, and is converted into parallel data by the S / P converter. The output expected value converted into parallel data and the processing result of the logic unit are compared by a comparator, and a signal of the comparison result is output from a test output terminal.

According to a second aspect of the present invention, in the same IC as the first aspect, a test input signal and an expected output value of a logical operation performed in the logic section based on the test input signal are serially given. A S / P sequence converter for converting a test input signal and an output expected value given to the test input terminal into parallel data, and a test input signal converted to parallel data by the S / P converter. An input switching unit for providing the input signal to the logic unit, a comparator similar to the first invention, and a test output terminal are provided.

According to the second aspect, the following operation is performed. The test input signal serially supplied to the test input terminal and the output expected value of the logical operation performed by the logic unit based on the test input signal are converted into parallel data by the S / P converter. The test input signal converted to parallel data by the S / P converter is provided as an input signal to a logic unit via an input switching unit, and a predetermined logical operation process is performed, and a processing result is output in parallel to an output terminal. Is done. The processing result of the logic unit is given to the comparator, compared with the output expected value converted into parallel data by the S / P converter, and a signal of the comparison result is output from the test output terminal.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG.
FIG. 2 is a configuration diagram of an IC showing a first embodiment of the present invention,
The same reference numerals are given to the elements common to the elements described above. This
2 have input signals IN1 to IN similar to the IC of FIG.
input terminal 1 to which m is given₁~ 1_mAnd these inputs
Child 1₁~ 1_mThe logic unit 2 is connected to the
The logic unit 2 performs a predetermined operation according to the input signals IN1 to INm.
And the output signal OUT of the processing result
1 to OUTn. Output of logic part 2
Output terminal 3 on the power side₁~ 3_nConnected to this output terminal 3
₁~ 3 _nOutput signals OUT1 to OUTn are output from
It has become. In addition, this IC is
The S / P converter 7 and the comparator 5 are provided as paths,
Test input terminals 8 and 9 are provided.

The test input terminal 8 is a terminal for applying pattern data PNT of an expected output value of the logic unit 2 in series. The test input terminal 9 is connected to the pattern data PN.
This is a terminal for supplying a clock signal CLK indicating the input timing of T. The test input terminals 8 and 9 are connected to a serial input terminal and a clock terminal of the S / P converter 7, respectively.

The S / P converter 7 fetches and holds serial data applied to a serial input terminal while sequentially shifting the data in synchronization with a clock signal CLK applied to a clock terminal, and converts the serial data as parallel data from a parallel output terminal. Output. The parallel output terminal of the S / P converter 7 is connected to the first
, And an output side of the logic unit 2 is connected to a second input side of the comparator 5. Comparator 5
Outputs a coincidence signal when the signals supplied to the first and second input sides coincide. The output side of the comparator 5 is connected to the test output terminal 6.

Next, the operation of the IC during a function test will be described. First, the input terminal ₁ 1 to 1 _m, and the test input terminal 8,
9 is connected to a test device such as a logic tester.

Next, provide the input terminal ₁ 1 to 1 _m, the input signal IN1~INm for testing in parallel. In addition, pattern data PTN of expected output values of output signals OUT1 to OUTn to be output from the logic unit 2 based on the input signals IN1 to INm are provided in series from the test input terminal 8. Input signal supplied to the input terminal _{1 1 ~1 m IN1~}
INm is subjected to predetermined logical operation processing by the logic unit 2, and output signals OUT ₁ to OUTn of the processing result are output to the output terminals 31 to 3 _n and are given to the second input side of the comparator 5. Can be

On the other hand, the pattern data PNT applied to the test input terminal 8 is converted into parallel data by the S / P converter 7 in accordance with the clock signal CLK applied to the test input terminal 9, and the first data of the comparator 5 To the input side. The comparator 5 compares the output signals OUT1 to OUTn of the processing result given from the logic unit 2 with the pattern data PTN given from the S / P converter 7, and if they match, a test output terminal. 6 outputs a coincidence signal. Such a test is performed for all combinations of input signals IN1 to INm to be tested, and the function of the logic unit 2 is tested.

As described above, the IC of the first embodiment
Has the following advantages (1) to (3). (1) An S / P converter 7 for inputting pattern data PTN of an expected output value corresponding to a combination of the input signals IN1 to INm in series and converting the pattern data PTN in parallel. For this reason,
Does not require a large number of test input terminals. (2) The comparator 5 compares the output signal of the S / P converter 7 with the output signal of the logic unit 2 and outputs a coincidence signal of the comparison result. As a result, an IC that performs complicated logic processing even in a test apparatus that does not have many test input terminals
The result of the function test can be determined. (3) Unlike the IC of FIG. 2, it is not necessary to store the expected output value in the ROM 4 in advance, so that the contents of the function test can be freely changed or added.

(Second Embodiment) FIG. 3 shows a second embodiment of the present invention.
FIG. 2 is a configuration diagram of an IC showing the embodiment of FIG. 1, in which components common to those in FIG. 1 are denoted by common reference numerals. In this IC, the input terminals 1 ₁ to 1 _m are connected to an input switching unit (for example, a two-input OR gate, hereinafter referred to as “OR”) 10 ₁ , 1
0 _2, ..., it is connected to the input side of the logic unit 2 through a 10 _m. Further, the m-bit S / P converter 7 in FIG.
S / P having m + n-bit parallel output terminals
A converter 7A is provided. M in the first half of S / P converter 7A
The bit parallel output terminal is connected to the second input side of OR10 ₁ to 10 _m , and the latter half n-bit parallel output terminal is
It is connected to the first input of the comparator 5. Other configurations are the same as those in FIG.

Next, the operation of the IC during a function test will be described. First, all of the input terminals ₁ 1 to 1 _m and sets the logical value "0", to connect the test equipment to the test input terminals 8 and 9.

Next, the clock signal CL is applied to the test input terminal 9.
K from the test input terminal 8 according to the timing of the clock signal CLK.
m and pattern data PTN of an expected output value with respect to the input signals IN1 to INm.

The input signal IN applied to the test input terminal 8
1 to INm and the pattern data PTN are converted by the S / P converter 7
At A, the data is converted into parallel data of an m-bit input signal IN1 to INm and n-bit pattern data PTN, and output to a parallel output terminal. The m-bit input signals IN1 to INm converted in parallel by the S / P converter 7A are OR10 ₁
Given the logic unit 2 through to 10 _m, a predetermined logical operation is performed. Output signal OUT1 of logic unit 2
~OUTn is output to the output terminal ₃ 1 to 3 _n, it applied to the second input of the comparator 5.

The n-bit pattern data PNT converted into parallel data by the S / P converter 7A is supplied to the first input side of the comparator 5. In the comparator 5, the output signals OUT1 to OUTn given from the logic unit 2 and S /
The pattern data PTN provided from the P converter 7A is compared with the pattern data PTN, and if they match, a match signal is output from the test output terminal 6. Such a test is performed on the input signals IN1 to INm of all combinations to be tested and the corresponding pattern data PTN, and the logic unit 2
Test the function of.

As described above, the IC of the second embodiment
Has the following advantages (4) in addition to the advantages (1) to (3). (4) The input signal IN1 together with the pattern data PTN
ＩＮINm are input in series and the S / P converter 7A converts the signals in parallel. Therefore, even in a test apparatus that does not have many test output terminals, the input signals IN1 to INm can be given to an IC that performs complicated logic processing.

The present invention is not limited to the above embodiment.
However, various modifications are possible. Examples of this variant are
For example, there are the following (a) and (b). (A) In the IC of FIGS. 1 and 3, the output terminal 3₁~ 3_n
Output signals OUT1 to OUTn output to
Although the data PTN is compared with the data PTN,
It is also possible to compare the signal with the pattern data PTN.
You. (B) OR10 in FIG.₁-10_mSelector instead of
Use the input terminal 1 ₁~ 1_mSide and S / P converter 7
It is also possible to switch between the A side.

[0029]

As described above in detail, according to the first aspect, the test input terminal to which the output expected value of the logical operation processing is given in series, and the output expected value given to this test input terminal, And a serial-parallel converter for converting the data into parallel data. Thus, a large number of test signals can be input with a small number of test input terminals.

Further, it has a comparator for comparing the expected output value with the processing result of the logic unit, and a test output terminal for outputting a signal of the comparison result. As a result, even a test apparatus that does not have a large number of test input terminals can determine the result of a functional test of an IC that performs complicated logical processing. Further, unlike the conventional IC, it is not necessary to previously store the expected output value in the ROM, so that the contents of the function test can be freely changed or added.

According to the second aspect of the present invention, a test input terminal to which a test input signal is provided in series in addition to an expected output value, an S / P converter for converting these into parallel data, and a conversion into parallel data. An input switching unit that supplies a test input signal to the logic unit. Thus, in addition to the effects of the first aspect, even in a test apparatus that does not have many test output terminals, an input signal can be given to an IC that performs complicated logical processing.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an IC showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an example of a conventional IC.

FIG. 3 is a configuration diagram of an IC showing a second embodiment of the present invention.

[Explanation of symbols]

1 ₁ to 1 _m input terminal 2 Logic section 3 _{1 to} 3 _n output terminal 5 Comparator 6 Test output terminal 7, 7A S / P converter (serial / parallel converter) 8, 9 Test input terminal 10 ₁ to 10 _m OR (OR gate)

Claims (2)

[Claims] A plurality of input terminals to which input signals are supplied in parallel; a logic unit for performing a predetermined logical operation based on the input signals supplied to the input terminals; and a processing result of the logic unit in parallel. An integrated circuit including a plurality of output terminals for outputting, a test input terminal to which an output expected value of a logical operation process performed by the logic unit based on the input signal is serially given; A serial-to-parallel converter for converting the output expected value into parallel data, a comparator for comparing the output expected value converted to parallel data by the serial-to-parallel converter and a processing result of the logic unit, An integrated circuit, comprising: a test output terminal that outputs a comparison result signal. 2. A plurality of input terminals to which input signals are supplied in parallel, a logic unit for performing a predetermined logic operation based on the input signals supplied to the input terminals, and a processing result of the logic unit in parallel. An integrated circuit having a plurality of output terminals for outputting, a test input terminal to which a test input signal and an expected output value of a logical operation performed in the logic unit based on the test input signal are given in series; A serial-to-parallel converter that converts a test input signal and an output expected value given to an input terminal into parallel data; and a test input signal that is converted to parallel data by the serial-to-parallel converter as the input signal to the logic unit. An input switching unit, a comparator that compares an expected output value converted into parallel data by the serial / parallel converter with a processing result of the logic unit, Integrated circuit, characterized in that a test output terminal for outputting the compare result signals provided.