JPH11344535A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit capable of arbitrarily changing the constitution, and high in recycling possibility. SOLUTION: A semiconductor integrated circuit device is provided with a plurality of registers REG1-REG8 which are successively connected to each other, a switching circuit 1 connected between stages of the registers, and a register length judging circuit to output the bit width setting signal, and each switching circuit 1 is provided with an AND gate G1 and an EXOR gate G. When the corresponding data in the parallel control data S11-S17 is [1], the register output of the final stage is outputted without any change, and the corresponding EXOR gate G2 outputs the output of the AND gate G1, the register output of the previous stage, and the exclusive logical sum. When the corresponding data in the parallel control data S11-S17 is [1], the EXOR gate G2 functions as a feedback point. The bit width of MFSR and the position of the feedback point can be arbitrarily set by the logic of the externally fed parallel control data S11-S19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for automatically testing one or more circuit blocks included in a semiconductor integrated circuit by using a shared built-in self-test circuit.

[0002]

2. Description of the Related Art BIST is one of the test facilitating methods for solving the difficulty of testing large and complex semiconductor integrated circuits.
(Built-In Self Test). BIST is to automatically generate the test pattern given to the test block under test and analyze the test results output from the test block automatically by the logic circuits configured around the test block. It is characterized by. FIG. 8 is a general configuration diagram of BIST. When the external input signal TEST has a predetermined logic, the semiconductor integrated circuit including the test target block 51 is set to the test mode. As a result, a test input signal different from that in the normal operation is supplied to the input terminal of the test target block 51. After the entire circuit of FIG. 8 is initialized, a self test is executed by inputting a predetermined number of BIST clocks CLOCK. The external input signal TEST and the BIST clock CLOCK are directly supplied from outside.

During the execution of the self-test, an input signal to the block under test 51 is automatically generated by a test pattern generator 53. The test result output from the test target block 51 is input to the test result analyzer 54,
The data is sequentially compared with expected values or compressed and converted into data (signature) having a specific bit width. Finally, the test analysis result of the test target block 51 is output, and the analysis result output device 55 determines whether the test is good or bad by the test.

In BIST, it is not necessary to store test patterns in an external tester memory, so that the configuration of the tester can be simplified and the cost of the tester can be reduced. Further, since all operations are performed in the chip in synchronization with the BIST clock CLOCK, if the BIST clock CLOCK is accelerated, the test can be performed at a higher speed than the test operation frequency by the tester. Therefore, a product test can be performed while the test target block 51 is actually operated. Also, BIST requires only a small number of test external input / output signals, so that a plurality of blocks can be tested in parallel. As a result, the test time of the entire chip including these blocks can be significantly reduced.

The BIST is classified into a memory BIST for a memory device and a logic BIST for a logic block according to the type of the block under test 51. Since the memory device generally operates regularly, the test pattern generator 53 for the memory device generates an algorithmically regular pattern. On the other hand, since the logic block generally operates at random, the test pattern generator 53 for the logic block generates a random pattern. An LFSR (Linear Feedback Shift Register) is often used as a random pattern generator because of its simple structure.

FIG. 9 is a diagram showing a configuration example of an 8-bit LFSR. The LFSR in FIG. 9 is configured by cascading eight registers REG1 to REG8, and each of the registers REG1 to REG8 performs a shift operation in synchronization with a clock CLK. Each register REG1
An EXOR gate G10 is provided at a specific location between the stages of REG8 to calculate the exclusive OR of the output of the previous stage register and the output of the last stage register REG8 and supply the result to the next stage register. This specific location is called a feedback point. The output terminal of the last-stage register REG8 is supplied to the input terminal of the first-stage register REG1.

When the LFSR of FIG. 9 is used as a pattern generator, first, each of the registers REG1 to REG
8 is initialized to a predetermined initial value (all non-zero values). After that, every time the clock CLK is input,
The output value of the register shifts and a random number pattern is generated. The generated random number pattern is stored in the last register
The data is output serially from the REG 8 or output in parallel from the registers of each stage and supplied to the block under test.

In the LFSR shown in FIG. 9, when the above-mentioned feedback point is set at a desired position between the stages of the register, all combinations of patterns (except for all 0s) that can be obtained from the register are output at a predetermined period. Appears once. The combination of feedback points in this case is called a primary combination. This is an ideal feature of a pseudo-random pattern generator, which is why many LFSRs are used.

On the other hand, as a configuration of a compressor applicable to both a memory BIST and a logic BIST, a MISR (Multiple Input
Signature Register) is often used. The MISR has the same basic configuration as the LFSR, but differs from the LFSR in that input data is taken in parallel.

FIG. 10 is a diagram showing a configuration example of an 8-bit MISR. The MISR of FIG. 10 includes eight registers REG1 to REG8.
Are connected in cascade with EXOR gates G10 and G10 'interposed therebetween. Each of the registers REG1 to REG8 performs a shift operation by a common clock CLK. Some EXOR gates G10 'act as feedback points, and calculate the exclusive OR of the corresponding data in the parallel input data D21 to D28, the output of the preceding register, and the output of the last register REG8. Then, the operation result is input to the register of the next stage. The other EXOR gate G10 calculates the exclusive OR of the corresponding data in the parallel input data D21 to D28 and the output of the register at the preceding stage, and inputs the result to the register at the next stage.

When performing data compression, first, the outputs of the registers REG1 to REG8 are initialized to a predetermined value (usually all 0s), and then the parallel input data D21 to D28 are sequentially taken in synchronization with the clock CLK. While compressing. Each register REG at the end of all data input
Outputs of 1 to REG8 are compression results. By comparing this compression result with an expected value calculated in advance, the quality of the test block is determined.

The output of each register when the input of all data is completed is called a signature, and the process of analyzing the compression result is called a signature analysis. In an N-bit MISR, the probability that a single fault existing in a test block is overlooked due to loss of information (alias) due to compression is about 1 / ^2N , and when N is sufficiently large (for example, 16 or 3).
2), the loss of information due to compression can be almost ignored. Thus, MISR, combined with its structural simplicity, has desirable features for use as a compressor.

A system LSI is composed of a plurality of blocks having different functions and different scales, and it is necessary to select a different method and level for each block in the design for testability. For example, for embedded memory blocks, there are cutout to external terminals by a multiplexer, memory BIST, etc.
For a logical block, there are a full scan, a partial scan, a logic BIST, and the like.

Of the above-described test-easiness design methods, the memory BIST and the logic BIST require less test pins and do not require a test pattern generator externally. It is easier to integrate (share) than.

For example, when there are a plurality of blocks having BIST circuits in a system LSI, each BIST circuit can be shared. LFSR functioning as a pattern generator and MI functioning as a compressor as one method of sharing
BI that provides SR for each block and controls LFSR and MISR
A method of sharing only the ST control circuit can be considered.

FIG. 11 shows a plurality of memory devices 61 and 6.
FIG. 3 is a diagram illustrating an example of a system LSI in which a common memory BIST control circuit 63 is provided for 2 and a common logic BIST control circuit 66 is provided for a plurality of logic blocks 64 and 65. As shown, the BIST control circuits 63 and 66
, The circuit size of the BIST control circuit can be reduced.

For further sharing, LFSR and MISR
Must be shared by a plurality of blocks under test, in which case there are some problems. The biggest problem among them is that the required bit width and feedback point differ depending on the block under test.

The simplest method for testing a plurality of blocks under test having different bit widths in a single BIST is the BIST according to the block under test having the maximum bit width.
Is determined. For example, FIG. 12 shows an example in which an input bit width of 4 bits, 5 bits, and 8 bits is used to test three logic blocks 71 to 73.
It is a figure showing the example which arranged LFSR74.

The 8-bit width LFSR is primary to the block under test 73 also having the 8-bit width, and can generate all the 8-bit patterns input to the block 73 under test. However, this LFSR
Cannot generate all the patterns input to the 4-bit and 5-bit width logical blocks 71 and 72 in FIG. 12 without duplication, and are not suitable as a generator of a pseudo-random number pattern.

[0020]

In order to solve the above problem, it is necessary to change the bit width of the LFSR according to the block to be tested. Also, if the bit width of the LFSR is different, the combination of the feedback points also changes. Therefore, it is necessary to change the combination of the feedback points according to the block under test.

FIG. 13 shows three logical blocks 7 of FIG.
It is a figure which shows an example of LFSR which set the bit width and the feedback point so that the corresponding LFSR may become primary with respect to each of 1-73. LFSR75 of FIG.
Has multiplexers MPX11 and MPX12, and the multiplexers MPX11 and MPX12 are provided with an external configuration selection signal SEL.
Either input A or B is selected by the logic of SEL1 and SEL2. Thereby, the bit width is set. The position of the feedback point is also set by the configuration selection signals SEL1 and SEL2.

For example, when the configuration selection signal is (1, 0),
Each of the multiplexers MPX11 and MPX12 selects the input A.
The output of the ND gate G12 is "0", and the AND gates G11 and G1
3, the output of G14 has the same logic as the register output of the last stage. Therefore, the circuit of FIG.
It is the primary LFSR with feedback points at 1, 5, and 6 bit positions.

When the configuration selection signal is (0, 1), 5
It is a primary LFSR having a bit width (5 inputs) and a feedback point at 0 and 2 bit positions. In the case of the configuration selection signal (0,0), it is a 4 bit width (4 inputs) and
It becomes the primary LFSR with a feedback point at one bit position.

As shown in FIG. 13, the multiplexer MPX1
If logic circuits such as 1 and 12 and AND gates G11 to G13 are provided,
An LFSR whose configuration can be switched according to the block under test is obtained.

However, when the number of blocks to be tested increases, the types of primary LFSRs also increase, which complicates the circuit. Further, since the configuration of the BIST circuit largely depends on the configuration of the block under test, if the configuration of the block under test changes, the configuration of the BIST circuit must also change accordingly. That is, the circuit of FIG. 13 is difficult to reuse for different blocks under test, and the circuit must be configured for each block under test.
Design costs and manufacturing costs are increased.

Further, in the circuit shown in FIG. 13, once the LFSR circuit is constructed, the combination of the feedback points is changed, and the work for improving the detection rate cannot be performed by finding the combination having the highest failure detection rate.

[0027] The present invention has been made in view of the above points, and its object is to provide:
It is an object of the present invention to provide a semiconductor integrated circuit device in which the bit width and the feedback point of a linear feedback shift register can be arbitrarily changed and the reusability is high.

[0028]

In order to solve the above-mentioned problems, the invention according to claim 1 comprises a plurality of registers cascaded and operated by a common clock, and at least one portion between stages of the plurality of registers. And a feedback point for inputting a result obtained by calculating an exclusive OR between the register output of the previous stage and the register output of the final stage to the register of the next stage, the semiconductor integrated circuit having a linear feedback shift register. The apparatus comprises a plurality of switching circuits provided between stages of each register in the linear feedback shift register, wherein each of the switching circuits is based on a first control signal corresponding to each switching circuit. Switching whether or not to set the feedback point, the linear feedback
The shift register generates a test pattern based on the feedback point set by the switching circuit.

According to a second aspect of the present invention, there are provided a plurality of registers connected in cascade and operated by a common clock, and a register output of a preceding stage and a register output of a last stage provided at at least one position between stages of the plurality of registers. And a feedback point for inputting the result of the exclusive-OR operation to the next-stage register, and a linear feedback shift register having a linear feedback shift register. A plurality of switching circuits provided between the stages,
Each of the switching circuits is a first switching circuit corresponding to each switching circuit.
Switching whether or not to set the feedback point, based on the control signal, the linear feedback shift register inputs signals between stages of the respective registers based on the feedback point set by the switching circuit. Compression of the first input data to be performed.

The "first control signal" in claim 1 corresponds to, for example, the parallel input data S11 to S17 in FIG.

The "switching circuit" of claim 3 corresponds to the first switching circuit 1 'of FIG. 6, and the "second control signal" corresponds to, for example, FIG.
And the "shift selection circuit" corresponds to the multiplexers MPX21 to MPX28.

The "input selection circuit" according to claim 4 is, for example, a circuit shown in FIG.
Corresponding to the AND gates G41 to G48.

The "register dividing circuit" of claim 5 corresponds to, for example, the AND gate G5 of FIG. 7, and the "third control signal" is A
Corresponds to the ND gate control signal GCTRL3.

The "stage number setting circuit" according to claim 6 is, for example, as shown in FIG.
And the "fourth control signal" corresponds to the bit width setting signals D31 to D37.

The present invention also provides a plurality of registers connected in cascade and operated by a common clock, and a register provided at at least one position between stages of the plurality of registers. And a feedback point for inputting the result of the exclusive OR operation to the next-stage register. In the semiconductor integrated circuit device having the linear feedback shift register, the stage of each register in the linear feedback shift register A plurality of switching circuits respectively provided between the switching circuits, wherein each of the switching circuits inputs an output of a previous-stage register to a next-stage register based on a first control signal corresponding to each of the switching circuits, or Whether the exclusive OR of the output of the previous register and the output of the last register is input to the next register To choose.

The present invention also provides a plurality of registers connected in cascade and operated by a common clock, and a register provided at at least one position between the stages of the plurality of registers, wherein a register output of a preceding stage and a register output of a final stage are provided. And a feedback point for inputting the result of the exclusive OR operation to the next-stage register. In the semiconductor integrated circuit device having the linear feedback shift register, the stage of each register in the linear feedback shift register A plurality of switching circuits provided between the respective registers, each of the switching circuits being based on a first control signal corresponding to each of the switching circuits, the first input data being input between the stages of each of the registers. The exclusive-OR of the output of the previous stage register and the output of the previous stage register, or Choose whether to enter the exclusive OR of the output of the register over data and the previous register and the output of the last stage to the next register.

The present invention also provides a plurality of registers connected in cascade and operated by a common clock, and a register provided at at least one position between the stages of the plurality of registers, wherein a register output of a preceding stage and a register output of a final stage are provided. And a feedback point for inputting the result of the exclusive OR operation to the next-stage register. In the semiconductor integrated circuit device having the linear feedback shift register, the stage of each register in the linear feedback shift register A plurality of first multiplexers provided in correspondence with each of the registers except the last-stage register in the linear feedback shift register, the plurality of first multiplexers being cascaded; A plurality of switching control signals for switching control of each of the multiplexers are output. And a switching control signal output circuit that switches the output of the preceding register based on a first control signal corresponding to each switching circuit. Select whether to input to the next-stage register or input the exclusive OR of the output of the previous-stage register and the output of the first-stage first multiplexer to the next-stage register. The connected switching circuit inputs the output of the previous-stage register to the final-stage register based on the first control signal, or exclusive-connects the output of the previous-stage register with the output of the final-stage register. Whether the logical OR is to be input to the final stage register, the output of the final stage first multiplexer is input to the initial stage register, and that of the first multiplexer excluding the initial stage. That is, based on the corresponding switching control signal, one of the output of the corresponding register and the output of the first multiplexer of the preceding stage is selected, and the first multiplexer of the first stage selects the corresponding switching control signal. Based on the logic of the signal, one of the output of each register of the last stage and the preceding stage is selected.

The "first multiplexer" corresponds to, for example, the multiplexers MPX11 to MPX17 in FIG. 4, the "switch control signal" corresponds to the bit width setting signals D31 to D37, and the "switch control signal output circuit" determines the register length. Corresponds to circuit 2.

Further, the present invention provides a plurality of registers cascaded and operated by a common clock, and a register provided at at least one position between the stages of the plurality of registers. And a feedback point for inputting the result of the exclusive OR operation to the next-stage register. In the semiconductor integrated circuit device having the linear feedback shift register, the stage of each register in the linear feedback shift register A plurality of first multiplexers provided in correspondence with each of the registers except the last-stage register in the linear feedback shift register, the plurality of first multiplexers being cascaded; A plurality of switching control signals for switching control of each of the multiplexers are output. And a switching control signal output circuit that performs switching control signals other than the switching circuits connected to the register at the final stage. The switching circuits correspond to each switching circuit based on a first control signal corresponding to each switching circuit. The exclusive OR of the first input data and the output of the previous stage register is input to the next stage register, or the corresponding first input data, the output of the previous stage register and the output of the last stage register To select whether to input the exclusive OR with the next stage register, the output of the last stage first multiplexer is input to the first stage register, and each of the first multiplexers except the first stage has: Based on the logic of the corresponding switching control signal, one of the output of the corresponding register and the output of the first multiplexer of the preceding stage is selected, and the first multiplexer of the first stage selects a pair. On the basis of the logic of the switching control signal for the final stage and selects one of the register output of the previous stage.

The present invention also provides a plurality of registers cascaded and operated by a common clock, and at least one register between stages of the plurality of registers, wherein a register output of a preceding stage and a register output of a final stage are provided. And a feedback point for inputting the result of the exclusive OR operation to the next-stage register. In the semiconductor integrated circuit device having the linear feedback shift register, the stage of each register in the linear feedback shift register A plurality of switching circuits respectively provided between the first and second registers, and a plurality of cascade-connected first multiplexers provided corresponding to each register except the last-stage register in the linear feedback shift register; A feedback shift register is provided corresponding to each register. A plurality of second multiplexers connected to an input terminal of a star, and a switching control signal output circuit for outputting a plurality of switching control signals for switching control of each of the first multiplexers; Are respectively based on a first control signal corresponding to each switching circuit, and the second multiplexer corresponding to an exclusive OR of first input data corresponding to each switching circuit and an output of a register in a preceding stage. Or the exclusive OR of the corresponding first input data, the output of the previous-stage register and the output of the final-stage register,
, The output of the first multiplexer at the last stage is input to the register at the first stage, and each of the first multiplexers except the first stage outputs a logic signal corresponding to the switching control signal. Based on the output of the corresponding register or the output of the first multiplexer of the preceding stage, and the first multiplexer of the first stage selects the output of the last stage based on the logic of the corresponding switching control signal. The second multiplexer selects one of the register outputs at the preceding stage, and the second multiplexer outputs one of the corresponding output of the switching circuit and the corresponding first input data based on a second control signal. Select

The "second multiplexer" corresponds to, for example, the multiplexers MPX21 to MPX28 in FIG.

The present invention further includes a register dividing circuit connected to at least one portion between the stages of the plurality of cascaded registers, wherein the register dividing circuit operates based on a division control signal. It switches between inputting the output of the register to the next-stage register or inputting a signal of a predetermined logic to the next-stage register.

The "register division circuit" is, for example, an AND of FIG.
The “division control signal” corresponds to the gate G5, and corresponds to the AND gate control signal GTRL3.

[0044]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit device according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device according to the present invention includes a shift register 101 that can arbitrarily change a bit width and a position of a feedback point, and a register configuration control circuit 102 that sets the bit width and the position of a feedback point of the shift register 101. . The register configuration control circuit 102 sets the bit width and the position of the feedback point based on the parallel control data S11 to S1n supplied from the outside and the parallel control data S11 to S1n output from a shift register (not shown).

The shift register 101 shown in FIG. 1 generates a test pattern for testing the block under test 103 based on the set bit width and the feedback point, and fetches a test result from the block under test 103. Performs the analysis of the test results.

Hereinafter, the specific configuration of FIG. 1 will be described.

(First Embodiment) In the first embodiment, an LFSR capable of arbitrarily setting a feedback point is configured.

FIG. 2 is a circuit diagram of the first embodiment of the semiconductor integrated circuit, showing the configuration of the LFSR. LFSR in Fig. 2
Has a plurality of cascaded registers REG1 to REG8 and a switching circuit 1 connected between the stages of the registers REG1 to REG8. The combination of these registers REG1 to REG8 and the switching circuit 1 corresponds to the shift register 101 in FIG.

The LFSR of FIG. 2 sets a feedback point at an arbitrary position between the registers REG1 to REG8 by arbitrarily setting the logic of the parallel control data S11 to S17 supplied from the outside.

Each of the registers REG1 to REG8 has a clock CLK.
Works in sync with. The corresponding data in the parallel control data S11 to S17 from the outside and the output of the register REG8 of the last stage are input to each of the switching circuits 1. Each of the switching circuits 1 includes an AND gate G1 and an EXOR gate G
2, the corresponding data in the parallel control data S11 to S17 is input to one input terminal of the AND gate G1, and the output of the register REG8 of the last stage is input to the other input terminal. The output of the corresponding AND gate G1 is input to one input terminal of the EXOR gate G2, and the output of the preceding register is input to the other input terminal. Each EXOR
The output of the gate G2 is input to an input terminal of a register at a subsequent stage.

When the corresponding data in the parallel control data S11 to S17 is "0", the data is input.
The output of the AND gate G1 becomes low level and the corresponding EXO
From the R gate G2, the output of the previous register is output as it is. On the other hand, when the corresponding data in the parallel control data S11 to S17 is "1", the output of the final stage register REG8 is output as it is from the AND gate G1 to which the data is input, and the corresponding EXOR gate G2 is AN
An exclusive OR of the output of the D gate G1 and the output of the preceding register is output. That is, the parallel control data S11 to
When the corresponding data in S17 is "1", the EXOR gate G2 functions as a feedback point.

As described above, the circuit shown in FIG. 2 arbitrarily sets the logic of the parallel control data S11 to S17 supplied from the outside, so that a plurality of cascaded registers REG can be connected.
A feedback point can be set at any position of 1 to REG8.

Further, in the circuit of FIG. 2, after assembling the circuit once, the feedback point can be arbitrarily changed by changing the logic of the parallel control data S11 to S17. Therefore, it is possible to generate a plurality of different types of test patterns without changing the circuit configuration, and it is possible to generate an optimal pattern according to the type of the block under test. Further, since there is no need to change the circuit configuration even if the type of the block under test changes, the design cost can be reduced and a circuit having high reusability can be obtained.

The test pattern generated by the circuit of FIG. 2 is taken out serially from the output terminal of the final stage register REG8, or the test pattern of each stage register REG1 to REG
8 is taken out in parallel from the output terminal.

In the circuit of FIG. 2, an example has been described in which parallel control data S11 to S17 are input from the outside. However, a shift register is provided in the same semiconductor chip, and parallel control data S11 to S17 are generated by this shift register. You may.

In FIG. 2, eight registers REG1-R
Although an example in which the EG 8 is connected is shown, the number of register connection stages is not particularly limited.

(Second Embodiment) In a second embodiment, a MISR in which a feedback point can be set arbitrarily is constructed.

FIG. 3 is a circuit diagram of a second embodiment of the semiconductor integrated circuit, showing the configuration of the MISR. MISR of FIG.
Is a plurality of cascaded registers REG as in FIG.
1 to REG8, and a switching circuit 1 connected between the stages of the registers REG1 to REG8. The switching circuit 1 receives parallel control data S11 to S17 for setting the position of the feedback point and parallel input data D21 to D28 for data compression.

Each of the switching circuits 1 includes an AND gate G1
And an EXOR gate G3. The EXOR gate G3 is connected to the output of the corresponding AND gate G1 and the parallel input data D21.
The exclusive OR of the corresponding data in .about.D28 and the register output of the preceding stage is calculated. The output of the EXOR gate G3 is input to the next stage register.

For example, when the corresponding data in the parallel control data is "1", the corresponding EXOR gate G3 functions as a feedback point.

When operating the circuit of FIG. 3, first, the parallel input data D21 to D28 are all initialized to "0", and a feedback point is set by the parallel control data S11 to S17.

Next, data compression processing is performed while taking in the parallel input data D21 to D28 in synchronization with the clock CLK. The output (signature) of each of the registers REG1 to REG8 at the time when the data compression process is completed is taken out in parallel from the output terminal of each of the registers REG1 to REG8, or is sequentially shifted by the clock CLK to register the final register REG8. Is taken out serially. The compression result taken out to the outside is compared with an expected value set in advance, and the quality of the test block is determined.

As described above, according to the second embodiment, an arbitrary position between a plurality of cascade-connected registers REG1 to REG8 can be set by arbitrarily setting the bit string of the parallel control data S11 to S17 supplied from the outside. Since the feedback point can be set for the parallel input data D21 to D28 supplied from the outside, data compression can be performed with a different configuration. Therefore, a plurality of compression results can be obtained for the same input pattern, and the failure oversight rate due to compression can be reduced.

(Third Embodiment) In the third embodiment, the LFSR is configured so that not only the position of the feedback point but also the bit width can be varied.

FIG. 4 is a circuit diagram of a third embodiment of the semiconductor integrated circuit, showing the configuration of the LFSR. LFSR in Fig. 4
Is a plurality of cascaded registers REG as in FIG.
1 to REG8, a switching circuit 1 connected between the stages of the registers REG1 to REG8, and a register length for outputting a signal for setting a bit width (hereinafter, a bit width setting signal) D31 to D37. It has a decision circuit 2.

The switching circuit 1 shown in FIG. 4 has AND gates G1 and EXOR gates G2 similarly to FIG. 1, and also has cascaded multiplexers MPX11 to MPX17. The multiplexers MPX11 to MPX17 are provided corresponding to the respective registers except the register REG8 at the last stage, and switch according to the corresponding bit width setting signal. Last stage multiplexer MPX11
Is input to the first-stage register REG1, and the multiplexers MPX other than the final-stage and first-stage multiplexers MPX11 and MPX17.
Each of 12 to MPX16 selects one of the corresponding register and the output of the preceding-stage multiplexer based on the corresponding bit width setting signal. The first-stage multiplexer MPX17 selects one of the outputs of the last stage and the registers REG7 and REG8 of the preceding stage based on the corresponding bit width setting signal D31.

In the circuit of FIG. 4, the parallel control data S11
Through S19, a bit string (characteristic polynomial) for selecting a feedback point is supplied. The parallel control data S11 to S19 may be supplied from outside the chip, or may be generated by a shift register provided in the chip.

When parallel control data is generated by the shift register, for example, the bit width is set to “6”, and 0,
In order to provide a feedback point at the second and third bits, data "001001101" is serially input from the last stage (MSB) of the shift register. The register length determination circuit 2 determines the bit width based on the bit position where the value “1” first appears, and outputs a corresponding bit width setting signal. In this case, since the bit width is "6", only the bit width setting signal D36 corresponding to the multiplexer MPX16 has a value "1", and all other signals have a value "0". Of the parallel control data S11 to S19, data other than the least significant bit data and the most significant bit data are input to the switching circuit 1 and used to set a feedback point. As a result, when the bit width is “6”, 0, 2, 3
An LFSR having a feedback point at the bit is obtained.

In the circuit of FIG. 4, when an LFSR having an 8-bit width is formed, for example, data "101100011" is serially input such that the MSB of the shift register for setting the feedback point becomes "1". In this case, the bit width setting signals output from the register length determination circuit 2 are all "0", all the registers REG1 to REG8 are selected, and an LFSR having an 8-bit width is obtained.

As described above, the circuit of FIG. 4 uses the logic of the parallel control data S11 to S19 supplied from the outside to
Since the bit width of the SR and the position of the feedback point can be set arbitrarily, the optimum bit width for the block under test can be selected without changing the circuit configuration, and an ideal test pattern can be generated.

(Fourth Embodiment) In a fourth embodiment, a MISR in which a feedback point can be set arbitrarily is constructed. The MISR of FIG. 5 is the same as the circuit of the third embodiment shown in FIG. 4 except that the parallel input data D21 to D28 are externally supplied to the EXOR gate G3 in the switching circuit 1.

The MISR shown in FIG. 5 performs data compression processing while taking in parallel input data D21 to D28, as in the second embodiment shown in FIG. The output of each register REG1 to REG8 at the end of the test is the compression result (signature)
The compression result is output between the registers or from the output terminal of the register REG8 at the last stage.

As described above, the circuit of FIG. 5 uses the logic of the externally supplied parallel control data S11 to S19 to perform the MF operation.
Since the bit width of the SR and the position of the feedback point can be set arbitrarily, it is possible to perform pattern compression of different configurations for the same input pattern, and reduce the failure oversight rate due to compression.

(Fifth Embodiment) In the fifth embodiment, in addition to the configuration of the fourth embodiment, shifting between the registers REG1 to REG8 without compressing the externally input parallel input data. Is made possible.

The MISR of FIG. 6 includes a first switching circuit 1 'having the same configuration as the switching circuit of FIG. 1 and the like, and multiplexers MPX21 to MPX28 connected to the input terminals of the registers REG1 to REG8. Each of the multiplexers MPX21 to MPX28 selects one of the corresponding data in the parallel input data D21 to D28 and the output of the EXOR gate G3 according to the logic of the shift enable signal ENBL supplied from the outside.

When the shift enable signal ENBL is set to low level, the operation is performed in the same manner as in FIG. That is, MISR having a bit width and a feedback point according to the bit string of the parallel control data S11 to S19 is obtained.

In order to perform the failure analysis operation by the circuit of FIG. 6, first, the parallel control data S11 to S17 are set to all 0s. In this state, when the clock CLK is supplied while the shift enable signal ENBL is fixed at "1", the parallel input data D21 to D28 are directly stored in the register REG1.
REG8. Thereafter, when the shift enable signal ENBL is set to "0", the shift mode is set, and the outputs of the registers REG1 to REG8 are sequentially shifted in synchronization with the clock CLK, and are taken out of the final stage register REG8. This makes it possible to easily and accurately check which output has an error at which time. That is, each register REG1 at any time during the test is
REG8 output can be tested. In addition, the value during compression can be externally observed.

In the shift mode, the output of the register REG8 at the last stage of the circuit of FIG. 6 is directly input to the register REG1 at the first stage. To REG8 are the same as before the shift operation. In this state, by setting the shift enable signal ENBL to "1" again, the test can be restarted from the point at which the test was interrupted.

As described above, the circuit of FIG. 6 can arbitrarily set the bit width of MISR and the feedback point position by the bit string of the parallel control data S11 to S19, and shift the parallel input data D21 to D28 sequentially without compression. Since the shift mode is provided, the work of analyzing the failure of the block under test can be made much more efficient.

(Sixth Embodiment) In the sixth embodiment, the bit width and the feedback point position can be arbitrarily changed, the register group can be divided into a plurality of registers, and a pattern generator and a pattern compressor are used. They can be configured at the same time.

The circuit shown in FIG. 7 has a plurality of circuits for switching between generating a test pattern and compressing an input pattern.
It has AND gates G41 to G48 and an AND gate G5 for switching whether or not to divide the register group into two. The AND gates G41 to G44 perform a switching operation according to the AND gate control signal GCTRL1, and the AND gates G45 to G48 perform the AND gate control signal GC.
The switching operation is performed by TRL2. AND gate G5 is AN
When the D gate control signal GCTRL3 is at a low level, the register groups REG1 to REG8 are divided into two.

When the AND gate control signal GCTRL3 is at a high level, the circuit of FIG. 7 operates as a single LFSR. At this time, if the AND gate control signals GCTRL1 and GCTRL1 are at a low level, a test pattern is generated. When the AND gate control signals GCTRL1 and GCTRL2 are at a high level, the circuit operates as a MISR that performs a compression operation while taking in the parallel input data D21 to D28.

When the AND gate control signal GCTRL3 is at the low level, the register groups REG1 to REG8 store the 4-bit LFSR2
Divided into pieces. At this time, the AND gate control signal GCTRL
The logic of 1, 2 determines whether each of the divided parts operates as a normal LFSR or MISR.

As described above, the circuit shown in FIG. 7 can constitute an 8-bit width test pattern generator or an 8-bit width pattern compressor and a 4-bit width test circuit by the logic of the AND gate control signals GCTRL1 to GCTRL3. Pattern generator and 4
It is also possible to simultaneously configure a bit width pattern compressor. That is, the circuit of FIG. 7 can simultaneously perform pattern generation and pattern compression.

FIG. 7 shows an example in which the LFSR is divided into two LFSRs. However, if two or more AND gates G5 are provided, the LFSR can be divided into three or more LFSRs.

[0087]

As described above in detail, according to the present invention, a feedback point can be set at an arbitrary position between the stages of the register according to the logic of the first control signal. An optimal test pattern can be generated. Further, since various test patterns can be generated only by changing the logic of the first control signal without changing the circuit configuration, the test circuit can be shared,
A test circuit with high reusability is obtained.

Further, since the position of the feedback point can be set arbitrarily when compressing the input data, data compression of a different configuration can be performed for the same test pattern, and the failure oversight rate due to compression can be reduced. Can be reduced.

Further, since the number of registers in the linear feedback shift register can be arbitrarily set by the number-of-stages setting circuit, the test of various test blocks having different numbers of input / output terminals can be performed without changing the circuit configuration. It can be carried out.

Further, since the first input data input for data compression can be shifted between the registers without compression, the output of the block under test under test can be sequentially observed, Each register output during compression can be sequentially observed. After the observation, the test can be continued by switching the shift selection circuit. Thereby, the failure analysis work of the block under test can be performed efficiently.

Further, since the cascade-connected registers can be divided into a plurality of blocks by the register dividing circuit, a plurality of pattern generators and pattern compressors having different bit widths and feedback point positions can be simultaneously operated from the cascade-connected registers. The test pattern generation and the pattern compression can be performed at the same time. As a result, different tests can be simultaneously performed on the same or a plurality of blocks under test, and the tests can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a circuit diagram of a first embodiment of a semiconductor integrated circuit.

FIG. 3 is a circuit diagram of a second embodiment of a semiconductor integrated circuit.

FIG. 4 is a circuit diagram of a third embodiment of a semiconductor integrated circuit.

FIG. 5 is a circuit diagram of a semiconductor integrated circuit according to a fourth embodiment.

FIG. 6 is a circuit diagram of a fifth embodiment of a semiconductor integrated circuit.

FIG. 7 is a circuit diagram of a semiconductor integrated circuit according to a sixth embodiment;

FIG. 8 is a general configuration diagram of BIST.

FIG. 9 is a diagram showing a configuration example of an 8-bit LFSR.

FIG. 10 is a diagram showing a configuration example of an 8-bit MISR.

FIG. 11 is a diagram showing an example of a system LSI sharing a BIST control circuit.

FIG. 12 is a diagram showing an example in which an LFSR having an 8-bit width is arranged for a plurality of logical blocks having different bit widths.

FIG. 13 is a diagram showing an example of an LFSR in which a bit width and a feedback point are set so that the LFSR becomes primary.

[Explanation of symbols]

 Reference Signs List 1 switching circuit 2 register length judgment circuit 101 shift register 102 register configuration control circuit 103 block under test REG1 to REG8 register MPX11 to 17, MPX21 to 28 multiplexer S11 to S19 parallel control data D21 to D28 parallel input data D31 to D37 bit width setting signal

Claims (6)

[Claims] 1. A plurality of registers cascaded and operated by a common clock, and an exclusive OR of a register output of a preceding stage and a register output of a last stage provided at at least one position between stages of the plurality of registers. And a feedback point for inputting the result of the calculation to the next stage register, and a linear feedback shift register having the following: a feedback point provided between the registers in the linear feedback shift register. A plurality of switching circuits, wherein each of the switching circuits is a first switching circuit corresponding to each switching circuit.
Based on the control signal, switches whether or not to set the feedback point, the linear feedback shift register generates a test pattern based on the feedback point set by the switching circuit. A semiconductor integrated circuit device characterized by the above-mentioned. 2. A plurality of registers cascaded and operated by a common clock, and an exclusive OR of a register output of a preceding stage and a register output of a last stage provided at at least one position between stages of the plurality of registers. And a feedback point for inputting the result of the calculation to the next stage register, and a linear feedback shift register having the following: a feedback point provided between the registers in the linear feedback shift register. A plurality of switching circuits, wherein each of the switching circuits is a first switching circuit corresponding to each switching circuit.
Based on the control signal, whether to set the feedback point or not, the linear feedback shift register, based on the feedback point set by the switching circuit, the input between each stage of each register A first integrated data to be compressed. 3. A shift selector for switching between inputting the output of the switching circuit to the next-stage register and inputting the corresponding first input data to the next-stage register based on a second control signal. Wherein the linear feedback shift register sequentially shifts between the registers in the linear feedback shift register without compressing the first input data when the second control signal has a predetermined logic. 3. The semiconductor integrated circuit device according to claim 2, wherein: 4. An input selection circuit for selecting whether to input the first input data between stages of each register in the linear feedback shift register, wherein the linear feedback shift register comprises: When the input selection circuit selects the input of the first input data, the compression of the first input data is performed, and when the selection of not inputting the first input data is performed, 4. The semiconductor integrated circuit device according to claim 2, wherein the device generates a test pattern. 5. A register dividing circuit connected to at least one portion between stages of the plurality of cascade-connected registers, wherein the register dividing circuit is configured to cascade-connect when a third control signal has a predetermined logic. 5. The semiconductor integrated circuit device according to claim 2, wherein the plurality of registers are divided into the plurality of linear feedback shift registers for generating a test pattern or compressing input data. . 6. The linear control circuit according to a fourth control signal.
6. The semiconductor integrated circuit device according to claim 1, further comprising a stage number setting circuit for setting the number of stages of the register in the feedback shift register.