JP3179646B2 - Shared test register and built-in self-test circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shared test register for facilitating test of an integrated circuit and a built-in self test (BIST) circuit using the same.

[0002]

2. Description of the Related Art As one method for facilitating the test of an integrated circuit, a compact test method in which a tester function (test pattern generator, pattern compressor, comparator, expected value) is incorporated in the same integrated circuit. Embedded self-test circuits are known. In order to achieve high fault coverage and short test time for larger and more complex integrated circuits,
The above-described pattern generator, a distributed configuration in which a plurality of pattern compressors are mounted in an integrated circuit is becoming essential.As the distributed configuration, a part of a register used for normal operation in the integrated circuit is used. There has been known a method of increasing testability by replacing a common test register which is switched between a normal operation and a test operation by mode selection. As a conventional example of a distributed built-in self-test circuit, a built-in logic block which performs a normal register operation, a shift operation, an initialization, a pattern generation, and a pattern compression (time compression) by mode switching as a shared test register is used.
Observations (BILBO: Built-In Logic-Block Obser
vation), a method of sequentially testing the logic blocks surrounded by the BILBO register while switching the above-mentioned modes is known (reference: Kone).
mann B., Muncha J. and Zwiehoff G .: “Built-In Log
ic Block Observation Techniques ”, IEEE Int. Test
Conference, pp37-41 (1979)). However, since it is necessary to use a linear feedback shift register type multi-function register cell as a plurality of BILBO registers mounted in the integrated circuit, there is a problem that an additional circuit added for the test becomes large. Further, in order to test all blocks in the integrated circuit, a plurality of test procedures are required, so that there is a problem that a test control circuit becomes complicated.

[0005] As a technique that can easily configure a test control circuit as compared with the BILBO technique, a self-test pass register 73 is used as a shared test register.
A configuration in which they are connected by one circulation path 74 is known. Fig. 7 shows the overall configuration of a conventional built-in self-test circuit (Reference: Krasniewski A. and Albicki A .: "C
ircular Self-Test Path: A Low-Cost BIST Technique
for VLSI Circuits ”, IEEE Trans. on CAD, Vol.8, N
o.1, pp.46-55 (1989)). By simultaneously operating the self-test path register 73 as a pattern compressor (time compressor) for the circuit under test on the input side of the register and a test pattern generator for the circuit under test on the output side, the test procedure can be performed in one test procedure. All blocks in the integrated circuit 78 can be tested, and a simple test control circuit can be configured. However, since all the self-test pass registers 73 are connected by one circulation path 74, it is difficult to apply the self-test pass register 73 to a multi-cycle circuit in which the clock cycle of each self-test pass register is different. On the other hand, there is a problem that it is difficult to guarantee timing because the number of registers to be simultaneously shifted is increased. In addition, since the self-test pass register 73 directly performs time compression with a large degree of compression, the self-test pass register 7 is used to reduce the failure mask rate in the compressor.
As the third problem, there is a problem that a configuration having a large amount of hardware having a feedback line, such as a multiple input signature register (MISR) and a feedback shift register, must be used. In Reference 2, a feedback shift register is used as the self-test pass register 73. However, in order to reduce the failure mask rate, it is necessary to increase the number of expected value comparisons compared to a multiple input signature register (MISR). There is a problem that the expected value vector becomes large.

[0004]

As the scale of an integrated circuit increases, power consumption tends to increase. Instead of operating the entire integrated circuit in one clock cycle, each functional block is required to meet its required performance. The number of multi-cycle circuits that operate in a clock cycle that has been seen is increasing. For this reason, it is desired that a test simplification technique can be applied to a multi-cycle circuit. As the scale of integrated circuits has increased, it has become difficult to guarantee timing during shift operations of registers. A level-sensitive scanning method in which a shift operation is guaranteed by two shift-dedicated clocks is known, but requires a large amount of hardware. For this reason, in the built-in self-test method, a configuration that can easily guarantee timing without using the level-sensitive scanning method is desired. As a test process when testing an integrated circuit using the built-in self-test circuit, the design, built-in,
Although there is a test execution step, it is desired to reduce the number of steps in order to reduce test costs. Of these, the design,
In order to reduce the number of man-hours for assembling, it is necessary to have a configuration capable of standardizing and simplifying all parts constituting the built-in self test circuit. In particular, a configuration that can standardize and simplify a test control circuit that requires design man-hours is required. Also at the manufacturing stage,
In order to facilitate the test execution at the system stage, it is desired to have a configuration in which an expected value is mounted in an integrated circuit and a pass / fail result can be output inside the integrated circuit without using a tester. If the chip area is increased by adding the hardware for the built-in self-test, the yield of the integrated circuit is directly reduced. Therefore, it is desired to reduce the amount of additional hardware for the built-in self-test as much as possible. For this reason, it is necessary that a shared test register, which is mounted in a plurality of integrated circuits and causes an increase in additional circuits, can be realized by a circuit with as little hardware as possible.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has been made in order to solve the problems. An object of the present invention is to provide an integrated self-test circuit for facilitating the test of an integrated circuit. Provides a shared test register that can be applied to multi-cycle circuits, facilitates timing assurance, and improves test man-hours.
Another object is to provide a built-in self-test circuit which requires less additional circuits for testing in addition to such improvements.

[0006]

According to the shared test register of the present invention for achieving one of the above objects, for example, as shown in FIG. 1, N (N is an arbitrary natural number) data input lines 32 A register 33 having one mode switching input line 34, N data output lines 36, and a test information output line 35 is connected to a circuit under test, for example, 31, 37, and the data input line 32 and the data output line 36. Of the register 33 in the circuit configuration connected via
It operates as an N-bit width register. In the test mode, information stored in the N-bit width register is input by N-bit × t pattern (t is the number of test patterns) input information output from the circuit to be tested in the preceding stage. In the integrated test register 33 of the integrated circuit for outputting the test circuit of the next stage as a test pattern of N bits × t pattern, the shared test register 33 includes N pieces of N test pieces arranged close to each other at the time of layout. For example, the memory elements are constituted by flip-flop storage elements, the N storage elements operate in the same clock cycle, and the test information output line comprises a single spatial compression output line 35. Information of N bits × t pattern in mode is 1 bit ×
The spatial compression output line 3 is obtained by spatially compressing the
5 is provided.

In the built-in self-test circuit of the present invention for attaining the above another object, for example, as shown in FIG. 2, an integrated circuit has L (L is an arbitrary natural number) of the above spaces. Shared test register 12 (R
3, R7, R8), an L-bit width time compressor 16 composed of, for example, a flip-flop storage element that operates in a clock cycle that is the least common multiple of the clock cycle given to each of the shared test registers, A test control circuit 17 is provided, and L spatial compression output lines (13) output from the L shared test registers 12 having a lower degree of compression than the time compressor are connected to the time compressor 16. In the time compressor 16, the information of the L bit × t pattern (t is the number of test patterns) is compared with the L bit × p pattern (p is the number of times of comparison with the expected value of the L bit width, p <
The test control circuit 17 compares the compressed information with an expected value and outputs a pass / fail result to the outside of the integrated circuit (110).

[0008]

According to the shared test register of the present invention, one shared test register is constituted by using N storage elements (flip-flops) arranged in close proximity at the time of layout. , It is possible to suppress the deviation of the clock applied to the clock and to easily guarantee the timing. According to the shared test register of the present invention, all blocks in the integrated circuit are tested in a single test procedure by simultaneously operating the shared test register as a test pattern generator and a space compressor in the test mode. Will be possible. Therefore, the test control circuit can be easily configured, and the number of test steps is reduced. Further, in the shared test register of the present invention, the storage circuit constituting the shared test register operates at the same clock cycle, so that a test circuit using the same is suitable for a multi-cycle circuit as described later. Such a base will be provided.

In the built-in self-test circuit of the present invention,
Pattern compression is performed in two stages, that is, spatial compression and time compression using a shared test register, and the spatial compressor (shared test register) uses only storage elements (flip-flops) that operate in clock cycles of the same frequency. When configured, the time compressor can be applied to a multi-cycle circuit by operating only with a storage element (flip-flop) operating at a clock cycle that is the least common multiple of the clock cycle given to each shared test register. . Further, in the built-in self-test circuit of the present invention, as a shared test register which is mounted in a large number on the integrated circuit and causes an increase in the number of additional test circuits, the pattern compression degree is large and the amount of hardware required to suppress the failure mask rate is low. Rather than using a time compressor that requires a large configuration, a spatial compressor that has a small pattern compression degree and can keep the failure mask rate low with a small amount of hardware is used. By using a compressor such as a signature register (MISR), the amount of hardware of the shared register can be reduced,
This makes it possible to reduce the amount of hardware of the entire test additional circuit. Further, according to the built-in self-test circuit of the present invention, the use of the shared test register having a small clock shift facilitates the incorporation of the self-test circuit whose timing is easily guaranteed. Further, according to the built-in self-test circuit of the present invention, the expected value and the comparison circuit are mounted in the integrated circuit, and the pass / fail result is determined inside the integrated circuit. Can be easily performed.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a basic configuration of a shared test register of the present invention, and FIG. 2 is a diagram showing an entire configuration of a built-in self-test circuit according to the present invention. As shown in FIG.
The built-in self-test circuit according to the present invention is usually a type 1 type of register / pattern generator switching type for self-test.
, A normal register / pattern generator + space compressor switchable type 2 shared test register 12, a time compressor 16, and a test control circuit 17. Among them, the shared test register of the present invention shown in FIG. 1 is a shared test register 12 of type 2, and the shared test register 11 of type 1 is shown in FIG. 4 to 6 show an embodiment of the shared test register of the present invention.

First, the shared test register 12 of type 2 shown in FIG. 1 has N data input lines 3 (N is an arbitrary natural number).
2, has one mode switching input line 34, N data output lines 36, and one spatial compression output line 35. In the normal mode, it operates as an N-bit width register used for normal operation. In the mode, N bits output from the test target circuit 31 at the preceding stage (N is the number of outputs of the test target circuit)
Information of × t pattern (t is the number of test patterns) is 1 × t
At the same time as compressing the information and outputting it from the spatial compression output line 35, it has a function of outputting the information stored in the N-bit width register as a test pattern for the test target circuit 37 in the next stage.

In FIG. 2, the type 1 shared test register 11 is mounted in an integrated circuit 116 in such a manner that a register (or a boundary scan register) directly connected to an external input 113 is replaced. Also type 1
The shared test register 11 operates in the same clock cycle during normal operation, and is configured for about 20 to 30 storage elements (flip-flops) belonging to a layout block capable of guaranteeing timing. In addition, there are N shared test registers 11 of type 1 (N is an arbitrary natural number).
It has a data input line, one mode switching input line, and N data output lines. In the normal mode, it operates as an N-bit width register used for normal operation. It has a function as a test pattern generator for the target circuit.

The type 2 shared test register 12 is an integrated circuit that replaces a part of a register surrounded by a combinational logic circuit 115 and a register (or a boundary scan register) directly connected to an external output. It is mounted in 116. As a register surrounded by the combinational logic circuit 115, a register having poor controllability and observability in a random number pattern is selected. Generally, a state control register or the like is given as an example. Further, a register that allows the integrated circuit to be divided into sub-blocks of an appropriate size is selected to facilitate evaluation such as calculation of a fault coverage. Also,
The type-2 shared test register 12 operates in the same clock cycle during normal operation, and is configured for each of about 20 to 30 storage elements (flip-flops) belonging to a layout block capable of guaranteeing timing.

The time compressor 16 uses an L-bit (L is the number of type-2 shared test registers) multi-input signature register (MISR). Information of L bits (L is the number of circuits to be tested) × t patterns (t is the number of test patterns) output from the space compression output line 13 of the all-shared test register is time-compressed into L × p pattern information. . Here, p (arbitrary natural number) is the number of comparisons with the expected value, and the failure mask rate of the other input signature register is 1 / (2L)
Therefore, when L becomes 20 to 30 bits or less, MI
The value of L × p is set to 30 or more from the viewpoints of both the fact that the failure mask rate in SR becomes remarkable and that the defective shipment rate is set to a target of, for example, 1 / 100,000. The time compressor 16 operates in the same clock cycle during normal operation, and is configured for each of about 20 to 30 storage elements (flip-flops) belonging to a layout block capable of guaranteeing timing. Also, if the entire integrated circuit operates in multiple clock cycles,
The time compressor 16 is operated in a clock cycle that is the least common multiple of each clock cycle.

The test control circuit 17 receives a test circuit activation signal 18 from outside the integrated circuit 116, initializes all registers in the integrated circuit by the initialization signal line 15, and initializes all shared type circuits by the test mode signal line 14. The test register is switched to the test mode to perform pattern generation and compression. After t periods (t is the number of test patterns), the output of the time compressor 16 is compared with an expected value, and the end signal 19 and the result determination signal 110 are integrated. Output to outside 116. The type 2 shared test register 12 controlled by the test control circuit 17
Operates simultaneously as a pattern generator and a pattern compressor, so the above-mentioned activation, initialization, pattern generation / compression,
The pass / fail determination can be performed in one test procedure, and the configuration of the test control circuit 17 is simplified as compared with a test that requires a plurality of test procedures such as the BILBO method.

FIG. 3 shows a shared test register 1 of type 1.
1 shows a configuration example. Type 1 shared test register 11
Is composed of N storage elements 23, N shift data / normal input data selection elements 24, and O (O is an integer of 1 to 3) exclusive OR elements 25. Shift data
The normal input data selection element 24 is connected to the mode switching input line 2
2, the data input line 21 is selected in the normal mode, and data shifted from the preceding storage element 24 is selected in the test mode. Further, the shared test register 11 of the type 1 has a plurality of feedback lines 26 in which a primitive polynomial is a generating polynomial as a position to be fed back, and operates as a linear feedback shift register (LFSR) in a test mode. A pseudo-random pattern of the maximum length sequence is given to the circuit to be tested in the next stage.

FIG. 4 shows a configuration example 1 (feedback type) of the shared test register 12 of the type 2 described above. The shared test register 12 of type 2 in FIG. 4 is configured using N test register cells 43. The test register cells 43 are connected by a shift line 410. The output of the last-stage test register cell 43 _n is coupled to the first-stage test register cell 43 _l by a feedback line, and further output as a space compression output line 47. The test register cell 43 includes a storage element 44, a two-input logic element 45,
The shift data / fixed value selection element 46 is used.
The shift data / fixed value selection element 46 applies a fixed value to the two-input logic element 45 in the normal mode by a signal supplied from the mode switching input line 42,
1 so as to be directly supplied to the storage element 44,
In the test mode, an operation is performed so that the value obtained by taking the logic of the data shifted from the test register cell 43 in the preceding stage and the data input 41 is given to the storage element 44. The two-input logic element 45 is configured by any one of a logical sum, a logical product, an exclusive logical sum, and their negation.

As another configuration of the above-mentioned feedback type, as shown in FIG. 5, a plurality of feedback lines 58 in which a primitive polynomial is a generator polynomial are provided as feedback positions, and an exclusive OR is used as a two-input logic element. Configuration 2 (MISR type) that operates as a multi-input signature register in the test mode using the element 55 is used.

FIG. 6 shows a configuration example 3 (no feedback type) of the shared test register 12 of type 2 described above.
The shared test register 12 of type 2 in FIG. 6 includes one normal register cell 63 and N−1 test register cells 6
The normal register cell 63 and the test register cells 64 are connected by a shift line 610. The output of the test register cell 64 _{n-1 at} the final stage is output as the space compression output line 68. The normal register cell 63 selects one of the outputs 32 of the circuit under test at the preceding stage that is randomly connected to the output having a high rate of inversion of 0 or 1. The test register cell 64 includes a storage element 65, a two-input logic element 66, and a shift data / fixed value selection element 67. The shift data / fixed value selection element 67 supplies a fixed value to the two-input logic element 66 in the normal mode by a signal supplied from the mode switching input line 62 so that the data input 61 is directly supplied to the storage element 65. In the test mode, the normal register cell 63 in the preceding stage operates.
Alternatively, the operation is performed so that a value obtained by taking the logic of the data shifted from the test register cell 64 and the data input 61 is given to the storage element. The two-input logic element 66 is configured by any one of a logical sum, a logical product, an exclusive logical sum, and their negation.

Next, additional items concerning application to a multi-cycle circuit, timing assurance, and a shared test register of type 2 will be described. (Application to Multi-Cycle Circuit) As described above, when the entire integrated circuit operates in a plurality of clock cycles, the type 1 shared test register 11 and the type 2 shared test register 12 operate normally. Sometimes it is configured for each storage element (flip-flop) that operates in the same clock cycle. The time compressor 16 is operated with a clock that is the least common multiple of each clock cycle. Thereby, the shift operation between the flip-flops constituting the type 1 shared test register 11, the type 2 shared test register 12, and the time compressor 16 is performed in the same clock cycle. Since the shift operation from the shared test register 12 to the time compressor 16 is always performed from the flip-flop of a low clock cycle to the flip-flop of a high clock cycle, information is lost during the shift operation. Does not occur. On the other hand, in the conventional method, all the registers are combined and shifted by one circulation path 74. Therefore, when the entire integrated circuit is operated in a plurality of clock cycles, the flip-flop of the high clock cycle is switched to the flip-flop of the low clock cycle. Since the shift operation to the flip-flop is performed, information is lost during the shift operation, and the failure mask rate in the compressor increases.

(Timing Assurance) As described above,
The shared test register 11 of type 1, the shared test register 12 of type 2 and the time compressor 16 each belong to a layout block capable of guaranteeing timing.
From 30 to about 30 storage elements (flip-flops). Regarding the timing guarantee between the flip-flops constituting the type 1 shared test register 11, the type 2 shared test register 12 and the time compressor 16, the flip-flops constituting the various test registers are 1, 2 Since the logic elements of the stages are arranged, there is a hold margin corresponding to the delay time of the logic elements. Therefore, in order to guarantee the timing, the dispersion of the clock applied to each flip-flop of the test register is held. What is necessary is just to keep it within the margin. Various test registers are configured in order to easily specify a layout block whose skew is guaranteed within the delay time of one or two stages of logic elements by clock design such as making the clock wiring length uniform or driving with the same driver. The flip-flop belongs to the above-mentioned layout block in which the timing can be guaranteed, and the timing can be easily guaranteed by suppressing the number to about 20 to 30. Also, type 2
As for the timing guarantee for the shift operation from the shared test register 12 to the time compressor 16, the clock assumed between the layout block including the type 2 shared test register 12 and the layout block including the time compressor 16 is assumed. This can be easily achieved by inserting a delay element corresponding to the variation between the common test register 12 of type 2 and the time compressor 16.

(Type 2 Shared Type Test Register) As described above, the type 2 shared type test register 12 has a feedback type, a MISR type or a no feedback type as a whole configuration, and has a logic as a two-input logic element. Any one of a sum, a logical product, an exclusive logical sum, and their negation is selected and configured.
The amount of hardware increases in the order of no-feedback type, feedback type, and MISR type, and becomes the largest when the exclusive OR and its negation are used as the two-input logic element. Type 2 shared test register 12
Function as a spatial compressor for the circuit under test 31 at the preceding stage and a test pattern generator for the circuit under test 37 at the next stage, as described above. It is necessary to select in consideration of the effect masking rate) and the test pattern efficiency of the test pattern generator (how much a highly random pattern is generated). Regarding the failure mask rate of the type 2 shared test register 12 as a spatial compressor, the final stage test register cells 43 _n , 53 _n , 64
_{Since the} compressed value is output in the entire test cycle from the spatial compression output lines 47, 57, 68 connected to the _n−1 , the failure occurs in the final stage test register cells 43 _n , 53 _n , 64 _n−1 even once. It is sufficient that the influence propagates, and there is no difference in the failure mask rate between the feedback type and the no feedback type. When exclusive OR or its negation is used as the two-input logic elements 45 and 66, in order to generate a fault mask, if an abnormal output is propagated from the test target circuit 31 in the previous stage in a certain cycle, By the time the output is shifted to the final-stage test register cells 43 _n , 53 _n , and 64 _n−1 , a new abnormal output that cancels the abnormal output needs to be propagated, so the failure mask rate is extremely low. . When a logical sum or its negation is used, when an abnormal output propagates from the test circuit 31 in the preceding stage in a certain cycle, even if an abnormal output that cancels out the influence does not come, a probability of 1/2 during the shift operation is obtained. Therefore, the failure mask rate is higher than that in the case of using exclusive OR or its negation. Regarding the test pattern efficiency of the type 2 shared test register 12 as a test pattern generator, various patterns are propagated from the test circuit 31 in the preceding stage, If the rate of random or total inversion is high at all or a part, the output is connected to the normal register cell 63 so that the test circuit 37 of the next stage can be connected to the next-stage test circuit 37 even if the no feedback type A pattern with high test pattern efficiency can be generated. When the output of the circuit under test 31 at the preceding stage is randomly low at 0 or 1 inversion, the no-feedback type increases the rate at which a fixed pattern is generated, and reduces test pattern efficiency. It is necessary to use a mold. In the case of a feedback type in which a fixed value is propagated in almost all test cycles from all outputs of the test target circuit 31 in the preceding stage, the pattern of the bit width number of the shared test register is repeated in the simple feedback type. Gets worse. Therefore, it is necessary to use the MISR type. When the logical sum, the logical product or its negation is used as the two-input logical elements 45 and 66, 0 or 1 is generated in the test register cell as compared with the case where the exclusive OR or its negation is used. The probability increases and the pattern efficiency decreases.

As described above, each type 2 of the shared test register 1
Considering the features of (2), first, feedback type, MIS
The R-type or no-feedback type is selected by using the no-feedback type when the rate of all or a part of the output of the circuit under test 31 at the front stage is randomly toggled high. If the rate at which all outputs of T.31 randomly toggle is uniformly low, a feedback type is used. If a fixed value propagates in most cycles from all outputs of the circuit under test 31 in the preceding stage, M
ISR type is used.

Next, when selecting the two-input logic elements 45 and 66, a large number of patterns having a high fault detection rate are given to the circuit under test 31 in the preceding stage, and the influence of the fault propagates to the output of the circuit under test, and This is used when the test target circuit 37 at the next stage can obtain a high fault detection rate even with a pattern having a low test pattern efficiency.

In the present invention, only spatial compression is performed as the pattern compression of the shared test register. Therefore, in the shared test register, pattern compression of about tens of minutes (the number of registers constituting the shared test register is several tens ), And as described above, in many cases, a shared test register with a small amount of hardware can be used, depending on the characteristics of the circuit to be tested connected to the previous and next stages. On the other hand, in the method of performing time compression directly with a shared test register as in the conventional method, it is necessary to perform pattern compression of several millionths (the number of test cycles is set to several millions) with a shared test register. Yes, in order to avoid a failure mask,
Regardless of the characteristics of the circuit to be tested connected to the preceding stage and the next stage, a compressor with a large amount of hardware such as a multi-input signature register (MISR) or a feedback type and using an exclusive-OR element as a two-input logical element Must be used.

[0026]

As described above, according to the built-in self-test circuit using the shared test register of the present invention, it is applicable to a multi-cycle circuit, the timing is easily guaranteed, the number of test steps is small, and A built-in self-test circuit for an integrated circuit with few additional circuits for testing can be realized.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a type 2 shared test register of the present invention.

FIG. 2 is an overall configuration diagram of a built-in self-test circuit according to the present invention.

FIG. 3 is a diagram showing a configuration example of a type 1 shared test register.

FIG. 4 is a diagram showing a configuration example 1 (feedback type) of a shared test register of type 2;

FIG. 5 shows a configuration example 2 (M
FIG.

FIG. 6 is a diagram showing a configuration example 3 (no feedback type) of a shared test register of type 2;

FIG. 7 is an overall configuration diagram of a conventional built-in self-test circuit.

[Explanation of symbols]

11: Shared test register (pattern generation) 12: Shared test register (pattern generation, space compression) 13: Space compression output line 14 ...
Mode switching signal 15 ... Initialization signal 16 ...
Time compressor 17 ... Built-in self-test control circuit 18 ...
Test circuit start signal 19 ... End signal 110 ...
Result judgment signal 111: Normal register 112
… Normal path 113… External input 114
... External output 115 ... Combination circuit 116
... Integrated circuit 31 ... Test target circuit at the previous stage 32 ...
Data input line 33: Shared test register (pattern generation, spatial compression) 34: Mode switching input line 35
Spatial compression output line 36 ... data output line 37 ...
Test circuit of next stage

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-62-49273 (JP, A) JP-A-63-286780 (JP, A) JP-A-1-221686 (JP, A) JP-A-5- 66249 (JP, A) JP-A-5-81855 (JP, A) JP-A-5-249197 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28-31 / 3193

Claims (2)

(57) [Claims] A register having N data input lines (N is an arbitrary natural number), one mode switching input line, N data output lines, and test information output lines is referred to as a circuit to be tested. In the circuit configuration connected via the data input line and the data output line, the register is operated as an N-bit width register in the normal mode, and is output from the circuit to be tested in the preceding stage in the test mode. N
An integrated circuit that outputs information stored in an N-bit width register in response to input information of a bit × t pattern (t is the number of test patterns) to a test circuit of the next stage as an N-bit × t pattern test pattern In the shared test register, the shared test register includes N storage elements arranged close to each other at the time of layout, and the N storage elements operate in the same clock cycle. The information output line has a structure composed of one spatial compression output line. The information of the N bits × t pattern in the test mode is spatially compressed into the information of 1 bit × t pattern and output from the spatial compression output line. A shared test register, comprising a configuration of a spatial compressor. 2. An integrated circuit comprising: L (L is an arbitrary natural number) shared test registers according to claim 1; and a clock cycle which is a least common multiple of clock cycles applied to each of said shared test registers. A space compressor output line output from the L shared test registers having a lower compression ratio than the time compressor, comprising: L lines are connected to the above-mentioned time compressor, and in this time compressor, information of L bits × t patterns (t is the number of test patterns) is compared with L bits × p patterns (p is the number of times the expected value of L bit width is compared) , P << t >> (a natural number of t), the compressed information is compared with an expected value in the test control circuit, and a pass / fail result is output outside the integrated circuit. Self-contained self-test circuit.