JP2001237379A - Circuit for testing integrated circuit and testing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit for testing an integrated circuit and a testing method thereof whereby the scale of test circuits for activating internal circuits does not increase in accelerated tests of the integrated circuit, and circuits for testing it can be easily changed even after completion of the integrated circuit design. SOLUTION: A random number generator circuit (LFSR) 2 is composed of signal feedback circuits 7a-7c connected from the input of a scan chain circuit 10 composed of a plurality of series connected flip-flops 9 for testing internal circuits of an integrated circuit to the same number (8 in Fig.1) of the flip-flops as the bit number of psendo random number data, and the random number generator circuit 2 generates and transmits psendo random number data to the scan chain circuit 10. Thus, it shares the flip flops being common parts of the circuit LFSR 2 with the scan chain circuit 10 and hence the increase of circuits can be minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a test circuit and a test method for an integrated circuit including a scan chain circuit and a pseudo random number generation circuit.

[0002]

2. Description of the Related Art In a reliability test of a semiconductor integrated circuit, in order to detect a defective product before shipment and ship a highly reliable product, a power supply terminal of the semiconductor integrated circuit is subjected to a voltage higher than a rated voltage in a high temperature environment. There is an accelerated test that applies a high voltage to stress a circuit. When performing an acceleration test on a semiconductor integrated circuit, a dynamic acceleration test, which is a test for actually operating the semiconductor integrated circuit and detecting a failure mode peculiar to the operation, is effective.

Generally, in order to perform a dynamic acceleration test of a semiconductor integrated circuit, it is necessary to input various logic signals from external input terminals of the semiconductor integrated circuit. These logic signals are usually generated using a test pattern generator. However, since the accelerated test apparatus including the test pattern generator is expensive, there is a problem that the test cost of the semiconductor integrated circuit is increased.

As a means for solving this problem, a linear feedback shift register (hereinafter, referred to as L) serving as a pseudo random number generation circuit as a test pattern generation circuit is provided in an internal circuit of a semiconductor integrated circuit.
Called FSR. ) Is incorporated in advance. According to this method, especially in a full scan circuit, an internal circuit can be easily activated only by inputting a pseudo random number from a scan input unit. Therefore, a method of incorporating the LFSR into the circuit has been considered effective.

[0005] FIG. 7 shows L which outputs an 8-bit pseudo random number.
FIG. 3 is a block diagram illustrating an example of a test circuit of a semiconductor integrated circuit incorporating an FSR. In the integrated circuit 61, a plurality of scan flip-flops 69 form a scan chain circuit 70 in which input terminals and output terminals are connected in series. The output side of each scan flip-flop 69 constituting the scan chain circuit 70 is connected to combinational logic circuits 71a to 71c which are internal circuits. A multiplexer 68 is connected to an input side of the scan flip-flop 69a which is an input side of the scan chain circuit 70. The LFSR 62 and the scan-in terminal 63 as an input terminal are connected to the multiplexer 68. In addition, a predetermined signal is input from the mode terminal 64, and the connection between the LFSR 62 and the scan-in terminal 63 is switched.

The LFSR 62 connects input terminals and output terminals of eight flip-flops 72 in series, respectively.
EXOR gates 67a to 67 which are exclusive OR gates
This is a configuration in which a signal is fed back by c. That is, EX is connected to the output side of the flip-flops 72 of the seventh and eighth stages.
The input terminals of the OR gate 67c are connected to each other. One of the input terminals of the EXOR gate 67b is connected to the output terminal of the EXOR gate 67c, and the other is
It is connected to the output side of the flip-flop 72 of the stage. Further, one of the input terminals of the EXOR gate 67a is connected to the output terminal of the EXOR gate 67b, and the other is connected to the output side of the third-stage flip-flop 72. The output terminal of the EXOR gate 67a is connected to the input terminal of the first-stage flip-flop 72.

The CLK terminal 65 is connected to clock pins (not shown) of all the scan flip-flops 69 and all the flip-flops 72 included in the integrated circuit 61.

In the burn-in mode in which a voltage higher than the rated voltage is applied, the LFSR 6 is switched by the multiplexer 68 which switches the input to the scan chain circuit 70.
2 is set in each scan flip-flop 69 using the scan chain circuit 70. That is, by inputting a clock signal from the CLK terminal 65, pseudo random number data is input from the LFSR 62 to the scan chain circuit 70, and the scan flip-flop 6 connected to the scan chain 70
At 9, the shift operation is performed in order.

Next, FIG. 8 is a block diagram showing an example in which the LFSR is incorporated in a multi-scan circuit having a plurality of scan chains. In the integrated circuit 81,
A plurality of scan flip-flops 89 are connected in series to form five scan chain circuits 95 to 99, and the input side of each scan chain circuit is provided with multiplexers 88a to 88e. The integrated circuit 81
Has an LFSR 82 for inputting a pseudo-random number to each scan chain circuit.

The LFSR 82 has, for example, a structure in which an 8-bit pseudo random number is generated, and input terminals and output terminals of eight flip-flops 92 are connected in series. Then, the flip-flops 92 of the seventh and eighth stages
Are connected to the input terminals of the EXOR gate 87c. One of the input terminals of the EXOR gate 87b is connected to the output terminal of the EXOR gate 87c, and the other is connected to the output side of the fifth-stage flip-flop 92. Further, one input terminal of the EXOR gate 87a is connected to the output terminal of the EXOR gate 87b, and the other is connected to the output side of the third-stage flip-flop 92. The output terminal of the EXOR gate 87a is connected to the input terminal of the first-stage flip-flop 92.

Each of the multiplexers 88a to 88e has two input terminals. The one input terminal is connected to each of the scan-in terminals 83a to 83e. The other input terminal is connected to the output side of each flip-flop 92 included in the LFSR 82.

That is, the input terminal of the multiplexer 88a is connected to the output side of the eighth stage flip-flop 92 of the LFSR 82. The input terminal of the multiplexer 88b is connected to the output side of the seventh-stage flip-flop 92 of the LFSR 82. The input terminal of the multiplexer 88c is connected to the flip-flop 92 of the sixth stage of the LFSR 82.
Is connected to the output side. The input terminal of the multiplexer 88d is connected to the fifth flip-flop 9 of the LFSR 82.
2 is connected to the output side. The input terminal of the multiplexer 88e is connected to the output side of the fourth stage flip-flop 92 of the LFSR 82.

The CLK terminal 85 is connected to clock pins of all scan flip-flops 89 and all flip-flops 82 included in the integrated circuit 81.

In the burn-in mode in which a voltage higher than the rated voltage is applied, the signals of the LFSR 82 are converted by the multiplexers 88a to 88e for switching the inputs of the scan chain circuits 95 to 99.
In this embodiment, each scan flip-flop 89 is set using the reference numeral 99. That is, the CLK terminal 8
5, the clock signal is input from the LFSR8.
2 to pseudo-random number data from scan chain circuits 95 to 9
The shift operation is sequentially performed in the scan flip-flops 89 input to the scan chain circuit 9 and connected to each scan chain circuit.

In the configurations shown in FIGS. 7 and 8, how many types of data can be generated is determined by the number of bits of the flip-flop (register) constituting the LFSR which is a pseudo random number generation circuit. For example, in the case of an 8-bit register configuration, there are 255 kinds of generated data excluding “00000000”. The greater the number of bits in the register of the LFSR, the more kinds of pseudo-random numbers can be generated. When a semiconductor integrated circuit is tested using this data, the use of more types of data increases the activation rate inside the semiconductor integrated circuit and increases the reliability of the accelerated test.

[0016]

As described above, at the time of an acceleration test of a semiconductor integrated circuit 61 having a built-in scan chain circuit shown in FIG. Incorporation inside eliminates the need for using an accelerated test apparatus having a test pattern generator. However, this configuration has a problem that the number of circuits increases by the amount of the LFSR.

In order to improve the reliability of the integrated circuit, it is necessary to input more data by increasing the number of LFSR resist steps. However, if the number of LFSR registers is increased, the circuit scale is further increased, which leads to an increase in cost.

Further, in the case of a semiconductor integrated circuit in which a scan chain circuit is built in a large-scale circuit, such as an integrated circuit 81 having a plurality of scan chains shown in FIG. In many cases, a multi-scan method is used in which scan operations can be performed in parallel using the scan chains. In this case, there are a method of providing LFSRs for an acceleration test in a plurality of circuits, and a method of transmitting a pseudo random number from one LFSR to each scan chain via a multiplexer. However, any of the methods has a disadvantage that the number of test circuits increases. Further, in the above method, the activation circuit for multi-scan needs to be incorporated at the time of designing an integrated circuit, and there is a disadvantage that the circuit portion to be activated cannot be changed during the production of the integrated circuit.

In addition, in order to set an initial value in a register of the LFSR at the time of starting, it is necessary to provide a terminal for an initial circuit from the outside in the acceleration test apparatus and to input a signal for initialization at the start of the acceleration test. . Therefore, the configuration of the burn-in board for the acceleration test becomes complicated. Further, there is a disadvantage that the procedure of the accelerated test is increased by one operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the scale of a test circuit for activating an internal circuit during an accelerated test of a semiconductor integrated circuit. An object of the present invention is to provide a test circuit and a test method for an integrated circuit in which a circuit section to be tested can be easily changed even after completion of circuit design.

[0021]

[Means for Solving the Problem] (1) A scan chain circuit in which a plurality of flip-flops are connected in series to test an internal circuit, and a random number which generates pseudo-random number data and transmits the data to the scan chain circuit A test circuit for an integrated circuit comprising: a signal feedback circuit connected to the same number of flip-flops as the number of bits of the pseudo-random number data from the input side of the scan chain circuit. It is characterized by the following.

In this configuration, in order to test the internal circuit, a signal feedback circuit is provided from the input side of a scan chain circuit in which a plurality of flip-flops are connected in series to the same number of flip-flops as the number of pseudo random number data. Connected to form a random number generation circuit, generate pseudo random number data, and transmit it to the scan chain circuit. Therefore, by sharing the flip-flop, which is a common part of the scan chain circuit and the LFSR circuit, the number of circuits can be minimized. Another feature is that increasing the number of bits in the LFSR register has almost no effect on the increase in the number of circuits.

(2) A plurality of scan chain circuits in which a plurality of flip-flops are connected in series to test an internal circuit, and a random number generation circuit for transmitting pseudo random number data to the scan chain circuit are provided. In the test circuit of the integrated circuit, the random number generating circuit is configured by connecting a signal feedback circuit from the input side of one scan chain circuit to the same number of flip-flops as the number of bits of the pseudo random number data. .

In this configuration, among a plurality of scan chain circuits in which a plurality of flip-flops are connected in series to test an internal circuit, the same number as the number of bits of pseudo random number data is input from one input side of one circuit. And a signal feedback circuit is connected to the flip-flop to form a random number generation circuit. Therefore, by sharing the flip-flop, which is a common part of the scan chain circuit and the LFSR circuit, the number of circuits can be minimized.

(3) There is provided a return circuit for outputting a return signal to the random number generation circuit to restart the operation when the random number generation circuit stops operating.

In this configuration, the test circuit of the integrated circuit includes a return circuit that outputs a return signal when the operation of the random number generation circuit stops. Therefore, when the random number generation circuit becomes inoperable and stops, the return signal is output from the recovery circuit, so that the initialization processing of the random number generation circuit does not have to be performed.

(4) In a test method of an integrated circuit for testing an internal circuit by inputting pseudo-random number data to a scan chain circuit formed by connecting a plurality of flip-flops in series,
A signal feedback circuit is connected from the input side of the scan chain circuit to the same number of flip-flops as the number of bits of the pseudo random number data to form a random number generation circuit, and an initial value is input to the random number generation circuit to convert the pseudo random number data. It is generated and input to a scan chain circuit.

In this configuration, a signal feedback circuit is connected from the input side of a scan chain circuit in which a plurality of flip-flops are serially integrated to the same number of flip-flops as the number of bits of the pseudo-random number data, thereby forming a random number generation circuit. The pseudo random number data is generated by inputting an initial value to the random number generation circuit and input to the scan chain circuit. Therefore, the test of the integrated circuit can be easily performed by inputting the initial value without increasing the scale of the test circuit of the integrated circuit.

(5) In an integrated circuit test method for inputting pseudo-random number data to a plurality of scan chain circuits each having a plurality of flip-flops connected in series and testing an internal circuit, one circuit among a plurality of scan chain circuits is provided. A signal feedback circuit is connected to the same number of flip-flops as the number of bits of the pseudo-random number data from the input side to generate pseudo-random number data, and another scan chain circuit is connected to the output side of the scan chain circuit to which the signal feedback circuit is connected. And a circuit in which the input terminal and the output terminal are connected in series, and pseudo-random data is input to a plurality of scan chain circuits.

In this configuration, a signal feedback circuit is connected to the same number of flip-flops as the number of bits of the pseudo random number data from the input side of one of the scan chain circuits in which a plurality of flip-flops are connected in series. Generate pseudo-random number data, and connect a circuit in which the input terminal and the output terminal of another scan chain circuit are connected in series to the output side of the scan chain circuit to which this signal feedback circuit is connected, and test the scan circuit. Do. Therefore, one of the scan chain circuits can be used as a pseudo-random number generation circuit and a plurality of other scan circuits can be tested, so that the test can be performed with a minimum scale of the test circuit.

(6) In the configuration of (3), the return circuit connects the input terminal of the NOR logic gate to the output side of a plurality of flip-flops constituting the scan chain circuit, and outputs the output terminal of the signal feedback circuit. And the output terminal of the NOR logic gate may be connected to an OR logic gate.

In this configuration, when the random number generation circuit stops operating, the return circuit that generates a return signal is a NOR circuit.
The input terminal of the logic gate is connected to the output side of a plurality of flip-flops constituting the scan chain circuit, and the output terminal of the signal feedback circuit and the output terminal of the NOR logic gate are connected to O.
It is connected to the R logic gate. Therefore, the random number generation circuit has a property of being inoperable only when all the values of the resist have become 0. To escape from this state, N
By using an OR logic gate and an OR logic gate,
It is possible to reliably recover from the inoperable state.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a test circuit for an integrated circuit according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a test circuit for an integrated circuit according to the first embodiment of the present invention. The integrated circuit 1 includes a scan chain circuit 10 to which a plurality of scan flip-flops 9 are connected. The output side of each scan flip-flop 9 constituting the scan chain circuit 10 is connected to combinational logic circuits 11a to 11c. The multiplexer 8 is connected to the input side of the scan flip-flop 9a, which is the input side of the scan chain circuit 10. The multiplexer 8 has a scan-in terminal 3
And the output terminal of the EXOR gate 7 and the mode terminal 4 are connected. When a predetermined signal is input from the mode terminal 4, the connection between the scan-in terminal 3 and the LFSR 2 can be switched.

In this embodiment, as a configuration for generating a pseudo-random number, scan flip-flops 9 connected in the same number as the number of bits of the pseudo-random number are provided.
The LFSR 2 is formed by using it as a shift resist.
In FIG. 1, 8-bit pseudo random number data is generated by LFSR2.

In the scan flip-flop 9 constituting the LFSR 2, three EXOR gates 7a to 7c, which are exclusive OR gates, are connected to the output side of each scan flip-flop 9 as in FIG. A circuit is configured. That is, the input terminal of the EXOR gate 7c is connected to the output side of the scan flip-flops 9 of the seventh and eighth stages constituting the LFSR2. Also, EXOR
One of the input terminals of the gate 7b is connected to the output terminal of the EXOR gate 7c, and the other is connected to the output side of the fifth-stage scan flip-flop 9. In addition, EXO
One input terminal of the R gate 7a is an EXOR gate 7b
And the other is connected to the output side of the third-stage scan flip-flop 9. And EX
The output terminal of the OR gate 7a is connected to the input terminal of the multiplexer 8.

The CLK terminal 5 is connected to a clock pin (not shown) of all the scan flip-flops 9 included in the integrated circuit 1. Then, by inputting a clock signal from the CLK terminal 5, the scan chain circuit 10
The data is sequentially shifted in the scan flip-flop 9 connected to.

In a normal scan test, the mode terminal 4
, And data is input from the scan input terminal 3 via the multiplexer 8. Then, a clock signal is input from the CLK terminal 5 and data is set in the scan flip-flop 9 by a shift operation.

In the acceleration test, a signal is input from the mode terminal 4 to switch the multiplexer 8 to the EXO of the LFSR 2.
Switch to the connection side of the R gate 7, and use the pseudo random number data generated in the LFSR2. Here, since all the scan flip-flops 9 in the integrated circuit 1 are connected to the scan chain circuit 10, the data created in the LFSR2, which is a pseudo-random number circuit, is sequentially propagated. Therefore, the combinational logic circuits 11a to 11c connected to the scan flip-flop 9 perform various operations by changing the data of all the scan flip-flops 9 by the pseudo random numbers. Therefore, the entire internal circuit of the integrated circuit 1 is activated, and the acceleration test can be effectively performed.

Next, a procedure for performing an acceleration test in the circuit of FIG. 1 will be described with reference to FIG. FIG. 5 is a flowchart showing the procedure of the acceleration test of the semiconductor integrated circuit 1. First, a voltage is supplied to a power supply terminal (not shown) of the integrated circuit 1 (s1). Then, a predetermined signal is input from the mode terminal 4 and the multiplexer 8 is switched to receive a signal from the scan-in terminal 3 (s2). Also,
An initial value for initializing the LFSR 2 is input from the scan-in terminal 3 (s3).

Next, a signal is input from the mode terminal 4 so as to receive the pseudo-random number data generated by the LFSR 2, and the connection of the multiplexer 8 is switched (s4). Then, the integrated circuit 1 is operated for a predetermined time under a high temperature environment (s5). After a predetermined time has elapsed, the operation of the integrated circuit is stopped. Then, the quality of the integrated circuit 1 is determined by the tester. That is, it is tested whether or not the integrated circuit has been destroyed due to the application of the stress, and the non-defective integrated circuit is shipped.

Next, a description will be given of a case where the present invention is applied to an integrated circuit including a multi-scan type test circuit in the integrated circuit test circuit according to the second embodiment of the present invention.
FIG. 2 is a block diagram showing a test circuit of an integrated circuit having a plurality of scan chains according to a second embodiment of the present invention. The integrated circuit 21 includes five scan chain circuits 35 to 39 each including a plurality of scan flip-flops 29 connected in series. Scan flip-flop 29a on the input side of scan chain circuit 35
Is connected to a multiplexer 28.
In the integrated circuit 21, in order to generate pseudo-random data of 8 bits, the flip-flops 29a to 29 of the first stage of the scan chain circuit 35 to the eighth stage and the eight flip-flops are provided. Three exclusive OR gates E as connected signal feedback circuits
XOR gates 27a to 27c, and LFSR 22
Is configured. That is, the input terminal of the EXOR gate 27c is connected to the output side of the scan flip-flops 29 of the seventh and eighth stages constituting the LFSR 22. One of the input terminals of the EXOR gate 27b is EXO.
The other end is connected to the output terminal of the scan flip-flop 29 at the fifth stage. Further, one input terminal of the EXOR gate 27a is connected to the output terminal of the EXOR gate 27b, and the other is connected to the output side of the third-stage scan flip-flop 29. The output terminal of the EXOR gate 27a is connected to the input terminal of the multiplexer 28.
The other input terminal of the multiplexer 28 is connected to the scan-in terminal 23a. Further, a switching signal terminal of the multiplexer 28 is connected to the mode terminal 24.

The output side of the scan chain circuit 35 is connected to the scan-out terminal 26a. The input terminals of the scan chain circuits 36 to 39 are connected to the scan-in terminals 23b to 23e, respectively. Further, the output sides of the scan chain circuits 36 to 39 are connected to the scan out terminals 26b to 26e, respectively. In addition, combination logic circuits 31a to 31e are connected to the scan chain circuits 35 to 39, respectively.

When performing the acceleration test of the integrated circuit 21, each input terminal and each output terminal of the scan chain circuit are connected to each other by wiring on a burn-in board for the acceleration test. That is, the scan-out terminal 26a of the scan chain circuit 35 and the scan-in terminal 23b of the scan chain circuit 36 are connected by the wiring 40a.
Also, the scan-out terminal 26b of the scan chain circuit 36 and the scan-in terminal 23c of the scan chain circuit 37 are connected by a wiring 40b. Further, a scan-out terminal 26c of the scan chain circuit 37, a scan-in terminal 23d of the scan chain circuit 38,
Are connected by a wiring 40c. In addition, the scan-out terminal 26d of the scan chain circuit 38 and the scan-in terminal 23e of the scan chain circuit 39 are connected to the wiring 40d.
Connect with. With this connection, the pseudo-random number data generated by the LFSR 22 provided in the scan chain circuit 35 propagates to the scan chain circuits 35 to 39, and the combinational logic circuits 31a to 31e of the integrated circuit 21.
Can all be operated.

Incidentally, there is a case where the integrated circuit has a scan chain circuit which does not need to be tested during the accelerated test. At the time of design, the scan chain circuit provided in the integrated circuit was to be tested during the acceleration test,
Testing may not be required during production.
In such a case, the acceleration test can be limited by connecting the output terminal and the input terminal of the scan chain circuit that needs to be tested and inputting the pseudo random number data from the random number generation circuit.

FIG. 3 is a block diagram showing a connection state when the scan chains 37 and 38 are not tested in the integrated circuit 21. Integrated circuit 21 shown in FIG.
In, the scan-out terminal 26a of the scan chain circuit 35 and the scan-in terminal 23b of the scan chain circuit 36 are connected by a wiring 40a. Also, the scan-out terminal 26b of the scan chain circuit 36
And the scan-in terminal 23 of the scan chain circuit 39
e is connected by a wiring 40e. At this time, the scan-in terminals 23b and 2 of the scan chain circuits 37 and 38
3c is grounded to prevent an open state. In this way, by connecting only a part of the scan chains, it is possible to operate only a part of the integrated circuit in the accelerated test.

Next, a test circuit for an integrated circuit according to a third embodiment of the present invention will be described with reference to FIG. FIG.
It is a block diagram showing a random number generation circuit provided with a return circuit. The scan flip-flop 49 included in the LFSR 42 has three exclusive OR gates EXOR gate 4 serving as a signal feedback circuit similarly to the LFSR 2 and the LFSR 22.
7a to 47c are connected to the output side of each scan flip-flop 49.

That is, the seventh stage and the eighth stage constituting the LFSR 42
EX on the output side of the scan flip-flop 49 with the stage
The input terminal of the OR gate 47c is connected. Also,
One of the input terminals of the EXOR gate 47b is connected to the output terminal of the EXOR gate 47c, and the other is connected to the output side of the fifth-stage scan flip-flop 49.
Further, one input terminal of the EXOR gate 47a is E
The other end is connected to the output terminal of the scan flip-flop 49 at the third stage, and the other end is connected to the output terminal of the XOR gate 47b.

The CLK terminal 45 is connected to a clock pin (not shown) of all the scan flip-flops 49 included in the integrated circuit 41. Then, by inputting a clock signal from the CLK terminal 45, the scan flip-flop 4 connected to the scan chain circuit 50
At 9, the data is shifted in order.

In this embodiment, the output terminal of the EXOR gate 47a is connected to one input terminal of the OR gate 53 connected to the input terminal of the multiplexer 48.
LFSR4 for generating 8-bit pseudo random number data
The input terminals of a NOR gate 52, which is a NOT circuit of a logical sum, are connected to the respective output sides of the eight scan flip-flops 49 and 49a constituting the second scan flip-flop 2. And NOR
The output terminal of the gate 52 is connected to the other input terminal of the OR gate 53 which is an OR circuit. Thus, NO
LFSR using R gate 52 and OR gate 53
Can be configured.

The LFSR 42 becomes inoperable when all the registers become 0. However, by providing the return circuit, the output of the NOR gate 52 becomes 1 when all the outputs of the registers (scan flip-flops 49 and 49a) become 0. Therefore, the OR gate 53
And a flip 49 via a multiplexer 48
"1" is input to "a". Therefore, LFSR
Once the operation starts, the contents of the register do not become all zeros after that, and the pseudo random number data continues to be generated forever.

Also, by providing the LFSR 2 of the integrated circuit 1 and the LFSR 22 of the integrated circuit 21 with the return circuit provided in the LFSR 42, once the LFSR 2 of the integrated circuit 1 and the LFSR 22 of the integrated circuit 21 start operating once, The pseudo-random data will be generated forever. Therefore, there is no need to input an initial value when starting the LFSR.

Next, the procedure of the acceleration test of the integrated circuit 41 will be described with reference to FIG. FIG. 6 is a flowchart showing a procedure at the time of the acceleration test of the integrated circuit 41. As described above, since the LFSR 42 of the integrated circuit 41 is provided with the return circuit, the LFS
There is no need to input an initial value to R42.

When performing an accelerated test of the integrated circuit 41, power is supplied to a power supply terminal (not shown) of the integrated circuit 41 (s
7). Then, a predetermined signal is input to the mode terminal 44 so that the multiplexer 48 receives the output of the OR gate 53. Then, the integrated circuit 41 is operated under a high temperature environment for a predetermined time (s9). After a lapse of a predetermined time, the power supply to the power supply terminal of the integrated circuit 41 is stopped. Then, the integrated circuit 41 is connected to a tester to determine the quality (s10), and it is checked whether the integrated circuit 41 has been destroyed due to the application of stress, and the non-defective integrated circuit is shipped.

As described above, in the integrated circuit 41, LF
No initialization of SR42 is required. In addition, LFSR42
Only the mode that uses the pseudo-random data generated from. Therefore, since the mode terminal 44 may be fixed by wiring on the burn-in board for the acceleration test, the step s8 is not actually required.

In the embodiment of the present invention, LFS
Although the configuration for generating 8-bit pseudo random number data for R has been described, the present invention is not limited to this configuration.

[0056]

According to the present invention, the following effects can be obtained.

(1) A signal feedback circuit is connected from the input side of a scan chain circuit in which a plurality of flip-flops are connected in series to test the internal circuit to the same number of flip-flops as the number of bits of the pseudo random number data. And generates a pseudo-random number data and sends it to the scan chain circuit.
By sharing a flip-flop, which is a common part of the R circuit, the number of circuits can be minimized. In addition, LFS has almost no effect on the increase of the circuit.
The number of bits of the R register can be increased.

(2) Of a plurality of scan chain circuits in which a plurality of flip-flops are connected in series to test an internal circuit, the same number of flip-flops as the number of bits of pseudo-random number data is input from one circuit input side. Since the signal feedback circuit is connected to the flip-flop to form a random number generation circuit, the number of circuits can be minimized by sharing the flip-flop which is a common part of the scan chain circuit and the LFSR circuit.

(3) Since the test circuit of the integrated circuit has a return circuit that outputs a return signal when the random number generation circuit stops operating, when the random number generation circuit becomes inoperable and stops, Since the return signal is output from the return circuit, the random number generation circuit can be operated without performing the initialization processing of the random number generation circuit.

(4) A signal feedback circuit is connected from the input side of the scan chain circuit in which a plurality of flip-flops are integrated in series to the same number of flip-flops as the number of bits of the pseudo-random number data to constitute a random number generating circuit. , Inputting an initial value to this random number generation circuit to generate pseudo random number data,
Since the input is input to the scan chain circuit, the test of the integrated circuit can be easily performed by inputting the initial value without increasing the scale of the test circuit of the integrated circuit.

(5) A signal feedback circuit is connected to the same number of flip-flops as the number of bits of the pseudo-random number data from the input side of one of the scan chain circuits in which a plurality of flip-flops are connected in series. The scan circuit is tested by generating data and connecting a circuit in which the input terminal and the output terminal of another scan chain circuit are connected in series to the output side of the scan chain circuit connected to this signal feedback circuit. Since one of the scan chain circuits can be used as a pseudo-random number generation circuit and a plurality of other scan circuits can be tested, the test can be performed while minimizing the scale of the test circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a test circuit of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a test circuit of an integrated circuit including a plurality of scan chains according to a second embodiment of the present invention.

FIG. 3 shows a scan chain circuit 1 in the integrated circuit 21.
It is a block diagram which shows the connection state when the test of 7 and 18 is not performed.

FIG. 4 is a block diagram illustrating a random number generation circuit including a return circuit.

FIG. 5 is a flowchart illustrating a procedure of an acceleration test of the semiconductor integrated circuit 1.

FIG. 6 is a flowchart showing a procedure at the time of an acceleration test of the integration 41;

FIG. 7 is a block diagram illustrating an example of a test circuit of a semiconductor integrated circuit incorporating an LFSR that outputs an 8-bit pseudo random number.

FIG. 8 is a block diagram illustrating an example in which an LFSR is incorporated in a multi-scan circuit including a plurality of scan chains.

[Explanation of symbols]

 2-random number generation circuit (LFSR) 7a-7c-signal feedback circuit 9-flip-flop 10-scan chain circuit

Continued on the front page F term (reference) 2G032 AA00 AB03 AB05 AG01 AG10 AK16 5F038 DT08 DT10 5F064 BB04 BB18 BB19 BB31 DD07 DD32 HH10 HH12 5J049 AA07 AA18 AA21 CA05 9A001 BB05 EE02 FZ05 ZK06 LL06 L05

Claims (5)

[Claims] 1. A scan chain circuit comprising a plurality of flip-flops connected in series for testing an internal circuit, and a random number generation circuit for generating pseudo random number data and transmitting the data to the scan chain circuit. An integrated circuit test circuit, wherein the random number generation circuit is configured by connecting a signal feedback circuit to the same number of flip-flops as the number of bits of pseudo random number data from the input side of the scan chain circuit. Test circuit. 2. An integrated circuit comprising: a plurality of scan chain circuits in which a plurality of flip-flops are connected in series for testing an internal circuit; and a random number generation circuit for transmitting pseudo random number data to the scan chain circuit. In the circuit test circuit, the random number generation circuit is configured by connecting a signal feedback circuit to the same number of flip-flops as the number of bits of the pseudo random number data from the input side of the one scan chain circuit. Circuit test circuit. 3. When the random number generation circuit stops operating,
3. A return circuit for outputting a return signal for restarting the operation to the random number generation circuit.
3. The test circuit for an integrated circuit according to claim 1. 4. An integrated circuit test method for testing pseudo-random data by inputting pseudo-random number data to a scan chain circuit in which a plurality of flip-flops are connected in series, comprising the steps of: A signal feedback circuit is connected to the same number of flip-flops to form a random number generation circuit, an initial value is input to the random number generation circuit, pseudo-random number data is generated, and input to the scan chain circuit. Characteristic integrated circuit test method. 5. A method for testing an internal circuit by inputting pseudo-random number data to a plurality of scan chain circuits in which a plurality of flip-flops are connected in series, comprising the steps of: A signal feedback circuit is connected from the input side to the same number of flip-flops as the number of bits of the pseudo random number data to generate pseudo random number data, and the output of the scan chain circuit to which the signal feedback circuit is connected is connected to another scan chain circuit. A method for testing an integrated circuit, comprising connecting a circuit in which an input terminal and an output terminal are connected in series, and inputting pseudo-random number data to a plurality of scan chain circuits.