JPH1183950A - Testing circuit for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing circuit capable of appropriately detecting the operation frequency of the semiconductor integrated circuit of a microprocessor or the like and easily selecting the processing performance of the semiconductor integrated circuit, based on the detected result. SOLUTION: An LSI chip 1 is provided with a function area (a) where a prescribed logic gate is formed and this testing circuit formed adjacently to the function area (a). The testing circuit is provided with an input signal setting means (b) for setting test signals Sa to be inputted to the function area (a), an output signal evaluation means (c) for comparing the test signals processed by the function area (a) and prescribed expected value signals, a test state switching means (d) for switching a test state to the function area (a) based on an evaluated result from the output signal evaluation means (c) and a clock supply means (e) for supplying the clock signals of a prescribed frequency at least to the input signal setting means (b) and the output signal evaluation means (c).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a semiconductor integrated circuit, and more particularly to a test for a semiconductor integrated circuit for detecting an operating frequency of a microprocessor or the like which affects the processing performance (processing speed) of a mounted device. Circuit.

[0002]

2. Description of the Related Art With the advancement of computer technology in recent years, there is an increasing demand for a higher processing speed of a semiconductor integrated circuit. On the other hand, demand for lower prices due to the spread of computers is also severe. In particular, the processing performance of a computer is determined by the performance of a microprocessor mounted on the computer. Therefore, even if the microprocessors have the same function, the selling price greatly differs depending on the operating frequency.

Conventional semiconductor integrated circuits, in particular, integrated circuits having a large-scale logic circuit such as a microprocessor (hereinafter, referred to as LSI) are compared with an operating frequency of a device on which the microprocessor is mounted. Then, a functional test is performed using a low-speed LSI tester. On the other hand, the detection of the highest operating frequency of the microprocessor itself is performed by LS
A method of roughly estimating a numerical value based on an oscillation frequency output from a Ring oscillation circuit mounted on an I chip is adopted.

[0004] R used to detect the operating frequency of an LSI
The ing oscillation circuit will be described with reference to FIG. R
As shown in FIG. 7, the LS oscillation circuit
NAND formed in the functional area a of the I chip 1,
It is formed by appropriately selecting an odd number of logic gates such as OR and connecting the inputs and outputs of these logic gates in series to form a loop. A ring oscillation set is applied to one input of a specific logic gate, for example, a NAND gate.
When a signal is set and power is supplied, the Ring oscillation circuit performs Ring oscillation (self-oscillation), so that a Ring oscillation output can be detected from the output of the NAND gate, and the output determines the operating frequency of the LSI. .

[0005]

However, the above-described Ring oscillation circuit forms a Ring chain (the connection form of the logic gates shown in FIG. 7) using only a small part of the functional area a of the LSI. It's just that. That is, since the oscillation circuit is formed by using several tens of logic gates among the logic gates formed in the LSI, the accurate operation frequency of the LSI reaching hundreds of thousands of gates is reflected. I can't say that. In addition, since there is no special rule in the method of forming the Ring oscillation circuit, if the number of connection stages and connection arrangement of the logic gates are different, the Ri characteristics having different characteristics are different.
There is a problem that an ng oscillation circuit is formed, and operating frequencies detected by LSIs having the same function are different.

Therefore, although the LSI is evaluated as a high-speed chip based on the operating frequency detected by the Ring oscillation circuit, there occurs a problem that the processing speed when the LSI is mounted on a device does not reach a desired specified value. This leads to a problem of lowering the reliability of having to replace the chip and a problem of an increase in the number of working steps. SUMMARY OF THE INVENTION The present invention solves the above-described problems, appropriately detects the operating frequency of a semiconductor integrated circuit such as a microprocessor, and can easily select the processing performance of the semiconductor integrated circuit based on the detection result. It is intended to provide a circuit.

[0007]

According to an aspect of the present invention, there is provided a test circuit for a semiconductor integrated circuit for testing an operating frequency of a functional region formed on an integrated circuit chip. A test circuit, input signal setting means for setting a test signal input to the function area, output signal evaluation means for comparing the test signal processed by the function area with a predetermined expected value signal, Test state switching means for switching a test state to the functional area based on the evaluation result from the signal evaluation means, and a clock supply for supplying a clock signal of a predetermined frequency to at least the input signal setting means and the output signal evaluation means And a test of the functional area by sequentially changing the frequency of the clock signal supplied from the clock supply means. I have.

According to the test circuit for a semiconductor integrated circuit of the present invention, for example, input and output of a test signal to a macro area or a functional area such as a RAM formed on an LSI chip while sequentially changing an operation frequency. To easily and accurately detect the highest operating frequency at which the functional area can perform normal processing operation by comparing and evaluating the test signal processed by the functional area and a predetermined expected value signal. Can be. As a result, the maximum operating frequency can be detected with sufficient accuracy compared to the conventional test method using a ring oscillation circuit, and the maximum operating frequency in a state equivalent to a state where the LSI is mounted on the device can be easily determined. Can be detected.

According to a second aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the first aspect, the clock supply unit includes an initial frequency holding unit that holds an initial frequency of the clock signal; A frequency setting unit that sequentially changes and sets the initial frequency based on the operation state of the clock generation unit; a clock generation unit that generates and outputs a clock signal based on the frequency set by the frequency setting unit; And a frequency extracting unit that extracts a predetermined frequency from among the frequencies set by (1), and sets the test signal to the input signal setting unit in a first test state set by the test state switching unit. And setting an initial frequency of the clock signal in the clock supply means, and generating a clock based on the initial frequency in the second test state. And comparing the test signal processed in the functional area with the expected value signal, and when the comparison results match, changing the frequency of the clock signal by a predetermined amount and continuing the test state, If the comparison results do not match, the test state is switched to a third test state. In the third test state, among the frequencies of the clock signal supplied from the clock supply unit, the comparison results match. It is characterized by extracting the highest frequency to be used.

According to the test circuit for a semiconductor integrated circuit of the present invention, a clock signal is supplied to the functional area by sequentially increasing the operating frequency with the lowest operating frequency as an initial frequency, and supplying a clock signal to the functional area. Is determined (compared), and when the test signal deviates from the expected value, it is determined that the frequency of the clock signal supplied in the test state of the functional area has reached the maximum operating frequency, so that the maximum operation of the functional area is performed. The frequency can be easily detected, so that it is possible to improve the reliability of the LSI and reduce the number of man-hours for securing the operation capability of the LSI-mounted device.

According to a third aspect of the present invention, in the test circuit for a semiconductor integrated circuit according to the first aspect, the clock supply unit includes a minimum frequency holding unit that holds a minimum standard frequency of the functional area; The highest frequency holding unit that holds the highest standard frequency of the area, the frequency setting unit that uses the lowest and highest standard frequencies, sequentially changes and sets the frequency by an algorithm of binary sorting, and is set by the frequency setting unit. A clock generation unit that generates and outputs a clock signal based on a frequency; and a frequency extraction unit that extracts a predetermined frequency from the frequencies set by the frequency setting unit, and that is set by the test state switching unit. In the first test state, the test signal is set in the input signal setting means, and the clock supply means is set to the clock signal. Set the initial frequency of the click signal, a second
In the test state, the test signal processed in the functional area by the clock signal generated based on the initial frequency is compared with the expected value signal, and when the comparison result matches, the clock signal The test state is continued by increasing the frequency of the test signal by a predetermined amount, and when the comparison result does not match, the test state is switched to the third test state, or when the comparison result does not match, The test state is continued by lowering the frequency of the clock signal by a predetermined amount, and when the comparison results match, the test state is switched to a third test state. It is characterized in that, of the frequencies of the supplied clock signal, the highest frequency at which the comparison result matches is extracted.

According to the test circuit for a semiconductor integrated circuit of the present invention, the lowest standard frequency and the highest standard frequency are set in the lowest and highest frequency holding units in the first test state, respectively.
By holding, the frequency of the clock signal supplied in the test state of the functional area in accordance with the algorithm of the binary sort is set by sequentially increasing or decreasing the predetermined frequency calculated from the lowest and highest standard frequencies. By repeating the test state repeatedly,
The time required to reach the maximum operating frequency can be shortened, and the accuracy of the detected maximum operating frequency can be increased.

The test circuit for a semiconductor integrated circuit according to claim 4 is the test circuit for a semiconductor integrated circuit according to claim 1, 2 or 3, wherein the functional area has a plurality of circuits to be tested. The test circuit is characterized by having selection means for switching a connection state with each of the plurality of test target circuits. According to the test circuit of the semiconductor integrated circuit according to the fourth aspect, since the plurality of test target circuits and the test circuit in the functional area that determines the processing speed of the LSI are connected via the selection unit, the selection unit is controlled. By connecting the test circuit to an arbitrary circuit to be tested, the processing performance of the LSI when mounted on various devices can be properly evaluated.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic configuration of a test circuit for a semiconductor integrated circuit according to the present invention will be described with reference to FIG. In FIG. 1, the LSI chip 1 has a function area a in which a predetermined logic gate is formed, and a test circuit formed adjacent to the function area. The test circuit includes an input signal setting unit b, an output signal evaluation unit c, a test state switching unit d, and a clock supply unit e. The clock supply unit e includes an initial frequency holding unit f, A frequency setting unit g;
It comprises a clock generator h and a frequency extractor i.

The input signal setting means b holds the test signal Sa input to the test target circuit in the functional area in the test state. The test signal Sa may be input from outside the LSI, or may be an RO signal formed inside the LSI.
It may be stored in a storage area such as M. The output signal evaluation unit c holds a result (output signal) of processing and outputting the test signal SA input to the test target circuit in the test state, and holds an expected value (an expected value signal) of the output signal held and set in advance. ) Are compared with each other, and the agreement and disagreement between the two are evaluated and discriminated.

The test state switching means d switches the test state (first to third test states) for the circuit under test based on the test state setting signal Sm and the evaluation result by the output signal evaluation means. The clock supply unit e supplies the clock signal of a predetermined frequency to at least the input signal setting unit b and the output signal evaluation unit c to operate the circuit under test at a predetermined frequency. The clock signal may be supplied to the circuit under test.

The initial frequency holding unit f constituting the clock supply means e holds an initial value (initial frequency) Fa of a frequency for operating the circuit under test in the test state. The initial value Fa may be input from outside the LSI, or may be stored in a storage area such as a ROM formed inside the LSI. The frequency setting unit g determines the operation state of the test target area by counting a clock signal supplied from a clock generation unit h described later, and changes the set frequency sequentially to supply the clock to be supplied to the next test state. Determine the frequency of the signal.

The clock generation unit h generates a clock signal based on the frequency set by the frequency setting unit g.
At least input signal setting means b and output signal evaluation means c
To supply. The generated clock signal is supplied depending on the type of the circuit under test. The frequency extracting unit i extracts the highest frequency Fb among the frequencies for which the evaluation result from the output signal evaluating means c is the same.

Next, a test method using a test circuit having such a configuration will be described. In the first test method, first, in the first test state, the test signal Sa is set in the input signal setting unit b, and the initial frequency Fa is set in the initial frequency holding unit f of the clock supply unit e. Second
In the test state, the test signal Sa is input to the test target circuit by the clock signal generated based on the initial frequency Fa, and the processed signal is compared with the expected signal.

If all the comparison results match, the test state switching means d continues the second test state.
The frequency setting unit g of the clock supply unit e changes the frequency of the clock signal so as to increase the frequency by a predetermined amount, and the clock signal is supplied. Then, the input and output signals of the test signal are compared and evaluated again. This test state is repeated until a mismatch occurs in the comparison result.

Then, if the comparison results in a mismatch, the second test state is canceled. Next, the test state is switched to the third test state, and among the frequencies of the clock signals set by the frequency setting unit g of the clock supply unit e, the highest frequency Fb when the comparison result matches is determined by the frequency extraction unit i. Is extracted.

In the second test method, first, in the first test state, the test signal Sa is set to the input signal setting means b, and the initial frequency holding unit f of the clock supply means e is set.
In the second test state, the test signal Sa is input to the circuit under test by the clock signal generated based on the initial frequency Fa, and the processed and output signal and the expected value signal are set. Is compared.

If all the comparison results match, the frequency setting unit g of the clock supply means e changes the frequency of the clock signal so as to increase the frequency by a predetermined amount, and the clock signal is supplied. , The output signals are compared and evaluated, and are repeated until a mismatch occurs in the comparison result. If the comparison result does not match, the clock supply means e changes the frequency of the clock signal so as to decrease by a predetermined amount, and the clock signal is supplied. The input and output signals of the test signal are compared and evaluated again. This is repeated until all the comparison results match.

Then, if the comparison result is a mismatch or a match, the second test state is canceled. Next, the test state is switched to the third test state, and among the frequencies of the clock signal set by the frequency setting unit g of the clock supply unit e, the highest frequency F when the comparison result matches is obtained.
b is extracted by the frequency extracting unit i as the highest operating frequency.

That is, a predetermined test circuit in the functional area is repeatedly subjected to an evaluation test with clock signals of different frequencies sequentially, and the clock signal is output in a state where the output signal from the test circuit matches the expected value. By extracting the highest frequency, the highest operating frequency at which the circuit under test can execute normal processing can be detected. Based on the detection result, the processing speed of the entire LSI is determined, and appropriate selection is performed. Can be.

Next, a first embodiment of a test circuit for a semiconductor integrated circuit according to the present invention will be described with reference to FIG. In FIG. 2, reference numeral 2 denotes a specific test target circuit in a functional area on the LSI chip. The test circuit includes a register 3 for holding an input signal to the test target circuit 2, and an output processed by the test target circuit. Register 4 for holding signal
And a register 5 for holding an expected value signal of the output signal in advance.
And a logic gate (EOR) for comparing the contents of the registers 4 and 5 for each bit, and a comparison and evaluation result by the logic gate as one input, and a frequency detection test state (BIST).
And a CLOCK controller 8 that generates and supplies a clock signal of a predetermined frequency to the test target circuit 2, the registers 3, 4, and 5, and a logic gate (OR) having the other input of the BIST mode setting signal Sbist for setting the mode) And CL
A counter circuit 7 for counting the clock signal from the OCK controller 8 and setting the frequency of the clock signal; a register 6 for holding an initial value of the frequency of the clock signal; a decoder 9 for decoding the frequency set by the counter circuit 7; It has a PLL that synchronizes the clock signal generated by the CLOCK controller 8 with the reference clock CKref.

The registers 3, 4, 5, and 6 are scan registers, and constitute a serial scan chain (dotted line in the figure) from the scan-in terminal SI to the scan-out terminal SO. Although not shown, the initial values are set in the registers 3 and 6, the BIST mode setting signal Sbist is set in the OR gate,
It is assumed that an LSI tester for performing scan-in and scan-out with respect to the scan chain is connected. MUX is a multiplexer, and EO
The comparison result for each bit from the R gate is multiplexed and output to the OR gate.

Next, an LSI using such a test circuit will be described.
The test method will be described with reference to the flowchart of FIG. First, the lowest operating frequency (lowest standard frequency) that must be satisfied in the evaluation of the LSI is set as the initial frequency fmin, and a clock signal of this frequency fmin is supplied to exclude the malfunctioning LSI from the test target (S
1). Next, the BIST mode setting signal Sbist is set to “H”.
, The test state is set to the scan mode (S2), and the shift register operation is performed on the serial scan chain from the scan-in terminal to the scan-out terminal by a signal serially input from the scan-in terminal. , Initialize the contents of the register (S
3).

Next, a test input signal input to the test target circuit from the scan-in terminal is set in the register 3, and an initial frequency fmin is set in the register 6 (S
4). Next, the BIST mode setting signal Sbist is set to “L”.
, The "L" signal is applied to the counter circuit 7 to activate it, and the BIST mode is set (S5).
The CLOCK controller 8 has an initial frequency fmin captured by the counter circuit 7, and has a reference clock CKr.
A clock signal synchronized with ef is generated and supplied to the registers 3, 4, 5 and the test target circuit 2 operating in the BIST mode.

Here, the counter circuit 7 operates at a frequency division of m corresponding to the number m of flip-flops FF of the circuit under test 2 and counts a clock signal of a frequency fmin supplied from the CLOCK controller 8. (S
6). The clock signal from the CLOCK controller 8 is m
When the input signal is transmitted in batches, the input signal held in the register 3 is advanced by the number m of FFs in the test target circuit 2, output, and held in the register 4 as an output signal. Then
By inputting the output signal held in the register 4 and the expected value of the output signal previously set and held in the register 4 to the EOR gate, the contents of both are compared, and
A mismatch is determined (S7). The output of the EOR gate is
The data is multiplexed by the MUX and sent to an OR gate for setting a test state.

The input of an input signal from the register 3 to the circuit under test 2, the output of an output signal from the circuit under test 2 to the register 4, and the comparison between the contents of the registers 4 and 5 in the EOR gate are performed on a bit-by-bit basis. Done in In the EOR gate, when the contents of the registers 4 and 5 match each other in all bits, the output becomes “L”, and the test state is maintained in the BIST mode. In the EOR gate, if the contents of the registers 4 and 5 are different even by one bit, the output becomes "H", the BIST mode is canceled (S9), and the counter circuit 7 and the CLOC are output.
The operation of the K controller 8 is stopped (S10).

When the BIST mode is maintained and the test state is continued, the counter circuit 7 raises the frequency f of the clock signal by a predetermined change amount Δf, so that f ← fmin
A frequency of + Δf is set (S8), and the CLOCK controller 8 generates a clock signal based on the frequency f,
And then repeat the test operation described above. Note that the change amount Δf is set by sequentially increasing the frequency f of the clock signal.
May be preset in the counter circuit 7 or may be set externally by an LSI tester.

On the other hand, when the BIST mode is released, the test state is set to the scan mode (S11),
By decoding the highest frequency among the frequencies set by the counter circuit 7 from the decoder 9 and scanning it out, the highest operating frequency of the test target circuit 2, that is, the LSI can be detected (S12). In the present embodiment, the frequency held by the counter circuit 7 when the BIST mode is released is Δf higher than the maximum operating frequency fmax.
However, since the value of the variation Δf is known in advance, the maximum operating frequency fmax can be easily detected.

As described above, according to the present embodiment, the lowest operating frequency f with no problem in the functional operation is applied to the circuit under test.
The clock signal is supplied by sequentially increasing the operating frequency from min, and the processing status of the test signal is determined.When the processing result deviates from the expected value, the frequency of the clock signal supplied to the circuit under test is the highest. It is determined that the frequency has reached fmax. Therefore, it is possible to easily detect the accurate maximum operating frequency of the test target circuit, and to improve the reliability of the LSI and reduce the number of work steps for securing the operation capability of the LSI-mounted device.

Next, a second embodiment of the test circuit for a semiconductor integrated circuit according to the present invention will be described with reference to FIG. The same components as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted. This embodiment is characterized in that a configuration for performing an operation based on a binary sorting algorithm is added to the configuration of the clock supply unit e of the test circuit described above.

In FIG. 4, reference numeral 11 denotes the lowest standard frequency F of the clock signal generated by the CLOCK controller.
register for holding min, 12 for holding the maximum standard frequency Fmax of the clock signal, 13 for holding the instruction for setting the value of MUX, 14 for holding the instruction for setting the test state in the BIST mode ,
15 is a register for holding a binary sort error Fs;
16 is a register for holding the number of FF stages of the circuit under test 2,
Reference numeral 17 denotes an average frequency (Fmin + Fmax) / 2 = (Fre) calculated from the highest standard frequency Fmax and the lowest standard frequency Fmin.
g1 + Freg2) / 2, a register 18 holds the initial frequency Fbist of the clock signal supplied in the test state of the test target circuit 2, and a register 19 holds the frequency Freg of the clock signal supplied in the test state. , 20 are the frequency deviations of the clock signal (Fre
g-Fbist), a register 21 for holding an input signal to the test target circuit 2, and a register 22 for holding an output signal of the test target circuit and comparing it with an expected value signal.

The registers 11 to 22 are scan registers, and constitute a serial scan chain (dotted line in the figure) from the scan-in terminal SI to the scan-out terminal SO. In addition, the minimum standard frequency Fmin
Is the lowest operating frequency in the product standard that allows the circuit under test 2 to operate normally, and the highest standard frequency F
max is the highest operating frequency in a product standard that allows the test target circuit 2 to operate normally.

With respect to the test operation in the above configuration,
This will be described with reference to the flowchart shown in FIG. First, the test circuit is set to the scan mode (S21), and initial values are set in all registers and initialized (S2).
2). Next, the register 11, the scan-in operation is performed.
The minimum standard frequency Fmin, the maximum standard frequency Fmax, and the binary sort error Fs are set in each of the steps 12 and 15 (S23), and predetermined data is set in other registers.

First, the frequency Fbist of the clock signal supplied when the test is performed is set as the minimum standard frequency Fmin (S24), the test state is set to the BIST mode (S25), and the minimum standard frequency Fmin is set. Is output from the CLOCK controller in accordance with the number of FF stages of the circuit under test 2 to obtain an output signal. By comparing this output signal with the expected value, the processing operation of the test target circuit 2 is evaluated (S26).

If there is an abnormality in the processing operation and the comparison result does not match all bits (fail), the circuit under test 2, that is, the LSI is determined to be malfunctioning (S27), and is excluded from the subsequent test. If the processing operation is normal and all the bits match (pass), the test operation is performed by sequentially changing the frequency of the clock signal to be supplied in accordance with the following binary sorting algorithm.

That is, the initial value of the frequency Freg set in the register 9 is set to Fmin (S28),
Set Fbist1 = Fmin and Fbist2 = Fmax (S2
9) The frequency of the clock signal supplied in the test state is F
bist = (Fbist1 + Fbist2) / 2 = (Fmin + Fmax) /
2, that is, the highest standard frequency Fmax and the lowest standard frequency F
The average value of min is set (S30). This frequency Fbist
The test operation is performed by supplying the clock signal of
The processing operation is evaluated (S31).

If the comparison result of the output signals matches all bits (pass), Fbist1 = Fbist is set (S3).
5) The above-described test operation is performed by increasing the frequency Fbist of the clock signal to be supplied next time, and the test state is repeated until the first match is determined to be unsuccessful (Fail) in the comparison of the output signals. On the other hand, when the comparison result of the output signals does not match all the bits (fail), the test operation is performed by setting Fbist2 = Fbist to lower the operating frequency Fbist to be supplied next time, and the output signals are compared for the first time. The test state is continued until it is determined as (pass). In addition,
When all the bits of the comparison result of the output signals match (pass), the detection accuracy is set in advance, that is, the frequency deviation Fsub (= Fsub) detected using the binary sort error Fs.
The test operation is repeatedly performed until (reg−Fbist) becomes equal to or less than the detection accuracy Fs (S33, S34). When Fsub <Fs, and the accuracy increases to a predetermined value or more, Freg = Fbist is set (S36).

Since the BIST mode is canceled once when the comparison result of the output signals matches all bits, the test state is set to the scan mode after setting Freg = Fbist (S37). Then, the highest operation frequency is extracted by scanning out the highest frequency among the frequencies in which the comparison result of the output signal matches all bits and the detection accuracy is equal to or higher than a predetermined value (S38).

As described above, according to this embodiment, the lowest standard frequency Fmin, the highest standard frequency Fmax, and the binary sort error Fs are set in the register in the scan mode, respectively.
By holding, the frequency of the clock signal supplied to the test target circuit 2 in accordance with the binary sorting algorithm is changed to the lowest standard frequency Fmin and the highest standard frequency Fmax.
In order to set up or down sequentially around the average frequency (Fmin + Fmax) / 2 calculated from
Compared to the first embodiment described above, the time until the maximum operating frequency is detected is shortened, and the deviation Fsub of the detected frequency is set to be equal to or less than a predetermined magnitude Fs (Fsub <Fs) Therefore, the accuracy of the detected frequency can be improved.

Next, a third embodiment of the test circuit for a semiconductor integrated circuit according to the present invention will be described with reference to FIG. The present embodiment is characterized in that a plurality of test target circuits are prepared in the functional area, and each test target circuit and the test circuit of the present invention can be selectively connected by the selection means.

As shown in FIG. 6, a plurality of circuits under test 2a, 2b, and 2c are formed in a functional area a in the LSI chip 1, and clocks supplied to the respective circuits 2a, 2b, and 2c to be tested are provided. Wiring groups 30a, 30b, 30c for transmitting signals and input / output signals are individually provided. In the test circuit 10, a plurality of test target circuits 2a, 2b, 2
c, an arbitrary circuit is selected, and the wiring groups 30a, 30b,
Selection means j connected by 30c is provided.

A register for inputting / outputting a test signal to / from each test target circuit 2a, 2b, 2c, a register for setting an initial frequency of a clock signal supplied in a test state, and the like are the same as in the above-described embodiment. A scan chain is configured and provided for every test target circuit 2a, 2b, 2c, or provided commonly in the test circuit 10.

That is, the test of the operating frequency of the LSI is as follows.
Ideally, it should be executed for all macro areas, RAMs, etc., which affect the processing speed of the LSI. However, the evaluation of the operating frequency should be performed for all the functional areas of the LSI chip reaching hundreds of thousands of gates. Doing so increases the number of work steps and costs, which is not preferable. Therefore, according to such a configuration, a main macro area or the like which affects the processing speed of the LSI chip 1 is set as a test target in advance and the wiring group 3
0a, 30b, 30c and the selection means j,
For example, by controlling the selection means j from an external LSI tester, the test circuit 10 and an arbitrary
Since a, b, and c can be connected, the processing performance of the LSI when mounted on various devices can be properly evaluated.

In the above-described embodiment, the mode in which the test data held in the register of the test circuit is set by the scan-in from the external evaluation device has been described. However, a series of test patterns used for the test operation are tested in advance. By forming and storing in a ROM in an LSI chip together with a circuit, it is possible to reduce the functions and burden on the external LSI tester side, and it is possible to perform an appropriate operation frequency detection test using an inexpensive tester. it can.

[0050]

As described above, according to the test circuit for a semiconductor integrated circuit according to the first aspect, for example, the operating frequency is sequentially set to a macro area or a functional area such as a RAM formed on an LSI chip. The highest operating frequency at which the functional area can perform normal processing operations by performing test signal input / output while changing, comparing and evaluating the test signal processed by the functional area with a predetermined expected value signal. Can be easily and accurately detected. Therefore, the conventional R
The maximum operating frequency can be detected with sufficient accuracy compared to the test method using the ing oscillation circuit, and the maximum operating frequency in a state equivalent to the state where the LSI is mounted on the device can be easily detected. it can.

According to the test circuit for a semiconductor integrated circuit of the present invention, the clock signal is supplied to the functional area by sequentially increasing the operating frequency with the lowest operating frequency as the initial frequency and supplying the clock signal to the functional area. Judge processing status (comparison)
Then, when the test signal deviates from the expected value, it is determined that the frequency of the clock signal supplied in the test state of the functional area has reached the maximum operating frequency, so that the maximum operating frequency of the functional area can be easily detected. Therefore, it is possible to improve the reliability of the LSI and reduce the number of man-hours for securing the operation capability of the LSI-mounted device.

Further, according to the test circuit of the semiconductor integrated circuit of the third aspect, the minimum and maximum standard frequencies are set and held in the minimum and maximum frequency holding units in the first test state, respectively. The test state is repeated by setting the frequency of the clock signal supplied in the test state of the functional area in accordance with the sorting algorithm by sequentially increasing or decreasing the frequency around a predetermined frequency calculated from the lowest and highest standard frequencies. By continuing, the time required to reach the maximum operating frequency can be shortened, and the accuracy of the detected maximum operating frequency can be increased.

Further, according to the test circuit of the semiconductor integrated circuit of the present invention, the plurality of test target circuits and the test circuit in the functional area which influence the processing speed of the LSI are connected via the selection means. By controlling the selection means and connecting the test circuit to an arbitrary test target circuit, it is possible to properly evaluate the processing performance of the LSI when mounted on various devices.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a test circuit of a semiconductor integrated circuit according to the present invention.

FIG. 2 shows a first example of a test circuit for a semiconductor integrated circuit according to the present invention.
FIG. 3 is a circuit configuration diagram showing an example of the present invention.

FIG. 3 is a flowchart showing a test procedure in the first embodiment.

FIG. 4 shows a second example of the test circuit of the semiconductor integrated circuit according to the present invention.
FIG. 3 is a circuit configuration diagram showing an example of the present invention.

FIG. 5 is a flowchart showing a test procedure in the second embodiment.

FIG. 6 shows a third example of the test circuit of the semiconductor integrated circuit according to the present invention.
It is a key map showing an example of.

FIG. 7 is a conceptual diagram showing a conventional operating frequency detection circuit (Ring oscillation circuit).

[Explanation of symbols]

 a Functional area b Input signal setting means c Output signal evaluation means d Test state switching means e Clock supply means f Initial frequency holding part g Frequency setting part h Clock generation part i Frequency extraction part j Selection means 1 LSI chip 2, 2a-2c Test target circuit 3-6 Register 7 Counter circuit 8 CLOCK controller 9 Decoder 10 Test circuit 11-22 Register 30a-30c Wiring group

Claims (4)

[Claims] 1. A test circuit for a semiconductor integrated circuit for testing an operating frequency of a function area formed on an integrated circuit chip, wherein the test circuit sets an input signal to the function area. Output signal evaluation means for comparing the test signal processed by the functional area with a predetermined expected value signal; and switching a test state to the functional area based on an evaluation result from the output signal evaluation means. Test state switching means; and clock supply means for supplying a clock signal of a predetermined frequency to at least the input signal setting means and the output signal evaluation means. The frequency of the clock signal supplied from the clock supply means A test circuit for the semiconductor integrated circuit, wherein the test of the functional area is performed by sequentially changing the function areas. 2. The apparatus according to claim 1, wherein the clock supply unit includes an initial frequency holding unit that holds an initial frequency of the clock signal, and a frequency setting unit that sequentially changes and sets the initial frequency based on an operation state of the functional area. A clock generation unit that generates and outputs a clock signal based on the frequency set by the frequency setting unit; and a frequency extraction unit that extracts a predetermined frequency from the frequencies set by the frequency setting unit. In the first test state set by the test state switching means, the test signal is set in the input signal setting means, and the initial frequency of the clock signal is set in the clock supply means. In a test state, comparing the test signal and the expected value signal processed in the functional area by a clock signal generated based on the initial frequency,
If the comparison results match, the test state is continued by changing the frequency of the clock signal by a predetermined amount; if the comparison results do not match, the test state is switched to a third test state; 2. The test of the semiconductor integrated circuit according to claim 1, wherein, in the third test state, a highest frequency of the frequency of the clock signal supplied from the clock supply unit that matches the comparison result is extracted. circuit. 3. The clock supply means includes: a lowest frequency holding unit that holds a lowest standard frequency of the functional area; a highest frequency holding unit that holds a highest standard frequency of the functional area; A frequency setting unit that sequentially changes and sets the frequency according to a binary sorting algorithm; a clock generation unit that generates and outputs a clock signal based on the frequency set by the frequency setting unit; and a frequency setting unit. A frequency extracting unit that extracts a predetermined frequency from the set frequencies, and sets the test signal to the input signal setting unit in a first test state set by the test state switching unit. Simultaneously setting an initial frequency of the clock signal in the clock supply means, and generating a clock signal based on the initial frequency in the second test state. Comparing the test signal and the expected value signal processed in the functional area by the clock signal,
When the comparison result matches, the frequency of the clock signal is increased by a predetermined amount to continue the test state, and when the comparison result does not match, the test state is switched to a third test state; Or, if the comparison results do not match,
The test state is continued by lowering the frequency of the clock signal by a predetermined amount. When the comparison results match, the test state is switched to a third test state, and the clock supply means is switched in the third test state. 2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein the highest frequency at which the comparison result coincides is extracted from the frequencies of the clock signal supplied from. 4. The method according to claim 1, wherein the functional area has a plurality of circuits to be tested, and the test circuit has a selector for switching a connection state with each of the plurality of circuits to be tested. 4. A test circuit for a semiconductor integrated circuit according to claim 1, 2 or 3.