JP2001313231A - Capacitor array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve small-sized large capacity without changing a conventional packaging method, and a simple and inexpensive manufacturing method. SOLUTION: In this capacitor array, in a laminate where a dielectric layer is laminated, a plurality of first and second capacitor units are alternately aligned in the lamination direction of the dielectric layer. In the first and second capacitor units, at least two internal electrodes that are opposite each other and hold the dielectric layer between the internal electrodes are arranged. In the first capacitor unit, each internal electrode is extended to the different end face on the laminate, and at the same time the extension part is connected to a first external electrode that is formed on the end face of the laminate. In the second capacitor unit, each internal electrode is extended to the end face of a different laminate at a position being different from the position where the first external electrode is formed, the extension part is connected to the second external electrode that is formed on each end face of the laminate, and the first and second external electrodes are connected on each and face of the laminate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor array in which a plurality of capacitor units are stacked in a direction in which dielectric layers are stacked.

[0002]

2. Description of the Related Art With the spread of various electronic devices, the size and weight of these devices have been rapidly reduced. Especially in recent years,
There is an increasing demand for smaller and lighter electronic devices for portable use, such as a camera-integrated VTR, a mobile phone, a notebook personal computer, and a palmtop computer.

[0003] If the size and weight of such electronic devices are reduced, the circuit boards used for the electronic devices must be reduced in size and weight. From the mounting type, in which the pins of the electronic components are inserted into the through holes formed in the printed circuit board and soldered, the electronic components are placed and soldered on the conductive pattern lands provided on the printed circuit board to reduce the size and weight To surface mount technology (SMT).

The electronic components used in the SMT are collectively referred to as surface mount components (SMD). For example, in the field of capacitors, chip-type multilayer ceramic capacitors and capacitor arrays in which a plurality of capacitors are incorporated in an element are listed. Can be

FIG. 4 is an external perspective view of a conventional capacitor array 40, and FIG.
0 is a cross-sectional view, (a) is a partial cross-sectional view taken along line AA,
(B) is a partial cross-sectional view taken along line BB.

As shown in the figure, a capacitor array 40 has, for example, a plurality of internal electrodes 42a and 43a opposed to each other between layers of a laminated body 41 in which a plurality of dielectric layers 41 are laterally laminated. The internal electrodes 42a and 43a are respectively extended to different positions on the end face side of the multilayer body 41, and the external electrodes 46a and 4a are arranged on the end face side of the multilayer body 41.
7a. The dielectric layer 41 and the internal electrode 4
A capacitor unit N is formed by 2a, 43a and external electrodes 46a, 47a. This capacitor unit N
Are formed in the stacking direction of the dielectric layers 41 as needed to form the capacitor array 40. In the figure, adjacent capacitor units Na (42a, 43
a, 46a, 47a), Nb (42b, 43b, 46)
b, 47b),... are shown. Here, the colored part
3 shows a connection portion with an external electrode.

[0007] By using such a capacitor array 40, a single capacitor can be grouped as compared with the conventional one, variations in the size and shape of each capacitor can be suppressed, and the mounting work on the circuit board can be reduced. It can be simplified.

Conventionally, when a multilayer ceramic capacitor is mounted on a printed circuit board or the like, it is necessary to disperse lands that are slightly larger than each capacitor element on the circuit board, so that high-density mounting is required. Although it was difficult, the use of the capacitor array 40 enables high-density mounting by reducing the distance between lands. Further, the number of mountings can be reduced, and the mounting cost can be reduced.

[0009]

However, according to the capacitor array 40, the external electrodes 46a and 46b of the adjacent capacitor units Na-Nb or the external electrodes 47a and 47b are connected to the substrate mounting surface on the end face of the multilayer body 41. It is necessary to provide a distance so as to prevent conduction by the solder. Generally, the distance y between external electrodes is designed to be larger than the width x of the external electrodes. For example, in a 2012-type capacitor array according to the EIA standard, when the width x of the external electrodes is 0.2 mm, the distance y between the external electrodes is 0.3 mm. Therefore, it is necessary to intervene a large number of dielectric layers that do not interpose an internal electrode between adjacent internal electrodes, and since this portion does not generate a capacitance, it is merely an insulating layer, and it is necessary to meet a product demand for a small and large capacity. However, there is a problem that it may cause an increase in size.

The present invention has been achieved in view of the above problems, and an object of the present invention is to provide a capacitor array capable of realizing a small and large capacity.

[0011]

In order to solve the above-mentioned problems, a capacitor array according to the present invention has a structure in which a plurality of dielectric layers are laminated in a rectangular laminate at least facing each other with the dielectric layers interposed therebetween. The first, in which two internal electrodes are arranged,
A capacitor array in which a plurality of second capacitor units are alternately arranged in the stacking direction of the dielectric layers, wherein the first capacitor unit has internal electrodes facing each other on different end faces of the multilayer body. And the extension portion is connected to a first external electrode formed on an end face of the laminate, and the second capacitor unit is configured such that each facing internal electrode has a different end face of the laminate. so,
And extending to a position different from the position where the first external electrode is formed, and the extending portion is connected to second external electrodes formed on each end face of the laminate, and A capacitor array is provided, wherein the first external electrode and the second external electrode are connected.

According to the structure of the present invention, in addition to the capacitance generated between the internal electrodes in the first capacitor unit, the capacitance is generated in the second capacitor unit. An invalid area that does not occur is suppressed as much as possible. In addition, since the capacity generated between the internal electrodes in the second capacitor unit is added to the capacity generated between the internal electrodes in the first capacitor unit, a reduction in the size and the capacity can be realized.

Further, the first capacitor unit has a first
Are connected to the same end face of the multilayer body, so that input / output signals can be taken only on the end face side, so that mounting is easy, and A small and large-capacity capacitor array can be provided.

Further, since the external electrodes on the opposing main surfaces can be formed in the same shape, either main surface can be used as the mounting surface at the time of mounting, and the alignment at the time of mounting becomes unnecessary.

For these reasons, the conventional mounting method of the capacitor array can be used as it is.

The connection of the external electrodes on the end faces of the first and second capacitor units can be performed by a normal method such as a screen printing method.

That is, since a conventional method for manufacturing a multilayer ceramic capacitor element can be used, a simple and inexpensive manufacturing method can be realized.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is an external perspective view of a capacitor array according to the present invention. 2A and 2B are cross-sectional views of the capacitor array of FIG. 1, wherein FIG. 2A is a partial cross-sectional view taken along line AA, and FIG.
FIG. 3 is a partial cross-sectional view taken along line B-B. FIG. 3 is an exploded perspective view of a main part of the capacitor array of FIG. In the figure, a capacitor array 10 of the present invention has, for example, a rectangular laminated body 11 formed by laminating a plurality of dielectric layers 1, and a plurality of dielectric layers 1 inside the laminated body 11 in the laminating direction of the dielectric layers 1. A capacitor unit N is formed. The capacitor unit N is a capacitor unit N which is the first capacitor unit.
a ₁ , Nb ₁ and capacitor units Na ₂ , Nb _{2 as second} capacitor units, and the first and second capacitor units are formed alternately.

The dielectric layer 1 is made of a dielectric material such as barium titanate or strontium titanate.

The capacitor unit Na ₁ has at least two internal electrodes 2 a and 3 a facing each other with the dielectric layer ₁ of the multilayer body 11 interposed therebetween, and the internal electrodes 2 a and 3 a It extends to different end faces. That is, for example, the internal electrode 2a extends to one end surface of the laminate 11 and the extension portion is
Is connected to an external electrode 6a formed on one end face of
The internal electrode 3 a extends to the other end surface of the multilayer body 11, and the extending portion is connected to the external electrode 7 a formed on the other end surface of the multilayer body 11. The capacitor unit Nb ₁ similarly plurality of internal electrodes 2b, 3b, and is formed with external electrodes 6b, 7b.

The capacitor unit Na ₂ has at least two internal electrodes 4 a and 5 a opposed to each other with the dielectric layer 1 of the laminate 11 interposed therebetween, and these internal electrodes 4 a and 5 a It extends to different end faces. That is, for example, the internal electrode 4a extends obliquely above the external electrode 6a on one end surface of the multilayer body 11, and
The extending portion is connected to an external electrode 8a formed on one end surface of the laminate 11, and the internal electrode 5a is connected to the laminate 1
1 is extended obliquely above the other end face 5a, and the extension portion of the external electrode 9a is formed on the other end face of the laminated body 11.
Is connected to The capacitor unit Nb ₁ similarly plurality of internal electrodes 3b, and is formed with external electrodes 8b, 9b.

The internal electrodes 2a-
3a, 2b-3b and internal electrodes 4a-5a, 4b
The capacitance component can be formed by facing between −5b. The internal electrodes 2 to 5 of the capacitor unit N
As the material of (2a to 5b), a noble metal material such as Pd, Ag-Pd alloy, or a base metal such as Ni or Cu is used.

Here, in FIG. 2, the colored portions indicate the connection portions between the internal electrodes 3 to 5 and the external electrodes 6 to 9. Also,
In FIG. 2 (a), the dotted line and the dashed line
And the second external electrode. Further, in FIG. 2B, a dotted line and an alternate long and short dash line represent a first and a second internal electrode and an external electrode, respectively.

Further, as a characteristic part of the present invention, the capacitor unit Na ₁ as the _first capacitor unit and the second
Capacitor unit Na ₂
Are formed on the main surface of any of the external electrodes by electrically connecting the capacitor unit Nb1 as the _first capacitor unit and the capacitor unit Nb2 as the _second capacitor unit. The capacitance of both the first and second capacitor units is obtained only by connecting the parts.

That is, for example, part of the external electrodes 8a, 9a extends to the upper main surface, and part of the external electrodes 6a, 7a extends to the lower main surface to form a capacitor unit group Na. ing. With a similar configuration, the capacitor unit N
b.

The capacitor unit N (Na ₁ , N
a ₂ , Nb ₁ , Nb ₂ ) may be formed by continuously forming at least two electrodes, and the number of continuously formed electrodes is not limited.
Capacitor unit _{N (Na 1, Na 2,} Nb 1, Nb 2)
Is formed by printing electrodes of different patterns on the surface of the dielectric 1, as shown in FIG. Each internal electrode 2a, 3
As shown in FIGS. 3A and 3B, a, 2b, and 3b are alternately extended near the lower surface of the stacked body 11. Further, between the capacitor units Na ₁ -Nb ₁ , the internal electrodes 4a, 5a are alternately extended near obliquely above the internal electrodes 2a-3b. The capacitor unit N (Na ₁ , Na ₂ , Nb ₁ , Nb ₂ ) thus formed is formed in the direction in which the dielectric layers 1 are stacked. Such internal electrodes 2a-3a, 2b-3b and internal electrodes
When a-5a and 4b-5b face each other, a capacitance component can be formed. Next, the capacitor array 1 of the present invention
0 will be described. Hereinafter, the distinction between a, b and 1, 2 in the figure of the capacitor unit will be omitted for the parts common to both. From slip mixed with solvent, dispersant, binder, etc. in dielectric powder and sintering aid,
A ceramic green sheet to be the dielectric layer 1 is formed by a doctor blade method. For the molding method, another method, a pulling method, a die coater, a gravure roll coater, or the like may be used.

A metal ink for forming the internal electrodes 2 to 5 is printed on the dielectric layer 1 by a screen printing method. After that, the dielectric layers 1 on which the internal electrodes 2 to 5 are printed are laminated in the order shown in FIG. 3, and then, are thermocompression-bonded to obtain the block-shaped laminated body 11.

Next, the laminated body 11 is cut into a capacitor block including the capacitor unit N by a pushing blade.
When the laminate 11 is thick, it is desirable to cut it by a dicing method. At this time, the lead portion of the internal electrode in each capacitor unit N is exposed.

Next, the block-shaped laminate 11 is heated at 250 ° C.
After preliminarily firing in a furnace at ~ 400 ° C to remove the binder components, put in a main firing furnace and simultaneously sinter the dielectric ceramics 1 and the internal electrodes 2-5 at 1250-1300 ° C at an appropriate temperature of the ceramic material. .

Thereafter, in order to electrically connect each capacitor unit N to the outside, external electrodes 6 to 9 are formed on the end faces of the sintered body by a suitable electrode forming method. The external electrodes 6 to 9 are formed by applying and baking a conductive paste by screen printing or the like, or by electroless plating,
It can be performed by an appropriate conductive film forming method such as sputtering. Thus, the capacitor array 10 as shown in FIG. 1 is obtained.

Thus, according to the capacitor array 10 of the present invention, a rectangular laminate 11 in which a plurality of dielectric layers 1 are laminated is provided.
Inside, at least two opposing each other with the dielectric layer 1 interposed therebetween.
A capacitor array 10 in which a plurality of first and _second capacitor units Na ₁ and Na _{2 in} which three internal electrodes 2 to 5 are arranged are alternately arranged in the direction in which the dielectric layers 1 are stacked; The capacitor unit Na ₁ is configured such that the internal electrodes 2 and 3 extend from different positions to different end surfaces of the multilayer body 11, and the extended portions form the first external electrodes 6 and 6 formed on the end surface of the multilayer body 11. 7, the second capacitor unit Na ₂ is configured such that the internal electrodes 4 and 5 are different from each other at the end face of the laminated body 11 and the first external electrodes 6 and
7, and the extended portions are connected to the second external electrodes 8, 9 formed on the respective end faces of the laminated body 11, and the first external electrodes Is connected to the second external electrode, for example, in addition to the capacitance generated between the internal electrodes in the _first capacitor unit Na ₁ , the second capacitor unit Na ₂
The configuration is such that a capacity is also generated inside, so that an invalid area where no capacity is generated is suppressed as much as possible. Also, for example, the first
The capacitance generated between the internal electrodes 2a-3a in capacitor unit Na ₁ of the second capacitor unit Na ₂
The capacitance generated between the internal electrodes 4a and 5a is added, so that a small and large capacity can be realized.

Further, the first capacitor unit Na ₁
Since the first external electrodes 6a, 7a of the second capacitor unit Na and the second external electrodes 8a, 9a of the second capacitor unit Na are connected at the same end surface of the multilayer body 11, the external electrodes 6a, 7a on the main surface of the multilayer body 11 are connected. 9 can be formed sufficiently separated from each other, and the external electrodes 6 to 9 on the main surface can be prevented from conducting with the solder at the time of mounting without short-circuiting.

Further, since the external electrodes 6 to 9 on the opposing main surfaces can be formed in the same shape, either main surface may be used as the mounting surface at the time of mounting, and the alignment at the time of mounting becomes unnecessary.

From the above, the conventional mounting method of the capacitor array can be used as it is.

The first and second capacitor units N
The connection of the external electrodes 6a to 9a on the end surfaces of a ₁ -Na ₂ can be performed by a normal method such as a screen printing method.

That is, since a conventional method for manufacturing a multilayer ceramic capacitor element can be used, a simple and inexpensive manufacturing method can be realized.

Here, it is desirable to minimize the amount of solder at the time of mounting so that the solder does not enter under the element at the time of mounting and a short circuit does not occur. In addition, the external electrodes 6 to 9 are not only disposed on the end faces of the laminate 11 but also on the laminate 11
By forming so as to protrude from the main surface, the area of the portion to which the solder adheres at the time of mounting is increased, and the connection with the circuit board is ensured.

In this embodiment, each of the internal electrodes 2 to 5 extends to a different end face of the laminated body 11.
May extend to different ridges.

Further, the internal electrodes 4 and 5 may be arranged separately on both sides of the internal electrodes 2 and 3. It should be noted that the present invention is not limited to the above-described embodiment, and various changes and improvements may be made without departing from the scope of the present invention.

[0040]

As described above, according to the structure of the present invention,
First capacitor units and second capacitor units formed in the stacking direction of the dielectric layers 2 are alternately arranged, and the first capacitor unit is configured such that each of the internal electrodes is different from the stacked body at a position different from each other. While extending to the end face, the extension part is connected to a first external electrode formed on the end face of the laminate, and the second capacitor unit is configured such that each internal electrode is different from a different position from each other. At the end face of the laminate, and extending to a position different from the position where the first external electrode is formed,
Since the extension portion is connected to the second external electrode formed on each end face of the multilayer body, the extension between the internal electrodes of the first capacitor unit and the internal portion of the second capacitor unit Since a capacitance is also generated between the electrodes, an ineffective area where no capacitance is generated is reduced, and a small and large capacity can be realized.

Further, since the first external electrode and the second external electrode are connected at each end face of the laminate, the external electrodes on the main surface formed on the mounting surface of the laminate are sufficiently separated from each other. Thus, the external electrodes on the end face and the external electrodes on the main face can be prevented from conducting with the solder during mounting without short-circuiting.

The connection of the external electrodes on the end faces of the first and second capacitor units can be performed by a usual method such as a screen printing method.

Further, since the external electrodes on each main surface can be formed in the same shape, it is not necessary to align the directions at the time of mounting.

Therefore, the conventional method of mounting the capacitor array can be used as it is, and the conventional method of manufacturing the multilayer ceramic capacitor element can be used, so that a simple and inexpensive manufacturing method can be realized.

[Brief description of the drawings]

FIG. 1 is an external perspective view of a capacitor array according to the present invention.

FIG. 2 is a cross-sectional view of the capacitor array of FIG.
(A) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB.

FIG. 3 is an exploded perspective view of a main part of the capacitor array of FIG. 1;

FIG. 4 is an external perspective view of a conventional capacitor array.

FIG. 5 is a sectional view of the capacitor array of FIG. 4,
(A) is a partial cross-sectional view taken along line AA, and (b) is a partial cross-sectional view taken along line BB.

[Explanation of symbols]

 Reference Signs List 10 capacitor array 11 laminated body 1 dielectric layer 2 (a, b), 3 (a, b) internal electrode 4 (a, b), 5 (a, b) internal electrode 6 (a, b), 7 (a) , B) External electrode 8 (a, b), 9 (a, b) External electrode N (a, b) Capacitor unit x width of external electrode y distance between external electrodes

Claims (1)

[Claims] A first and a second capacitor unit in which at least two internal electrodes facing each other with the dielectric layer interposed therebetween are alternately arranged in a rectangular laminate in which a plurality of dielectric layers are laminated. A capacitor array in which a plurality of the dielectric layers are arranged in the stacking direction of the dielectric layer, wherein the first capacitor unit has internal electrodes facing each other extending to different end faces of the multilayer body, and Is connected to a first external electrode formed on an end face of the laminate, and the second capacitor unit is configured such that each facing internal electrode is a different end face of the laminate and the first external electrode And the extended portion is connected to second external electrodes formed on each end face of the laminate, and the first external electrode and the second external electrode are connected to each other. Connect to external electrode A capacitor array characterized by: