JP2001312428A - Data buffer monitor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data buffer monitor circuit which can securely detect trouble occurring in a write address generating circuit and a read address generating circuit in such a case. SOLUTION: Input data from an input terminal 1 are stored in a data storage part 4a of a storage circuit 4, and input parity corresponding to the input data is generated by a parity generating circuit 7, delayed by >=1 bit through a write address delay circuit 8, and stored in a parity storage part 4b of the storage part 4a. Further, the data stored in the data storage part 4a are read out and outputted to an output terminal 2, and delayed by >=1 bits through the write address delay circuit 8, and a parity matching circuit 11 compares the parity generated by the parity generating circuit 10 with the parity read out of the parity storage part 4b and outputs the parity comparison result from a comparison result output terminal 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a fault monitoring circuit, and more particularly to a data buffer monitoring circuit for detecting an abnormality in a data buffer circuit such as a two-port RAM (random access memory).

[0002]

2. Description of the Related Art Conventionally, various data buffer monitoring circuits have been proposed and used. FIG. 12 shows a typical example of a conventional data buffer monitoring circuit. The data buffer monitoring circuit includes an input terminal 1 for inputting data, a data output terminal 2 for outputting data, a parity check result output terminal 3,
A storage circuit 4, a write address generation circuit 5, a read address generation circuit 6, a write side (or first) parity generation circuit 7, a read side (or second) parity generation circuit 10,
Parity collation circuit 11 and read / write control circuit 1
It consists of two. The storage circuit 4 has a data storage unit 4a and a parity storage unit 4b.

[0003] Input data input from an input terminal 1 is written into a data storage section 4a of a storage circuit 4 based on a write address specified by a write address generation circuit 5, and
The parity of the input data generated by the parity generation circuit 7 is written to the parity storage unit 4b of the storage circuit 4 based on the address specified by the write address generation circuit 5. On the other hand, data read from the data storage unit 4a of the storage circuit 4 based on the read address specified by the read address generation circuit 6 is output from the output terminal 2. And
The parity data read from the parity storage unit 4b of the storage circuit 4 and the parity of the output data generated by the parity generation circuit 10 are collated by the parity collation circuit 11 based on the read address specified by the read address generation circuit 6. If there is an error in the parity check result, an error signal is output from the check result output terminal 3.

FIG. 13A is a timing chart for explaining the operation of the data buffer monitoring circuit shown in FIG. 13A, (a) is input data, (b) is input data parity generated by the parity generation circuit 7, (c) is a write address generated by the write address generation circuit 5, and (d) is a read. Address generation circuit 6
Is generated, (e) is output data read from the data storage unit 4a of the storage circuit 4 to the output terminal 2, (f) is output data parity A and (g) generated by the parity generation circuit 10 based on the output data. ) Is a read (read) parity B read from the parity storage unit 4b of the storage circuit 4. Further, FIG.
4 shows an example of data stored in a port RAM. That is, addresses 1, 2, 3,... And the storage contents of the data storage unit 4a and the parity storage unit 4b for each address are shown.

Japanese Patent Application Laid-Open No. 5-257822 discloses a data buffer monitoring circuit as shown in FIG. Note that, for convenience, the same reference numerals are used for components corresponding to the data buffer monitoring circuit in FIG. The data buffer monitoring circuit of FIG. 14 includes a data input terminal 1, a data output terminal 2,
Parity check result output terminal 3, storage circuit 4, write address register 5 ', read address register 6', parity check circuit 11, read / write control circuit 12,
It comprises EX-OR (exclusive OR) circuits 13 and 14, a write address parity output terminal 15, and a read address parity output terminal 16. With this configuration, the parity of the write address register 5 ′ and the parity of the read address register 6 ′ are output to the output terminals 15 and 16, respectively, and are written to the parity generation circuit (EX-OR circuit) 13 of the input data of the input terminal 1. The parity of the address register 5 'is input. Further, the parity of the read address register 6 ′ is input to a parity generation circuit (EX-OR circuit) 14 for the output data of the output terminal 2.

[0006]

The problems to be solved by the above-mentioned prior art are as follows. That is, in the prior art, a fault in the wiring of the storage circuit from the write address decoder or the write address register in the storage circuit and a fault in the wiring of the storage circuit from the read address decoder or the read address register in the storage circuit can be detected. If a failure occurs in generation and read address generation, the failure cannot be detected. The reason is that a failure in the transition of the address specified by the write address generation circuit and the read address generation circuit is not reflected on the data read from the storage circuit.

[0007]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide not only a data system failure but also a write address generation circuit, a wiring between a write address generation circuit and a storage circuit, a write address decoder and a read address generation circuit in a storage circuit, a read address An object of the present invention is to provide a data buffer monitoring circuit capable of detecting a wiring between a generation circuit and a storage circuit and a failure of a read address decoder in the storage circuit.

[0008]

A data buffer monitoring circuit according to the present invention stores input data in a data storage section of a storage circuit having a data storage section and a parity storage section, and writes the input data in the parity storage section in accordance with the input data. A parity check circuit that stores the parity generated by the side parity generation circuit and checks the parity generated by the read side parity generation circuit and the parity read from the parity storage unit in accordance with the data read from the data storage unit. A write address delay circuit and a read address delay circuit for delaying the parity of the write-side and read-side parity generation circuits by one bit or more, respectively.

According to a preferred embodiment of the data buffer monitoring circuit of the present invention, the write address delay circuit and the read address delay circuit are each constituted by a flip-flop circuit. Each of the write address delay circuit and the read address delay circuit is composed of a shift register. The write address delay circuit and the read address delay circuit are arranged before or after the write-side and read-side parity generation circuits, respectively.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a preferred embodiment of a data buffer monitoring circuit according to the present invention will be described below in detail with reference to the accompanying drawings. Note that, for convenience of explanation, the same reference numerals are used for elements corresponding to the components of the conventional data buffer monitoring circuit described above.

FIG. 1 is a block diagram showing the configuration of a first embodiment of a data buffer monitoring circuit according to the present invention. The data buffer monitoring circuit includes a data input terminal 1, a data output terminal 2, a parity check result output terminal 3,
A storage circuit 4, a write address generation circuit 5, a read address generation circuit 6, a write side parity generation circuit 7, a write address delay circuit 8, a read address delay circuit 9,
Read-side parity generation circuit 10, parity collation circuit 1
1 and a read / write control circuit 12.
The storage circuit 4 includes a data storage unit 4a and a parity storage unit 4b.

The data input from the data input terminal 1 is input to the write data input (data storage section) of the storage circuit 4.
4a and the parity generation circuit 7. The output signal of the parity generation circuit 7 is a write address delay circuit 8
Is input to The output signal of the write address delay circuit 8 is input to a write data input (parity storage unit) 4b of the storage circuit 4. Write address generation circuit 5
Are input to the write address input of the storage circuit 4 and the read / write control circuit 12. Storage circuit 4
The data output from the data storage unit 4a is output from the output terminal 2 and input to the read address delay circuit 9. The output signal of the read address delay circuit 9 is
The data is input to the parity generation circuit 10. An output signal of the parity generation circuit 10 is input to one input terminal of the parity check circuit 11. The parity output from the parity storage unit 4b of the storage circuit 4 is input to the other input terminal of the parity check circuit 11. An output signal as a parity check result of the parity check circuit 11 is output to the parity check result output terminal 3. The output signal of the read address generation circuit 6 is input to the read address input of the storage circuit 4 and the read / write control circuit 12. The output control signal of the read / write control circuit 12 is input to the write address generation circuit 5 and the read address generation circuit 6.

The data buffer monitoring circuit of FIG. 1 will be described in more detail. The input data input from the input terminal 1 is
Based on the write address specified by the write address generation circuit 5, the data is written to the data storage section 4a of the storage circuit 4 and is input to the parity generation circuit 7 to generate a parity corresponding to the input data. The parity generated from the input data is delayed by the write address delay circuit 8 in accordance with the rule for reading from the storage circuit 4 specified by the read address generation circuit 6, and then the write address specified by the write address generation circuit 5 Is written to the parity storage unit 4b of the storage circuit 4 based on Therefore, the input data and the parity generated from the input data are stored in the data storage unit 4 a of the storage circuit 4 at different addresses.
And stored in the parity storage unit 4b.

Next, a read operation will be described. Data is read from the data storage unit 4a of the storage circuit 4 based on the read address specified by the read address generation circuit 6, and parity data is read from the parity storage unit 4b of the address specified by the read address generation circuit 6.
The data read from the storage circuit 4 is output from the data output terminal 2 and the read address delay circuit 9
As a result, the delay is caused in accordance with the rule for writing to the storage circuit 4 specified by the write address generation circuit 5. Accordingly, when the storage (or data buffer) circuit is operating normally, the parity storage of the storage circuit 4 based on the data output from the read address delay circuit 9 and the read address specified by the read address generation circuit 6 The parity data read from the unit 4b is corresponded. Parity is generated by the parity generation circuit 10 for the data read from the storage circuit 4 delayed by the read address delay circuit 9. Then, the parity check circuit 11 checks the parity data read from the storage circuit 4 with the parity data. Failure in the data buffer circuit (write address generation circuit 5, read address generation circuit 6, parity generation circuit 7, write address delay circuit 8, read address delay circuit 9, parity generation circuit 1
0, parity check circuit 11, read / write control circuit 1
(2, bit inversion or fixation in wiring, etc.), an error signal is output from the parity check result output terminal 3.

FIG. 2 is a block diagram of a data buffer monitoring circuit according to a second embodiment of the present invention. FIG.
Uses a flip-flop (FF) 8a as a write address delay circuit 8 and a flip-flop 9a as a read address delay circuit 9.
You are using Further, the embodiment of FIG. 2 is similar to the first embodiment shown in FIG. The number of input data is eight, and each of the write address delay circuit and the read address delay circuit has one stage F
Counters (1 to 10) are used for F8a, FF9a, write address generation circuit 5, and read address generation circuit 6. Then, a 2-port RAM 4 of 10 words × 9 bits is used as a storage circuit.

In the data buffer monitoring circuit of the second embodiment shown in FIG. 2, data input from the input terminal 1 is a write data input (data storage section) 4a of a two-port RAM (storage circuit) 4 and a parity. It is input to the generation circuit 7. The output signal of the parity generation circuit 7 is F
Input to F8a. The output signal of the FF 8a is a write data input (parity storage unit) 4b of the two-port RAM 4.
Is input to The output signal of the write address generation circuit 5 is input to the write address input of the two-port RAM 4 and the read / write control circuit 12. 2-port RAM
The data output 4 (data storage unit) 4a is output from the data output terminal 2 and input to the FF 9a. F
The output signal of F9a is input to the parity generation circuit 10. An output signal of the parity generation circuit 10 is input to one input terminal of the parity check circuit 11. 2-port RA
The data output (parity storage unit) 4b of M4 is input to the other input terminal of the parity check circuit 11. The output signal of the parity matching circuit 11 is output from the matching result output terminal 3. The output signal of the read address generation circuit 6 is 2
The read address is input to the port RAM 4 and is input to the read / write control circuit 12. The output control signal of the read / write control circuit 12 is input to the write address generation circuit 5 and the read address generation circuit 6.

Next, the operation of the data buffer monitoring circuit shown in FIG. 2 in a normal state will be described with reference to FIG.
4A is a timing chart, wherein FIG. 4A shows input data of the data input terminal 1, and FIG. 4B shows a timing chart generated by the parity generation circuit 7 based on the input data of FIG.
(C) is the write address output from the write address generation circuit 5,
(D) is a read address output from the read address generation circuit 6, (e) is output data output from the data output terminal 2, and (f) is a parity (A) of output data generated by the parity generation circuit 10. And (g) are read parities (B) read from the parity storage unit 4b.
It is. On the other hand, FIG. 4B shows the address of the two-port RAM 4 and the contents of the data storage unit 4a and the parity storage unit 4b.

As shown in the timing chart of FIG. 4A, when data D1 (see (a) of FIG. 4A) is input, the input data D1 is stored at the address "1" of the two-port RAM 4. The data is written to the data storage unit 4a. Also,
The parity P1 for data D1 (see (b) of FIG. 4A) generated by the parity generation circuit 7 is the FF 8a
, And is written to the parity storage unit 4b at the address “2” of the two-port RAM 4. Similarly, parity P2, P3... Of input data D2, D3.
Is sequentially written to the address one bit after (or next to) the address where the input data of the two-port RAM 4 is written.

Thereafter, when the value of the read address counter constituting the read address generation circuit 6 becomes "1", the data D1 is read from the data storage section 4a of the 2-port RAM 4 at the address "1", and the output terminal is output. 2 (see (e) of FIG. 4A). After the read data D1 is shifted by one bit by the FF 9a, a parity p1 is generated by the parity generation circuit 10 (see (f) of FIG. 4A). At this time, since the value of the read address counter constituting the read address generation circuit 6 is “2”, the parity P1 corresponding to the data D1 is read from the parity storage unit 4b of the two-port RAM 4 at the address “2”. ((G) of FIG. 4A)
reference). The two parities p1 and P1 are collated by the parity collation circuit 11, and the parity collation result is monitored at the collation output terminal 3, whereby the data buffer circuit (write address generation circuit 5, read address generation circuit 6, parity generation circuit 7) , FF8a and FF9a, the parity generation circuit 10, the parity check circuit 11, the read / write control circuit 12, the wiring, etc.) can be confirmed to be normally operating.

Next, the operation of the data buffer monitoring circuit shown in FIG. 2 in the abnormal state of the data system will be described with reference to FIG. FIG. 5 shows an example of a case where an abnormality has occurred in the data system due to a failure in the 2-port RAM 4 or wiring. FIG.
As shown in the timing chart of FIG. 5A, when data D1 is input from the input terminal 1 (see (a) of FIG. 5A), the input data D1 is the data of the address "1" of the two-port RAM 4. The data is written to the storage unit 4a. Also,
The parity P1 of the data D1 generated by the parity generation circuit 7 (see (b) of FIG. 5A) is 1 in the FF 8a.
Bit-shifted, address “2” of 2-port RAM 4
Is written to the parity storage unit 4b. Similarly, the parity P2, P3... Of the input data D2, D3.
The input data of the two-port RAM 4 is sequentially written to an adjacent address one bit after the address at which the input data is written.
FIG. 5B shows a two-port RA corresponding to FIG.
The address of M4 and the contents of the data storage unit 4a and the parity storage unit 4b are shown.

Here, the input data D4 is stored in a two-port RAM.
When writing to port 4, some failure will cause a 2-port RA
It is assumed that incorrect data D4 has been written to M4. When the value of the read address counter becomes "1", the data D1 is read from the data storage unit 4a of the address "1" of the two-port RAM 4 and output via the data output terminal 2. After the read data D1 is shifted by one bit by the FF 9a, the parity p1 is generated by the parity generation circuit 10. At this time, since the value of the read address counter is “2”, the 2-port RAM 4
The parity P1 corresponding to the data D1 is read from the parity storage unit 4b at the address "2". And
The data is checked by the parity check circuit 11, and by monitoring the parity check result output terminal 3, it can be confirmed that the data buffer circuit is operating normally. However, when the value of the read address counter becomes "4", the data D4 is read from the data storage unit 4a of the two-port RAM 4 at the address "4" (see (e) of FIG. 5A). The parity p4 is generated by the parity generation circuit 10 after being shifted by one bit by the FF 9a (see (f) of FIG. 5A). Therefore, in the parity check circuit 11, the parity p4 generated from the read data D4 from the data storage unit 4a of the address “4” of the two-port RAM 4 and the read of the address “5” of the two-port RAM 4 from the parity storage unit 4b. The parity data P4 (see (g) of FIG. 5A) is collated, and a failure is detected. (However, such a failure in the data system can be detected by a conventional method.)

Next, the operation of the data buffer monitoring circuit shown in FIG. 2 when the write address is abnormal will be described with reference to FIG. FIG. 6A is a timing chart, and FIG. 6B shows the contents of the two-port RAM 4. FIG.
Is an example of a case where an abnormality has occurred due to a failure in the write address decoder or write address generation circuit 5 of the two-port RAM 4. As shown in the timing chart of FIG. 6A, when data D1 is input ((a) of FIG. 6A).
), And the input data D1 is written to the data storage unit 4a of the two-port RAM 4 at the address “1”. The parity P1 of the data D1 generated by the parity generation circuit 7 is shifted one bit by the FF 8a,
The data is written to the parity storage unit 4b of the address “2” of M4 (see (b) of FIG. 6A). Similarly, the parities P2, P2,... Of the input data D2, D3,.

Here, it is assumed that when the value of the write address generation circuit 5 becomes "4", the data is written by recognizing the value of the write address as "5" due to some trouble. When the value of the read address counter constituting the read address generation circuit 6 becomes "1", the 2-port RAM
4 from the data storage unit 4a of the address "1"
Is read (see (e) of FIG. 6A), and the output terminal 2
Output from The read data D1 is FF9
a, the parity generation circuit 1
The parity p1 is generated by 0 (see (f) of FIG. 6A). At this time, since the value of the read address counter is "2", the parity P1 corresponding to the data D1 is read from the parity storage unit 4b at the address "2" of the two-port RAM 4 ((A) in FIG. 6A). g)
reference). These two parities are collated by the parity collation circuit 11, and by monitoring the collation result output terminal 3,
It can be confirmed that the data buffer circuit operates normally.

However, when the value of the read address counter becomes "4" as described above, the data Dx previously written from the data storage unit 4a of the address "4" of the 2-port RAM 4 and the data Dx previously stored from the parity storage unit 4b Is read out. Therefore, in the parity matching circuit 11, the parity p3 generated from the data D3 read from the data storage unit 4a of the address "3" of the two-port RAM 4 and the parity p3 generated from the parity storage unit 4b of the address "4" of the two-port RAM 4 are read. The read parity data Px is collated, and a parity failure is detected from the collation result output terminal 3. Further, when the value of the read address counter becomes “5”, the parity check circuit 11 outputs the parity px generated from the read data Dx from the data storage unit 4 a at the address “4” of the two-port RAM 4 and the two-port RAM 4. The parity data P4 read from the parity storage unit 4b at the address “5” of the RAM 4 is collated, and a failure is detected. (In the conventional method, even if a failure occurs in the write address, since the data and the parity are written to the same address, the parity generated from the read data matches the read parity data, and the failure cannot be detected. Is.)

Next, the operation of the data buffer monitoring circuit shown in FIG. 2 when the read address is abnormal will be described with reference to FIG. FIGS. 7A to 7G are timing charts, and FIG. 7B shows the address, data storage unit 4a, and parity storage unit 4b of the two-port RAM 4.
It is the contents of. This is an example of a case where an abnormality has occurred due to a failure in the read address decoder or read address generation circuit 6 of the two-port RAM 4. As shown in the timing chart of FIG. 7, when the data D1 is input, the input data D1 is stored in the data storage unit 4a at the address “1” of the two-port RAM 4.
Is written to. The parity P1 of the data D1 generated by the parity generation circuit 7 is shifted by one bit by the FF 8a and written to the parity storage unit 4b at the address "2" of the two-port RAM 4. Similarly, the parities P2, P3,... Of the input data D2, D3,.

Thereafter, when the value of the read address counter becomes "1", the data D1 is read from the data storage section 4a of the two-port RAM 4 at the address "1" and output from the output terminal 2. After the read data D1 is shifted by one bit by the FF 9a, the parity p1 is generated by the parity generation circuit 10.
At this time, since the value of the read address counter is "2", the parity P1 corresponding to the data D1 is read from the parity storage unit 4b at the address "2" of the two-port RAM 4. Then, both parities are collated by the parity collation circuit 11 and output from the collation result output terminal 3. By monitoring this terminal 3, it can be confirmed that the data buffer circuit is operating normally.

Here, it is assumed that when the value of the read address counter is scheduled to be "4", the value of the read address counter is recognized as "5" (failure state) due to some failure. In this case, the data D5 is read from the data storage unit 4a of the address "5" of the two-port RAM 4, and the parity data P4 is read from the parity storage unit 4b.
Therefore, in the parity matching circuit 11, the two-port RAM
The parity p3 generated from the read data D3 from the address "3" of No. 4 is compared with the parity data P4 read from the address "5" of the two-port RAM 4, so that a parity error is detected. Next, the value of the read address counter becomes "5" (normal state), and the data D5 is read from the data storage unit 4a and the parity data P4 from the parity storage unit 4b of the 2-port RAM 4 at the address "5". Therefore, in the parity matching circuit 11,
Parity p5 generated from data D5 read from data storage unit 4a at address "5" (failure state) of 2-port RAM 4, and address "5" of 2-port RAM 4
The parity data P4 read from the (normal state) parity storage unit 4b is collated, and a failure is detected. (still,
In the conventional method, even when a failure occurs in the read address, the data and the parity are written to the same address. Therefore, the parity generated from the read data and the read parity data match, and the failure cannot be detected. )

FIG. 3 is a block diagram of a data buffer monitoring circuit according to a third embodiment of the present invention. In this embodiment, four stages of shift registers 8b and 9b are used as the write address delay circuit 8 and the read address delay circuit 9 in FIG. First, the operation of the data buffer monitoring circuit shown in FIG. 3 in a normal state will be described with reference to FIG. FIG. 8A shows a timing chart, and FIG. 8B shows the address of the two-port RAM 4 constituting the storage circuit and the contents of the data storage unit 4a and the parity storage unit 4b. In the third embodiment shown in FIG. 3, data input in the order of “1, 3, 2, 4, 5, 7, 6, 8,. ,
This is a circuit example when rearranging in the order of “7, 8...”.
As shown in the timing chart of FIG.
When 1 is input (see (a) of FIG. 8A), the input data D1 is written to the data storage unit 4a of the 2-port RAM 4 at the address "1". The parity generation circuit 7
Is shifted by 4 bits in the shift register 8 and written into the parity storage unit 4b at the address "5" of the two-port RAM 4 (see (b) of FIG. 8A). Similarly, parity P3, P2, P4... Of input data D3, D2, D4.
Is written to an address four bits after the address at which the input data of the two-port RAM 4 is written.

Thereafter, when the value of the read address counter becomes "1", the data D1 is read from the data storage section 4a of the two-port RAM 4 at the address "1" and output from the output terminal 2. Further, the read data D1 is shifted by 4 bits by the shift register 9b, and then the parity p1 is output by the parity generation circuit 10.
Is generated. At this time, since the value of the read address counter is "5", the parity P1 corresponding to the data D1 is read from the parity storage unit 4b at the address "5" of the two-port RAM 4, and the parity matching circuit 11
Is collated. Then, the data buffer circuit (write address generation circuit 5, read address generation circuit 6, parity generation circuit 7, shift register 8b, shift register 9
b, that the parity generation circuit 10, parity check circuit 11, read / write control circuit 12, wiring, etc.) are operating normally.

Next, the operation of the data buffer monitoring circuit of the third embodiment shown in FIG. 3 in the abnormal state of the data system will be described with reference to FIG. FIG. 9 shows a 2-port RAM
4, or a case where a failure occurs in a data system due to a wiring failure. As shown in the timing chart of FIG. 9A, when data D1 is input, input data D
1 is written to the data storage unit 4a of the 2-port RAM 4 at the address “1”. The parity P1 of the data D1 generated by the parity generation circuit 7 is shifted by 4 bits by the shift register 8 and written into the parity storage unit 4b at the address “5” of the two-port RAM 4. Similarly, the parity of the input data is written to the address of the 2-port RAM 4 four bits after the address where the input data is written. Here, the input data D4 is transferred to the 2-port RA.
It is assumed that D4 is written to the two-port RAM 4 due to some failure when writing to M4.

When the value of the read address counter becomes "1", the data D1 is read from the data storage section 4a of the two-port RAM 4 at the address "1" and output from the data output terminal 2. After the read data D1 is shifted by 4 bits by the shift register 9b, the parity p1 is generated by the parity generation circuit 10. At this time, since the value of the read address counter is “5”, the parity P1 corresponding to the data D1 is read from the parity storage unit 4b of the address “5” of the two-port RAM 4 and collated by the parity collation circuit 11. You. By monitoring the parity check result output terminal 3, it can be confirmed that the data buffer circuit is operating normally.

However, when the value of the read address counter becomes "4", the data D4 is read from the data storage section 4a at the address "4" of the two-port RAM 4, and the data D4 is shifted by four bits by the four-stage shift register 9b. Is done. Therefore, the value of the read address counter is "8".
, The parity check circuit 11 outputs a 2-port R
The parity p4 generated from the read data D4 from the address "4" of the AM4 is compared with the parity data P4 read from the parity storage unit 4b at the address "8" of the two-port RAM 4, and a failure is detected. (However, such a failure in the data system can be detected by a conventional method.)

Next, the operation in the abnormal state of the write address in the third embodiment of the present invention shown in FIG. 3 will be described with reference to FIG. FIG. 10A is a timing chart. FIG. 10A shows input data from the data input terminal 1, and FIG. 10B shows the parity of the input data generated by the parity generation circuit 7 and shifted by 4 bits by the shift register 8b. , (C) is a write address generated by the write address generation circuit 5, (d) is a read address generated by the read address generation circuit 6, (e) is output data output from the data output terminal 2, (f) is After being shifted by the shift register 9b according to the output data, the parity (A) and (g) of the output data generated by the parity generation circuit 10 are read parity (B) read from the parity storage unit 4b of the two-port RAM 4. ).
FIG. 10B shows the address of the two-port RAM 4 and the contents of the data storage unit 4a and the parity storage unit 4b.

FIG. 10 shows an example in which an abnormality has occurred due to a failure in the write address decoder or write address generation circuit 5 of the two-port RAM 4. As shown in the timing chart of FIG. 10A, when the data D1 is input (see (a) of FIG. 10A), the input data D1 is stored in the data storage unit 4a of the 2-port RAM 4 at the address “1”. Written. The parity P1 of the data D1 generated by the parity generation circuit 7 is
Bit-shifted, address “5” of 2-port RAM 4
(See (b) of FIG. 10A). Similarly, the parity of the input data is
The data is written to the address four bits after the address where the input data of the two-port RAM 4 is written. Here, it is assumed that when the value of the write address generation circuit becomes “4”, the write address value is recognized as “2” and data is written due to some failure.

When the value of the read address counter becomes "1", the data D1 is read from the data storage section 4a of the 2-port RAM 4 at the address "1" and output from the output terminal 2. After the read data D1 is shifted by 4 bits by the shift register 9b, the parity p1 is generated by the parity generation circuit 10. At this time, since the value of the read address counter is "5",
2 port RAM 4 Parity storage unit 4b at address "5"
, The parity P1 corresponding to the data D1 is read. Then, the data is compared by the parity matching circuit 11, and by monitoring the comparison result output terminal 3, it can be confirmed that the data buffer circuit is operating normally.

Next, when the value of the read address counter becomes "2", the data D4 is read from the data storage section 4a of the 2-port RAM 4 at the address "2". Therefore, when the value of the read address counter becomes “6”, the parity check circuit 11 outputs the two-port RA
The parity p4 generated from the read data D4 from the data storage unit 4a of the address “2” of M4 and shifted by 4 bits is compared with the parity data P2 read from the parity storage unit 4b of the 2-port RAM 4 at the address “6”. , A fault is detected. When the value of the read address counter becomes "4", the previously written data Dx is read from the data storage unit 4a at the address "4" of the two-port RAM 4. For this reason, when the value of the read address counter becomes “8”, the parity check circuit 11 generates four bits from the data Dx read from the data storage unit 4 a at the address “4” of the two-port RAM 4.
Bit-shifted parity px and 2-port RAM4
The parity data P4 read from the parity storage unit 4b at the address “8” is collated, and a failure is detected.
(In the conventional method, even if a failure occurs in the write address, since the data and the parity are written to the same address, the parity generated from the read data matches the read parity data, and the failure cannot be detected. Is.)

Next, the operation of the third embodiment shown in FIG. 3 when the read address is abnormal will be described with reference to FIG. FIGS. 11A and 11B correspond to FIGS. 10A and 10B, respectively. 2-port RAM
A case where an abnormality has occurred due to a failure of the read address decoder 4 or the read address generation circuit 6 will be described. FIG.
As shown in the timing chart of FIG.
Is input, the input data D1 is written to the data storage section 4a of the 2-port RAM 4 at the address "1". Further, the parity P1 of the data D1 generated by the parity generation circuit 7 is shifted by 4 bits in the shift register 8b, and written into the parity storage unit 4b of the 2-port RAM 4 at the address "5". Similarly, the input data D
Parities p3, p2, p4,... Of 3, D2, D4.
Is written to an address four bits after the address at which the input data of the two-port RAM 4 is written.

Thereafter, when the value of the read address counter becomes "1", the data D1 is read from the data storage section 4a of the 2-port RAM 4 at the address "1", and output from the output terminal 2. After the read data D1 is shifted by 4 bits by the shift register 9b, the parity p1 is generated by the parity generation circuit 10. At this time, since the value of the read address counter is “5”, the address “5” of the two-port RAM 4
The parity P1 corresponding to the data D1 is read from the parity storage unit 4b and collated by the parity collation circuit 11. Thereby, it can be confirmed that the data buffer circuit is operating normally.

Here, it is assumed that when the value of the read address counter is expected to be "6", the value of the read address counter is recognized as "5" due to some trouble. The data D5 and the parity data P1 are read from the data storage unit 4a and the parity storage unit 4b of the address "5" of the two-port RAM 4, respectively. Therefore, in the parity matching circuit 11, the parity p2 generated from the read data D2 from the data storage unit 4a of the address “2” of the two-port RAM 4 and the parity p2 generated from the parity storage unit 4b of the address “5” of the two-port RAM 4 are read. Read parity data P1
Are collated, and a failure is detected. When the value of the read address counter is "10", the data D10,
The parity data P6 is read from the parity storage unit 4b. Therefore, in the parity matching circuit 11, the parity p5 generated from the read data D5 from the data storage unit 4a at the address “5” (failure state) of the two-port RAM 4 and the parity storage at the address “10” of the two-port RAM 4 are stored. The parity data P6 read from the unit 4b is collated to detect a failure. (In the conventional method, even when a failure occurs in the read address, data and parity are written to the same address. Therefore, the parity generated from the read data matches the read parity data, and the failure cannot be detected. Is.)

The configuration and operation of the preferred embodiment of the data buffer monitoring circuit according to the present invention have been described above in detail. However, such embodiments are merely examples of the present invention and do not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications and changes can be made in accordance with the particular application without departing from the spirit of the invention.
For example, the write address delay circuit 8 may exist between the input terminal 1 and the parity generation circuit 7, between the input terminal 1 and the storage circuit 4, or both. Similarly, the read address delay circuit 9 may be present between the storage circuit 4 and the parity check circuit 11, between the parity generation circuit 10 and the parity check circuit 11, or both.

[0041]

As will be understood from the above description, according to the data buffer monitoring circuit of the present invention, when a failure occurs in the write address generation circuit and the read address generation circuit, the failure can be detected. is there. The reason is that the input data and the parity bits generated from the input data are stored in different addresses according to the input rules and the output rules.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a data buffer monitoring circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a data buffer monitoring circuit according to a second embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a data buffer monitoring circuit according to a third embodiment of the present invention;

FIG. 4 is a timing chart (A) showing a normal operation example of the second embodiment according to the present invention shown in FIG. 2 and contents stored in a RAM.

FIG. 5 is a timing chart showing an example of an abnormal operation of the data system according to the second embodiment of the present invention shown in FIG. 2;
M is the stored content.

FIG. 6 is a timing chart showing an example of an abnormal write address operation of the second embodiment of the present invention shown in FIG. 2 and the contents stored in a RAM.

FIG. 7 is a timing chart showing an example of an abnormal read address operation of the second embodiment shown in FIG. 2 and the contents stored in the RAM.

FIG. 8 is a timing chart showing a normal operation example of the third embodiment according to the present invention shown in FIG. 3 and contents stored in a RAM.

9 is a timing chart showing an example of an abnormal operation of the data system according to the third embodiment of the present invention shown in FIG.
M is the stored content.

FIG. 10 is a timing chart showing an example of a write address abnormal operation of the third embodiment according to the present invention shown in FIG. 3 and contents stored in a RAM.

11 is a timing chart showing an example of an abnormal read address operation of the third embodiment of the present invention shown in FIG. 3 and the contents stored in the RAM.

FIG. 12 is a block diagram showing a configuration of a conventional data buffer monitoring circuit.

13 is a timing chart showing the operation of the conventional example shown in FIG. 12 and the contents stored in a RAM.

FIG. 14 is a block diagram showing a configuration of another conventional example of a data buffer monitoring circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Data input terminal 2 Data output terminal 3 Parity collation result output terminal 4 Storage circuit (2-port RAM) 4a Data storage unit 4b Parity storage unit 5 Write address generation circuit 6 Read address generation circuit 7 Parity generation circuit (write data) 8 Write Address delay circuit 8a, 9a Flip-flop (FF) 8b, 9b Shift register 9 Read address delay circuit 10 Parity generation circuit (read data) 11 Parity collation circuit 12 Read / write control circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B001 AA01 AB01 AC04 AD08 AE05 5B018 GA01 GA07 HA12 HA33 MA03 MA32 MA33 NA01 NA07 RA11 RA13

Claims (5)

[Claims] An input data is stored in said data storage section of a storage circuit having a data storage section and a parity storage section,
The parity storage unit stores a parity generated by a write-side parity generation circuit according to the input data, and a parity generated by a read-side parity generation circuit and the parity storage according to data read from the data storage unit. A data buffer monitoring circuit for collating the parity read from the unit with a parity collation circuit, comprising: a write address delay circuit and a read address delay circuit for delaying the parity of the write side and read side parity generation circuits by one bit or more, respectively. Data buffer monitoring circuit. 2. The data buffer monitoring circuit according to claim 1, wherein said write address delay circuit and said read address delay circuit are each constituted by a flip-flop circuit. 3. The data buffer monitoring circuit according to claim 1, wherein each of said write address delay circuit and said read address delay circuit comprises a shift register. 4. The data according to claim 1, wherein the write address delay circuit and the read address delay circuit are arranged at a stage preceding the write side and read side parity generation circuits, respectively. Buffer monitoring circuit. 5. The data buffer monitoring circuit according to claim 1, wherein said write and read address delay circuits are respectively provided at a subsequent stage of said write side and said read side parity generation circuit. .