JP2001308291A - Semiconductor storage device, its drive method and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device high in reading precision of data by utilizing the polarization state of a ferroelectric substance film, its drive method and its manufacturing method. SOLUTION: When the data in response to the polarization state are read from the ferroelectric substance film 22 generating upward polarization or downward remaining polarization, bias is applied on a control gate electrode 23 to be read, for instance, a state where the downward remaining polarization exists is made data '1', and another state where the remaining polarization hardly exists from the state where the upward remaining polarization exists is made data '0'. Particularly, the reading precision is improved since reading current during the data '0' is nearly constant by making the state where the remaining polarization hardly exists the data '0'. In addition, the reading precision is further improved by previously inducing input to one data (for instance, the data '1').

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a structure in which a potential of a channel region of a field effect transistor is changed by utilizing a hysteresis characteristic of a ferroelectric thin film.

[0002]

2. Description of the Related Art Conventionally, a field effect transistor including a nonvolatile storage portion made of a ferroelectric thin film in a gate, for example, MFISFET, MFSFET, MFM
2. Description of the Related Art A semiconductor memory device including a field-effect transistor called an ISFET (hereinafter, referred to as a “ferroelectric FET”) is known.

FIG. 8 is a sectional view of a conventional MFISFET type ferroelectric FET. As shown in FIG. 1, a conventional ferroelectric FET includes a silicon oxide film 102 provided on a silicon substrate 101 and a zircon-lead titanate (PZT) or tantalum provided on the silicon oxide film 102. Ferroelectric film 103 made of a metal oxide such as bismuth strontium oxide (SBT), gate electrode 104 made of a conductive material such as Pt, and source regions provided on both sides of gate electrode 104 in silicon substrate 101 105 and a drain region 106. A region of the silicon substrate 101 located below the silicon oxide film 102 is a channel region.

[0006] In the structure shown in FIG.
In 3, depending on the polarity of the voltage applied between the gate electrode and the silicon substrate, an upward (a state in which a dipole moment in which the upper side is a positive electrode is generated) or a downward direction (a dipole moment in which the lower side is a positive electrode is generated) Polarization occurs, and the polarization remains even after the application of the voltage is stopped. When no voltage is applied to the gate electrode 104, the ferroelectric substance F corresponds to the two different types of remanent polarization.
The channel region 107 of the ET is in two states having different potential depths. On the other hand, the resistance value between the source and the drain of the ferroelectric FET changes according to the potential depth of the channel region 107. Therefore, the resistance between the source and the drain is determined to be either a high value or a low value in accordance with the two types of remanent polarization states of the ferroelectric film 103, and the two types of resistances differing between the source and the drain. The state indicating any of the values is retained (stored) as long as the state of the remanent polarization of the ferroelectric film 103 is retained. Therefore, a nonvolatile memory device can be configured using the ferroelectric FET.

Here, in a conventional nonvolatile memory device using a ferroelectric FET, for example, a state in which downward remanent polarization occurs in the ferroelectric film 103 is set to data “1”, The state in which upward remanent polarization occurs in 103 is associated with data “0”. In order to cause downward remanent polarization in the ferroelectric film 103, for example, a positive voltage is applied to the gate electrode 104 with the back surface of the silicon substrate 101 as a ground potential.
The voltage of the gate electrode 104 is returned to the ground potential. In order to cause upward remanent polarization in the ferroelectric film 103,
For example, after a negative voltage is applied to the gate electrode 104 with the back surface of the silicon substrate 101 set to the ground potential, the voltage of the gate electrode 104 is returned to the ground potential.

FIGS. 9 (a), 9 (b) and 9 (c) respectively show that the remanent polarization in the ferroelectric film 103 is downward,
The gate electrode 104, the ferroelectric film 103, the silicon oxide film 102, and the channel region 107 in the upward and substantially zero positions.
FIG. 3 is an energy band diagram showing an energy band state in a cross section passing through the hologram. 9A to 9C, the silicon substrate 101 is a P-type substrate and the source region 1
05 and the drain region 106 are N-type semiconductor regions. The arrows in FIGS. 9A and 9B indicate the direction of polarization of the ferroelectric.

To obtain the state shown in FIG. 9A, a positive voltage is applied to the gate electrode 104 with respect to the silicon substrate 101. The potential difference applied between the gate electrode 104 and the silicon substrate 101 is distributed at a certain ratio to the ferroelectric film 103 and the silicon oxide film 102 between the gate electrode 104 and the silicon substrate 101. At this time, the potential difference distributed to the ferroelectric film 103 is
Gate electrode 104 so as to be higher than the polarization inversion voltage of
, The polarization of the ferroelectric film 3 becomes downward. Then, when the applied voltage is removed to return the gate electrode 104 to the ground voltage, downward remanent polarization occurs as shown in FIG. When the remanent polarization is downward (state of data “1”), the electric field generated between the positive electrode induced at the lower end of the ferroelectric film 103 and the negative electrode induced at the upper end thereof causes the ferroelectric film 103, The energy bands of the silicon oxide film 102 and the channel region 107 are bent as shown in FIG. At this time, the channel region 107
The region near the interface with the silicon oxide film 102 becomes negatively ionized, and the depletion layer spreads deep into the substrate, and the channel region 1
07 in the region near the interface with the silicon oxide film 102 becomes lower than the ground potential. That is, a so-called inversion layer is formed.

On the other hand, in order to obtain the state shown in FIG.
A negative voltage is applied to the silicon substrate 101 so that the potential difference distributed to the ferroelectric film 103 is larger than the polarization inversion voltage of the ferroelectric, to the gate electrode 104. In this case, when the application of the voltage is stopped and the gate electrode 104 is returned to the ground potential, as shown in FIG.
Downward remanent polarization occurs. When the remanent polarization is upward (state of data “0”), the ferroelectric film 103 and the silicon oxide are generated by the electric field generated by the negative electrode induced at the lower end of the ferroelectric film 103 and the positive electrode induced at the upper end. Although the energy bands of the film 102 and the channel region 107 are bent, holes serving as majority carriers are accumulated in a region of the channel region 107 near the interface with the silicon oxide film 102, so that a depletion layer is not formed, The potential of the region 107 becomes substantially equal to the ground potential.

As described above, since the potential of the region near the interface of the channel region 107 differs depending on the direction of the remanent polarization, when a potential difference is given between the source region 105 and the drain region 106 which are N-type semiconductor regions, the residual The current value flowing differs depending on the direction of polarization. That is, in the state of data “1” in which the potential of the channel region 107 is lower than the ground potential, an inversion layer is formed in the channel region 107, so that the source-drain is in a low resistance state (ON state). A large current flows. On the other hand, in the state of data “0” where the potential of the channel region 107 is the ground potential, since no inversion layer is formed in the channel region,
There is a high resistance state (OFF state) between the drains and almost no current flows. When the current value between the source and the drain is measured in this manner, whether the ferroelectric FET is in the state of data "1" or the data "0" depends on the magnitude of the current value.
It can know whether it is in the state of.

As described above, in reading the data state of one ferroelectric FET, basically, it is not necessary to apply a bias to the gate electrode 104 only by applying a potential difference between the source and the drain. That is, the ferroelectric FE
The ON state of T corresponds to the depletion state of the MOS transistor.

[0011]

However, the conventional ferroelectric FET has the following disadvantages.

FIG. 10 is a characteristic diagram showing the relationship between the voltage Vg applied to the gate electrode 104 of the ferroelectric FET and the current Ids between the source and drain of the ferroelectric FET examined by the inventors of the present invention. As shown in the drawing, when data is read by setting the voltage applied to the gate electrode 104 to 0, the current difference ΔI1 between the state of data “1” and the state of data “0” is small. This is because, as shown in FIG.
In the state where no voltage is applied to channel region 4, channel region 1
It is considered that only a weak inversion layer is formed at 07.
As a result, when the polarization state of the ferroelectric film 103 changes over time, it may be difficult to reliably distinguish and read the state of data “1” and the state of data “0”.

[0013] Another problem is that, regardless of whether data "1" or data "0" is held, if these are stored for a long period of time, a hysteresis curve is generated in the direction of polarization corresponding to the held data. Is sometimes imprinted. This is a long term 1
In the ferroelectric film 103 in one polarization state, the coercive voltage for inverting the polarization corresponding to the held data is reduced and the polarization state is likely to occur, while the polarization having the opposite polarity to the polarization is generated. This is because the coercive voltage for inverting is increased and polarization of the opposite polarity is less likely to occur. As a result of this imprint phenomenon, the remanent polarization value of the ferroelectric film 103 of the ferroelectric FET, which has been held for a certain period of time for a long time, is different from the initial remanent polarization value. The signal level (read current value) of the data read after the read operation may be different from the initial signal level (read current value).

An object of the present invention is to provide a structure in which the potential of a channel region of a field effect transistor is changed by utilizing the hysteresis characteristics of a ferroelectric thin film.
An object of the present invention is to provide a semiconductor memory device capable of maintaining high readout accuracy, a driving method thereof, and a manufacturing method thereof.

[0015]

According to the present invention, there is provided a semiconductor memory device comprising: a semiconductor substrate; a ferroelectric film and a gate electrode provided on the semiconductor substrate; and a semiconductor substrate provided on both sides of the gate electrode in the semiconductor substrate. A field effect transistor having a source region and a drain region, wherein the ferroelectric film has a first polarization generated in the ferroelectric film in response to a positive voltage from the gate electrode to the semiconductor substrate; A second polarization generated in the ferroelectric film in response to a negative voltage from the gate electrode to the semiconductor substrate, wherein the first polarization occurs when no voltage is applied to the ferroelectric film. A state in which one of the first and second polarizations remains as a first logical value, and a state in which substantially no polarization remains from the state in which the other of the first and second polarizations remains. The in the second logical value, the first
Data of one of the logical value and the second logical value is stored in the ferroelectric film.

Thus, even when the second logical value written in the ferroelectric film is weak or the polarization hardly remains, data reading can be performed by distinguishing between the first logical value and the second logical value. It is possible to do.

When data in the ferroelectric film is read, a bias voltage is applied to the gate electrode, so that data of the first logical value is stored in the ferroelectric film. And the read current value when the data of the second logical value is stored in the ferroelectric film can be increased, and the read accuracy can be improved.

[0018] Even in the case where the repetition of the read operation accompanied by the application of the bias voltage causes a disturb phenomenon in which the other polarization weakens toward 0 in the ferroelectric film, even when the data is read, A state where a current substantially equal to the current value when the one polarization is written flows between the source region and the drain region is defined as a first logical value, and the state between the source region and the drain region when the other polarization is written is defined as a first logical value. The second logical value is a state in which a current flows from the current value of the above to the current value when the other polarization becomes substantially zero, thereby avoiding the deterioration of the reading accuracy due to the disturb. Can be.

According to the semiconductor memory device of the present invention, there is provided a semiconductor substrate, a ferroelectric film and a gate electrode provided on the semiconductor substrate, and a source region and a drain region provided on both sides of the gate electrode in the semiconductor substrate. A ferroelectric film, wherein the ferroelectric film has a first polarization generated in the ferroelectric film in response to a positive voltage from the gate electrode to the semiconductor substrate; And a second polarization generated in the ferroelectric film in response to a negative voltage with respect to the first and second voltages when the voltage is not applied to the ferroelectric film.
The state where one of the polarizations remains remains as the first logical value, and the state where the polarization hardly remains in the ferroelectric film is referred to as the second logical value. Data of one of the logical values is stored in the ferroelectric film.

Thus, the data of the second logical value corresponds to a state in which substantially no polarization remains due to the disturb from the beginning, so that at the time of reading data, the read current value corresponding to the data of the second logical value Becomes almost constant. Therefore, the distinction from the data of the first logical value is further clarified, and the reading accuracy of the data is remarkably improved.

In the ferroelectric film, the data of the first logical value and the data of the second logical value are written by applying voltages having different absolute values to the gate electrode. preferable.

The semiconductor device further includes a gate insulating film provided on the semiconductor substrate, and an intermediate gate electrode provided on the gate insulating film, wherein the ferroelectric film is provided on the intermediate gate electrode. The gate electrode is provided on the ferroelectric film, and at the time of writing data, the first or second gate electrode is applied to the ferroelectric film by a voltage applied between the gate electrode and the intermediate gate electrode. 2 and a bias voltage can be applied to the gate voltage by floating the intermediate gate electrode at the time of data reading, thereby providing an MFMIS structure. The above-described effect can be exhibited in a semiconductor memory device provided with a field effect transistor as a memory cell.

The gate insulating film provided on the semiconductor substrate, the first intermediate gate electrode provided on the gate insulating film, and the first intermediate gate electrode are provided separately and electrically. And a second intermediate gate electrode connected to the ferroelectric film. The ferroelectric film is provided on the second intermediate gate electrode, and the gate electrode is provided on the ferroelectric film. At the time of writing, the voltage applied between the gate electrode and the second intermediate gate electrode causes remanent polarization in the ferroelectric film, while at the time of reading data, the first and second intermediate gate electrodes are turned off. By being configured to be floating and to apply a bias voltage to the gate voltage, a field effect transistor having a substantially MFIS structure is provided as a memory cell. In the semiconductor memory device has, it can exhibit the above-described effects.

According to the method for driving a semiconductor memory device of the present invention, a ferroelectric film and a gate electrode provided on a semiconductor substrate are provided.
A source region and a drain region provided on both sides of a gate electrode in the semiconductor substrate, wherein the ferroelectric film is formed in accordance with a positive voltage from the gate electrode to the semiconductor substrate. And a second polarization generated in the ferroelectric film in response to a negative voltage from the gate electrode to the semiconductor substrate. A method for driving the device, wherein a state in which one of the first and second polarizations remains when no voltage is applied to the ferroelectric film is defined as a first logical value, In this method, data is read from the ferroelectric film from a state in which the other of the first and second polarizations remains to a state in which almost no polarization remains as the second logical value.

According to this method, even when the second logical value written in the ferroelectric film is weak or almost no polarization remains, data reading is performed by distinguishing the first logical value from the second logical value. Can be performed.

When reading data in the ferroelectric film, a bias voltage is applied to the gate electrode to read a current value when the data of the first logical value is stored in the ferroelectric film; The difference from the read current value when the data of the second logical value is stored in the ferroelectric film can be increased, and read accuracy can be improved.

[0027] Even when the other polarization in the ferroelectric film becomes weaker toward zero by repeating the read operation accompanied by the application of the bias voltage,
At the time of data reading, a current substantially equal to the current value when the one polarization is written is applied to the source region.
The state flowing between the drain regions is defined as a first logical value, and the current from the current value between the source region and the drain region when the other polarization is written to the current value when the other polarization becomes substantially zero. By setting the state in which is flowing as the second logical value, it is possible to avoid the deterioration of the reading accuracy due to the disturbance.

The bias voltage applied to the gate electrode is such that the difference between the currents flowing between the source region and the drain region when the data in the ferroelectric film has the first logical value and the second logical value is substantially maximum. It is preferable that the value be as follows.

According to the method for driving a semiconductor memory device of the present invention, a ferroelectric film and a gate electrode provided on a semiconductor substrate;
A source region and a drain region provided on both sides of a gate electrode in the semiconductor substrate, wherein the ferroelectric film is formed in accordance with a positive voltage from the gate electrode to the semiconductor substrate. And a second polarization generated in the ferroelectric film in response to a negative voltage from the gate electrode to the semiconductor substrate. A method of driving the device, wherein a state in which one of the first and second polarizations remains when no voltage is applied to the ferroelectric film is defined as a first logical value, A state in which almost no polarization remains in the dielectric film is used as a second logical value to store data in the ferroelectric film,
When reading data from the ferroelectric film, a bias voltage is applied to the gate electrode.

According to this method, since the data of the second logical value corresponds to a state in which the polarization remains substantially due to the disturbance from the beginning, the read current corresponding to the data of the second logical value at the time of reading the data. The value becomes almost constant. Therefore, the distinction from the data of the first logical value is further clarified, and the reading accuracy of the data is remarkably improved.

In this case, when writing the data to the ferroelectric film, the absolute value of the voltage applied to the gate electrode is different between when writing the first logical value and when writing the second logical value. Are different from each other, it becomes easy to correspond to a state in which the data of the second logical value has almost no polarization remaining due to the disturbance from the beginning.

The semiconductor device further includes a gate insulating film provided on the semiconductor substrate, and an intermediate gate electrode provided on the gate insulating film, wherein the ferroelectric film is provided on the intermediate gate electrode. When the gate electrode is provided on the ferroelectric film, a voltage is applied between the gate electrode and the intermediate gate electrode at the time of writing data, while the voltage is applied at the time of reading data. By applying a bias voltage to the gate voltage with the intermediate gate electrode floating, the above-described effect can be exhibited in a semiconductor memory device including a field effect transistor having an MFMIS structure as a memory cell.

The gate insulating film provided on the semiconductor substrate, the first intermediate gate electrode provided on the gate insulating film, and the first intermediate gate electrode are provided separately and electrically. A second intermediate gate electrode connected to the ferroelectric film, wherein the ferroelectric film is provided on the second intermediate gate electrode, and the gate electrode is provided on the ferroelectric film. Applies a voltage between the gate electrode and the second intermediate gate electrode when writing data, and floats the first and second intermediate gate electrodes when reading data to bias the gate voltage. By applying a voltage, M
The above-described effect can be exhibited in a semiconductor memory device including a field effect transistor having an FMIS structure as a memory cell.

When writing the data of the second logical value into the ferroelectric film, a bias is applied to the gate electrode so that the voltage applied to the ferroelectric film becomes substantially equal to the coercive voltage of the ferroelectric film. By applying a voltage, data can be written with a state in which almost no polarization remains in the ferroelectric film as the second logical value.

After the data is written to the ferroelectric film or immediately before the data is read, the intermediate gate electrode is once grounded and floated, thereby removing unnecessary charges and the like in the intermediate electrode and reading. Accuracy can be improved.

When reading data written in the ferroelectric film, a voltage is applied to the gate electrode so that a voltage applied to the ferroelectric film is smaller than a coercive voltage of the ferroelectric film. Is preferred.

According to the method of manufacturing a semiconductor memory device of the present invention, a ferroelectric film and a gate electrode provided on a semiconductor substrate;
A source region and a drain region provided on both sides of a gate electrode in the semiconductor substrate, wherein the ferroelectric film is formed in accordance with a positive voltage from the gate electrode to the semiconductor substrate. Cell having a field effect transistor configured to generate a first polarization generated in the ferroelectric film in response to a negative voltage applied to the semiconductor substrate from the gate electrode. Forming a step (a), and applying a voltage having the same polarity as a voltage applied for reading data to the ferroelectric film, releasing the voltage and releasing the first voltage in the ferroelectric film. (B) leaving the polarization, and heating the ferroelectric film for a certain period of time to change the hysteresis characteristic of the ferroelectric film from the first polarization to the second polarization. Necessary coercive voltage Thereby displaced in the increasing direction, and a step (c) for the hysteresis characteristics of the ferroelectric film asymmetric.

According to this method, the polarization state in the ferroelectric film is imprinted in advance on the side of the first logical value, so that the data of the first logical value and the data of the second logical value are read at the time of reading data. It is easy to distinguish between

After the step (b), the method may further include a step of erasing the first polarization remaining in the ferroelectric film.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment -Structure of Ferroelectric FET- FIG. 1 is a cross-sectional view of a MFIS structure ferroelectric FET according to a first embodiment of the present invention. As shown in FIG. 1, the ferroelectric FET includes a silicon oxide film 12 provided on a silicon substrate 11 and a zircon-lead titanate (PZT) or bismuth tantalate provided on the silicon oxide film 12. A ferroelectric film 13 made of a metal oxide such as strontium (SBT), a gate electrode 14 made of a conductive material such as Pt provided on the ferroelectric film 13, and a gate electrode 14 in the silicon substrate 11. It has a source region 15 and a drain region 16 provided on both sides, respectively. A region of the silicon substrate 11 below the silicon oxide film 12 is a channel region 17.

In the structure shown in FIG.
Depending on the polarity of the voltage applied between the gate electrode and the silicon substrate, an upward direction (a state in which a dipole moment in which the upper side is a positive electrode is generated) or a downward direction (a dipole moment in which the lower side is a positive electrode is generated). State), and has a hysteresis characteristic that the polarization remains even after the application of the voltage is stopped. When no voltage is applied to the gate electrode 14, the ferroelectric FET corresponds to the two different types of remanent polarization.
Channel region 17 is in two states with different potential depths. On the other hand, the resistance value between the source and the drain of the ferroelectric FET changes according to the potential depth of the channel region 17. Therefore, according to the two types of remanent polarization states of the ferroelectric film 13, the resistance between the source and the drain is determined to be either a high value or a low value, and the two types of resistances between the source and the drain are different. The state indicating any of the values is retained (stored) as long as the state of the remanent polarization of the ferroelectric film 13 is retained. Therefore, a nonvolatile memory device can be configured using the ferroelectric FET. For example, a state where downward remanent polarization occurs in the ferroelectric film 13 is defined as data “1” (first logical value), and a state where upward remanent polarization occurs in the ferroelectric film 13 is defined as data “0”. As the (second logical value), a ferroelectric FET can be used as a memory cell.

However, as described in the prior art, in the method of reading data without applying a bias to the gate electrode 14, the read current changes between the state of data "1" and the state of data "0". Is small (see FIG. 10). Therefore, in the present embodiment, it is assumed that a bias is applied to the gate electrode 14 at the time of reading.

FIG. 2 is a diagram for explaining a method of setting the gate bias (voltage applied to the gate electrode 13) ΔVg at the time of reading in the present embodiment. The source-drain current Ids of the ferroelectric FET as already described with reference to FIG.
Of the gate bias Vg at which the difference in read current between the state of data "1" and the state of data "0" becomes substantially the maximum value ΔI2, ΔV
g. Here, in the present embodiment, the gate voltage Vg at the time of reading is set to a position shifted from 0 by ΔVg. In other words, the S / N of the read signal
An offset voltage of ΔVg is applied to the gate electrode 14 to increase the ratio.

However, according to this method, the offset voltage ΔV is always applied to the gate electrode 14 of the ferroelectric FET during the read operation.
g will be applied. For example, when a positive offset voltage ΔVg is applied to the gate electrode, if the remanent polarization is downward (the state of data “1”), the direction of the remanent polarization matches the polarization direction induced by the electric field of the gate bias. The polarization state is not affected by the gate bias. However, when the remanent polarization is upward (data "0" state), the direction of the remanent polarization is opposite to the direction of the polarization induced by the electric field of the gate bias, and therefore, the offset voltage ΔVg is applied to the gate electrode. The remanent polarization in the ferroelectric film is slightly weakened. Further, when the read operation is repeated, each time the offset voltage ΔVg is applied to the gate electrode, the residual polarization in the ferroelectric film gradually weakens, and finally, as shown in FIG. The remanent polarization in the body membrane becomes almost zero. A phenomenon in which data is lost by repeatedly applying a voltage that gives an electric field in the direction of weakening the remanent polarization to the gate voltage is called a disturb phenomenon.

FIG. 11 is a hysteresis characteristic diagram for explaining the disturb phenomenon. In FIG.
The vertical axis represents the intensity of polarization expressed with the downward polarization as the positive direction, and the horizontal axis represents the voltage (gate bias) applied to the gate electrode. As shown in the figure, in the initial state, the downward polarization state (the state of data “1”) is at point A in the hysteresis curve, and the polarization state is upward (the state of data “0”).
Is at point B. When a positive gate bias is applied to the gate electrode 114 of the ferroelectric film whose polarization state is at the point A or B, the following behavior is exhibited. Polarization state is A
At the point, even if the gate bias is smaller than the coercive voltage, the polarization state changes from point A to A ′ along the hysteresis curve.
When the read operation is completed and the gate bias returns to zero, the polarization state at point A 'is changed to A
Return to the point. On the other hand, when the polarization state is at point B, even if the gate bias is smaller than the coercive voltage, the polarization state moves from point B to point B 'along the hysteresis curve. Even if it returns to zero,
The polarization state at point B 'no longer returns to point B but moves to point B ". That is, the upward polarization is slightly reduced by applying an offset voltage ΔVg (gate bias) to the gate electrode. When the read operation is repeated, the upward polarization gradually decreases and eventually disappears almost as shown by the dotted line in FIG.

When the polarization disappears due to the disturb phenomenon, in the conventional ferroelectric FET, the potential of the channel region of the ferroelectric FET holding data "0" is changed to the level shown in FIG. As shown in FIG. 7, since the potential changes so as to approach the potential of data “1”, the source-drain current I corresponding to the state of data “0” is changed.
This leads to a phenomenon that ds gradually changes from its initial value, which is undesirable in the design of the readout circuit.

-Reading Method- On the other hand, in the present embodiment, when reading out the ferroelectric FET, an offset voltage ΔVg in a direction for giving a downward polarization to the ferroelectric film 13 is applied to the gate electrode 14. Therefore, the potential near the surface of the channel region 17 when reading data is different from that of the conventional ferroelectric FET as described below.

FIGS. 3A, 3B and 3C respectively show the gate electrode 14 and the ferroelectric film 1 when the remanent polarization in the ferroelectric film 13 is downward, upward and almost zero.
FIG. 3 is an energy band diagram showing an energy band state at the time of reading which occurs in a cross section passing through the silicon oxide film 12 and the channel region 17. 3A to 3C, the silicon substrate 11 is a P-type substrate, and the source region 15 and the drain region 16 are N-type semiconductor regions. The arrows in FIGS. 3A and 3B indicate the directions of remanent polarization of the ferroelectric.

Also in the present embodiment, the procedure for causing polarization in the ferroelectric film 13 is the same as that in the prior art.
When no voltage is applied to the gate electrode 14, the energy band states in the cross section passing through the gate electrode 14, the ferroelectric film 13, the silicon oxide film 12, and the channel region 17 are shown in FIGS. It is as follows.

On the other hand, at the time of data reading, an offset voltage ΔVg is applied to the gate electrode 14 with respect to the silicon substrate 11 in the ferroelectric FET having the structure shown in FIG. At this time, the gate electrode 14 and the silicon substrate 1
1, the ferroelectric film 13 and the silicon oxide film 12 have a potential difference ΔV between the gate electrode 14 and the silicon substrate 11.
g is distributed in a certain ratio.

As shown in FIG. 3A, when the remanent polarization is downward (the state of data "1"), the polarization is further strengthened by the offset voltage .DELTA.Vg applied to the gate electrode 14, so that the ferroelectric Due to the positive electrode induced at the lower end of the film 13, the energy bands of the ferroelectric film 13, the silicon oxide film 12, and the channel region 17 are changed as shown in FIG.
It is bent as shown in FIG. Channel region 1
7, the region near the interface with the silicon oxide film 12 is strongly negatively ionized and the depletion layer spreads deep into the substrate, and the potential of the region near the interface with the silicon oxide film 12 in the channel region 17 becomes lower than the ground potential. That is, a strong inversion layer is formed, and the ferroelectric FET shows a current value in an ON state.

On the other hand, as shown in FIG. 3B, when the remanent polarization is upward (the state of data “0”), the polarization is weakened by the offset voltage ΔVg applied to the gate electrode 14, so that the ferroelectric The strength of the negative electrode induced in the film 13 decreases. The energy bands of the ferroelectric film 13, the silicon oxide film 12, and the channel region 17 are shown in FIG.
Since the channel region 17 is bent as shown in FIG. 2B and the potential of the channel region 17 near the interface with the silicon oxide film 12 becomes low, a weak inversion layer is formed in the channel region 17.

As shown in FIG. 3C, when the remanent polarization disappears due to the disturbance, the ferroelectric film 13, the silicon oxide film 12, and the channel region 17 are caused by the offset voltage ΔVg applied to the gate electrode 14.
Is bent as shown in FIG. 3 (c). At this time, the silicon oxide film 12 in the channel region 17
Since the potential at the conduction band edge in the region near the interface with the surface is bent downward, the channel region 17
An inversion layer that is slightly stronger than that shown in FIG.

As described above, since the potential of the region near the surface of the channel region 17 differs depending on the direction of the remanent polarization, when a potential difference is given between the source region 15 and the drain region 16 which are N-type semiconductor regions, The current value flowing differs depending on the direction of polarization.

That is, assuming that the state shown in FIG. 3A is data "1", in this state, a strong inversion layer is formed, so that a low resistance state exists between the source and the drain. A large current at point y flows. On the other hand, FIG.
Assuming that the state shown in (b) is data "0", in this state, since a relatively high resistance state exists between the source and the drain, a small current flows at the point w in FIG. By measuring the current value between the source and the drain in this way, it is possible to know whether the ferroelectric FET is in the data "1" state or the data "0" state depending on the magnitude of the current value. it can.

In the state shown in FIG. 3 (c), the polarization in the ferroelectric film 13 becomes almost 0, and an inversion layer which is slightly stronger than that shown in FIG. 3 (b) is formed. Point 2 of 2
, An intermediate current flows. Since this current value is sufficiently smaller than the current value at the point y, it is relatively easy to distinguish and detect the current values at the points w and v.

-Method for Setting Data Logic Value- Therefore, in the nonvolatile memory device using the ferroelectric FET of the present embodiment, reading is performed by applying an offset voltage (gate bias) ΔVg to the gate electrode 14. At the same time, in the change due to the disturbance of the hysteresis characteristic shown in FIG. 11, the polarization becomes 0 due to the disturbance from the current value (current value at point w in FIG. 2) when the polarization is upward (the state shown in FIG. 3B). The range up to the current value (the current value at point v in FIG. 2) in the state (state shown in FIG. 3 (c)) is determined as data "0". Specifically, a state indicating a current value equal to or smaller than the current value at point v in FIG. 2 may be determined as data “0”. Setting the current value (current value at the point y in FIG. 2) to “1” when the polarization is in the downward state (state shown in FIG. 3A) is the same as the conventional one.

Table 1 shows the correspondence between the logic state and the polarization of the conventional ferroelectric FET and the ferroelectric FET according to the present embodiment in terms of the resistance between the source and the drain. .

[0059]

[Table 1]

Table 1 shows the ferroelectric FE in the present embodiment.
The difference between T and the conventional ferroelectric FET is that when reading is performed in a state where the polarization has disappeared due to the disturbance, only a weak inversion layer is formed in the channel region 107 in the conventional ferroelectric FET (FIG. 9 ( On the other hand, in the ferroelectric FET of the present invention, since the polarization is generated by the offset voltage ΔVg applied to the gate electrode 14, a relatively strong inversion layer is formed in the channel region 17 (FIG. c)). As a result, in a state where the polarization has disappeared due to the disturbance, in the conventional ferroelectric FET, the current value at the time of changing from the point z in FIG. 2 to the point u and the current value at the point x in FIG. It must be detected. However, it is practically difficult to distinguish and detect the current values at the points u and x, and the logical state of the read data is unknown. On the other hand, in the present embodiment, the point y in FIG.
And the current value in the range from the point w to the point v may be detected separately, so that the read data is clearly associated with one of the two logical states. That is, according to the present embodiment, it is possible to reliably determine the logical state even when the upward polarization has disappeared due to the disturbance.

In the present embodiment, in the ferroelectric FET which is a memory cell, a state in which a downward remanent polarization occurs in the ferroelectric film 13 is defined as data “1”, A state in which remanent polarization occurs or a state in which remanent polarization is almost 0 is defined as data “0”. A state in which a downward remanent polarization occurs or a state in which polarization is substantially zero is defined as data “0”, and an upward residual state is determined. The case where the polarization occurs may be set to data “1”.

Further, since it is arbitrary which state is set to data “0” or data “1”, in the ferroelectric FET which is the memory cell in the present embodiment, the downward residual polarization is applied to the ferroelectric film 13. Is defined as data "0", and a state in which upward remanent polarization occurs in the ferroelectric film 13 or a state in which remanent polarization is substantially zero is data "1".
Needless to say, this may be done.

The silicon oxide film 12 is not always required.

Further, as shown in Table 1 (this embodiment), by appropriately adjusting the built-in potential, even when a bias voltage is applied to the gate electrode 14 when the remanent polarization is upward or disappears, the ferroelectric It is also possible to adjust so that the current Ids between the source and the drain of the FET does not flow (OFF state) and the current flows only when the remanent polarization is downward (ON state). Also in this case, unlike the conventional method, when reading data, when the polarization is in the downward state (data "1"), a large current Ids can be ensured, so that the polarization is zero or in the upward state (data "1"). The distinction from the current (zero) at the time of data “0” will not be obscured (Second Embodiment) Fig. 4 is a sectional view of a memory cell of a semiconductor memory device according to a second embodiment of the present invention. The memory cell of the semiconductor memory device according to the present embodiment is considered to be a ferroelectric FET having any MFMIS structure.

The ferroelectric FET is a P-type silicon substrate 1
1 and a first intermediate gate electrode 18 made of a conductive material such as polysilicon provided on the silicon oxide film 12.
And the first intermediate gate electrode 1 in the silicon substrate 11
N-type source regions 15 provided on both sides of
And a drain region 16. A region of the silicon substrate 11 below the silicon oxide film 12 is a channel region 17. Further, a second intermediate gate electrode 21 made of Pt or the like and a zircon-lead titanate (PZ) provided on the second intermediate gate electrode 21 are provided.
T) or bismuth strontium tantalate (SB
T), a ferroelectric film 22 having a thickness of about 200 nm made of a metal oxide, and a conductive material such as Pt provided so as to face the second intermediate gate electrode 21 with the ferroelectric film 22 interposed therebetween. And a control gate electrode 23. Further, the control gate electrode 23 is connected to the first wiring 25,
The first intermediate gate electrode 18 and the second intermediate gate electrode 21 are connected to a common second wiring 26.

This structure, when the first intermediate gate electrode 18 and the second intermediate gate electrode 21 are considered as a single unit, has a structure between the ferroelectric 13 and the silicon oxide film 12 in the ferroelectric FET shown in FIG. The first and second intermediate gate electrodes 18 and 21 are provided as intermediate gate electrodes, that is, an MFMISFET. However, the first intermediate gate electrode 18 and the second intermediate gate electrode 2
1 may be integrated, or as shown in FIG.
The first intermediate gate electrode 18 and the second intermediate gate electrode 21 may be provided separately.

Here, the material of the ferroelectric film 22 is SBT.
When the film thickness is about 200 nm, the coercive voltage of the ferroelectric film 22 is about 1V.

As compared with the ferroelectric FET of the first embodiment, the structural feature of the ferroelectric FET of the present embodiment is that the polarization state of the ferroelectric film 22 is changed in the present embodiment. And the second wiring 26 connected to the second intermediate gate electrode 21 and the first wiring 25 connected to the control gate electrode 23 so as to directly apply the necessary voltage. The configuration is such that the potential of the first intermediate gate electrode 18 can be determined by the second wiring 26 before the read operation.

Further, as compared with the ferroelectric FET which is the ferroelectric FET of the first embodiment, the feature of the operation of the ferroelectric FET of the present embodiment is that, in the present embodiment, data writing is performed. At the time of writing to cause a downward remanent polarization (data "1") in the ferroelectric film 22, and at the time of writing to cause an upward remanent polarization (data "0") to the ferroelectric film 22. Is that the absolute value of the voltage applied to the ferroelectric film 22 is different.

In this embodiment, although the illustration of the energy band structure in the ferroelectric FET is omitted, FIG.
Assuming that the first intermediate gate electrode 18 and the second intermediate gate electrode 21 are integrated in the structure shown in FIG. 3, in the energy band diagrams shown in FIGS.
Since only a conductor member is interposed between the ferroelectric film 13 and the silicon oxide film 12, the data read operation can be considered in the same manner as in the first embodiment. However,
The difference from the first embodiment is that a voltage is applied between the control gate electrode 23 and the second intermediate gate electrode 21 when the polarization of the ferroelectric film 22 is caused.

FIG. 5 is a hysteresis characteristic diagram for describing the data write operation in this embodiment on voltage-polarization coordinates. In FIG. 5, the horizontal axis is control gate 2
3 represents a voltage applied between the second intermediate gate electrodes 21;
The vertical axis represents the polarization generated in the ferroelectric film 22 with the downward direction being positive. In the following description, it is assumed that the potential of the silicon substrate 11 is always the ground potential.

As shown in FIG. 5, since the polarization of the ferroelectric film 22 before data is written is almost zero, the polarization state is near the origin O. To write data “1” into the ferroelectric film 22, for example, the second wiring 26 connected to the second intermediate gate electrode 21 is set to the ground potential, and the first wiring 25 connected to the control gate electrode 23 is set. Is applied along the solid line from the origin O to the point a ″. After that, when the first wiring 25 connected to the control gate electrode 23 is set to the ground potential, the polarization state changes to The point (a) moves to the point (a), and a charge (residual polarization) of about 10 μC / cm ² is held as data “1” in the ferroelectric film 22 at zero voltage.

Subsequently, in order to rewrite data “1” to data “0”, the first wiring 25 connected to the control gate electrode 23 needs to have a voltage of −3 V necessary for inverting the polarization state to the saturation state. Is applied, a voltage of about -1 V is applied. That is, in the present invention, since the charge due to polarization is defined from negative saturation state (about -10 C / cm ²⁾ to about 0 (about 0μC / cm ²⁾ and the data "0",
From the beginning, the polarization as data “0” is about 0 μC / c.
It is enough if it can be set to m ² . Then, when a voltage of about -1 V is applied to the first wiring 25 connected to the control gate electrode 23, the polarization state moves from the point a to the point b 'as shown by the locus shown in FIG. This operation is performed by the control gate electrode 2
3 is set to the ground potential, and the second wiring 26 connected to the second intermediate gate electrode 21 is supplied with the voltage 1
It is also realized by giving V. After that, when the first wiring 25 connected to the control gate electrode 23 is set to the ground potential, the polarization state moves from the point b ′ to the point b, and the ferroelectric film 22 has about 0 μC / The charge of cm ² is held as data “0”.

That is, in the present embodiment, the polarization (residual polarization) generated in the ferroelectric film 22 when the negative voltage is released after the negative voltage is applied to the ferroelectric film 22 in which the positive residual polarization is generated. ) Becomes substantially 0, a voltage substantially equal to the negative voltage (coercive voltage) is applied to rewrite data from “1” to “0”.

However, the coercive voltage between the second intermediate gate electrode 21 and the control gate electrode 23 (in this embodiment, -1
Even if a weak negative voltage having an absolute value larger than V) and not reaching the saturation state is applied, the effect of improving the reading accuracy described later can be exerted to some extent.

Also, when data "0" is written to the ferroelectric film 22 from a state where no data is written to the ferroelectric film 22, the coercive voltage (about -1 V) shown in FIG. Preferably, it is applied to the film 22.

After writing the data, the second wiring 26 connected to the second intermediate gate electrode 21 is set to the ground potential,
The potential of the first intermediate gate electrode 18 that leads to this is determined. Subsequently, the second wiring 2 connected to the second intermediate gate electrode 21 using a switching transistor or the like.
6 is electrically disconnected from peripheral circuits (not shown).

Alternatively, immediately before reading the data, first, the second wiring 2 connected to the second intermediate gate electrode 21
6 is set to the ground potential, and the potential of the first intermediate gate electrode 18 connected thereto is determined. This is to remove unnecessary electric charges accumulated in the first intermediate gate electrode 18 as a leakage current or the like in the writing and reading operations performed up to the reading or in a stationary state. Subsequently, the second wiring 26 connected to the second intermediate gate electrode 21 is electrically disconnected from a peripheral circuit (not shown) by using a switching transistor or the like. Thereafter, in order to read data, the offset voltage Δ described in the first embodiment is applied to the first wiring 25 connected to the control gate electrode 23.
A read voltage VR corresponding to Vg is applied. This read voltage VR is divided into a voltage applied to the ferroelectric film 22 and a voltage applied to the silicon oxide film 12. At this time, when the polarization of the ferroelectric film 22 is downward (data “1”), the direction of the polarization generated by the voltage applied to the ferroelectric film 22 and the direction of the held polarization (charge) are determined. Are the same, as described in the first embodiment, the direction and magnitude of the polarization do not change even if the read voltage VR is removed.

On the other hand, when the polarization of the ferroelectric film 22 is upward (data “0”), according to the writing method of the first embodiment, the direction of the polarization generated by the voltage applied to the ferroelectric film 22 And the direction of the held polarization (charge) is opposite, the ferroelectric film 22 is disturbed by application of the read voltage VR. As a result, the polarization gradually disappears due to the disturbance, and the source-drain current Ids for data "0" changes accordingly.

However, in the writing method of this embodiment, the state where the polarization is about 0 μC / cm ² is held as data “0” from the beginning. Further, in the present embodiment, the read voltage VR applied to the first wiring 25 connected to the control gate electrode 23 is set so that the voltage applied to the ferroelectric film 22 does not exceed the coercive voltage. The polarization does not disappear due to
The state of data "0" does not reverse to data "1". Therefore, even if data "0" is repeatedly read, the source-drain current Ids does not change. Specifically, the ratio between the voltage applied to the ferroelectric film 22 and the voltage applied to the silicon oxide film 12 is:
The capacitance of the capacitor formed by the second intermediate gate electrode 21, the ferroelectric film 22, and the control gate electrode 23;
It is determined by the ratio to the capacitance of the capacitor formed by the intermediate gate electrode 18, the silicon oxide film 12, and the silicon substrate 11. By adjusting the capacitance ratio and the read voltage VR, the voltage applied to the ferroelectric film 22 during data reading can be made equal to or lower than the coercive voltage of the polarization in the ferroelectric film 22.

In the data storage state, the first wiring 25 connected to the control gate electrode 23 and the second wiring 25 connected to the second intermediate gate electrode 21 are arranged at the last stage of the data writing operation. And the wiring 26 are grounded, thereby making the bias applied to the ferroelectric film 22 zero. As a result, the polarization does not change under the influence of the bias during data retention.

Thus, according to the present invention, data "1" is made to correspond to the state where the remanent polarization is downward, and data "0" is made.
Are written, rewritten, stored, and read in accordance with the range in which the remanent polarization does not reach the upward saturated state, so that the change in the read current due to the disturbance when the data is "0" is reduced. And the reading accuracy can be improved.

In particular, as in the present embodiment, data "0"
Corresponds to the state where the polarization is almost 0, so that the effect of improving the reading accuracy can be remarkably exhibited.

In the present embodiment, writing and rewriting are performed so that the polarization becomes almost 0 when data is "0". However, the present invention is not limited to such an embodiment. It is also possible to set the polarization to be almost 0 when the data is "1".

In this embodiment, the MFMIS
Although the present invention is applied to the ferroelectric FET having the structure, the same effect can be exerted by applying the present invention to the ferroelectric FET having the MFIS structure shown in FIG.

In this embodiment, the first intermediate gate electrode 18, the silicon oxide film 12, and the silicon substrate 1
1, the capacitance value of the ferroelectric capacitor composed of the control gate electrode 23, the ferroelectric film 22 and the second intermediate gate electrode 21 is the same as that of FIG. The position of point a and the position of point b are different. That is, the capacitance value of the capacitor corresponds to the slope on the hysteresis characteristic curve. The voltage applied between the control gate electrode 23 and the silicon substrate 11 is distributed to the paraelectric capacitor and the ferroelectric capacitor. Therefore, as the capacitance value of the ferroelectric capacitor increases, the distribution ratio of the voltage applied between the control gate electrode 23 and the silicon substrate 11 to the ferroelectric capacitor decreases. As described above, since the distribution ratio of the voltage value applied to the control gate electrode 23 changes in accordance with the change in the capacitance value of the ferroelectric capacitor, the current value changes and the data can be more easily distinguished. .

(Third Embodiment) Next, a third embodiment relating to a configuration for preventing imprint will be described.

According to the second embodiment, a change in bias at the time of reading due to disturbance can be suppressed. However, as described in the prior art, reading is performed after holding for a long time by imprinting. Source-
It is difficult to prevent the level of the drain-to-drain current Ids from being different from the initial level.

Therefore, in this embodiment, the ferroelectric film 22
Are written once so that the polarization state of the data is point a (data "1") shown in FIG. 5, and in this polarization state, imprint of data "1" is forcibly induced in advance. Therefore, a feature of the semiconductor memory device of the present embodiment with respect to the conventional method of manufacturing a semiconductor memory device is that, in a normal semiconductor memory device manufacturing process, a step of inducing an imprint after writing data “1” is added. Is to be.

FIG. 6 is a flowchart showing an example of a manufacturing process of the ferroelectric FET (see FIG. 4) of the semiconductor memory device according to the present embodiment.

First, in step ST11, a wafer diffusion step is performed. In this step, the silicon oxide film 1
2. Formation of first intermediate gate electrode 18, silicon substrate 11
Formation of the source region 15 and the drain region 16 by ion implantation of impurities into the first intermediate gate electrode 18, formation of the second intermediate gate electrode 21, the ferroelectric film 22, and the control gate electrode 23 on the first intermediate gate electrode 18; Wiring 2 above (not shown)
5 and 26 are formed.

Next, in step ST12, the ferroelectric FE
Inspect the electrical function of the T ferroelectric film. In this step, it is checked whether or not various characteristics of the ferroelectric film 22 such as voltage-polarization characteristics are appropriate.

Next, in step ST13, data "1" is written to all the ferroelectric FETs. That is, downward polarization is caused in the ferroelectric film 22. Thereafter, by heating the ferroelectric film 22 of the ferroelectric FET,
Imprint is induced in the direction of data "1". At this time, if heating is performed at 150 ° C. for about 10 hours, for example, the hysteresis curve of the ferroelectric film 22 is initially displaced in the direction of data “1”, that is, in the direction in which the downward polarization increases (that is, in (Printing is induced), but from some point this deviation almost stops. In other words, further progress of imprint is extremely small.

FIG. 7 is a hysteresis characteristic diagram showing a change in the hysteresis characteristic of ferroelectric film 22 in step ST13. In FIG. 7, the horizontal axis is the control gate electrode 2
3 represents a voltage applied between the second intermediate gate electrodes 21;
The vertical axis indicates the polarization generated in the ferroelectric film 22 with the downward direction being positive. As shown in the figure, the initial hysteresis characteristic of the ferroelectric film 22 is a curve represented by a dashed line in the figure, but when imprint is induced, the hysteresis characteristic of the ferroelectric film 22 is reduced. The characteristic shifts to the characteristic indicated by the curve represented by the broken line in FIG. When the data “1” is held in the ferroelectric film 22, the hysteresis curve after the imprint is induced shows that the coercive voltage (the voltage value at the point b ′) is lower than the initial hysteresis characteristic. The voltage changes so as to deviate from the voltage by about -0.2 V in the voltage axis direction. Then, even after the imprint is induced in the ferroelectric film 22, the slope of the curve from point a to point a ″ and the slope of the curve from point b to point a ″ (that is, data “1” is written). Since there is a sufficient difference between the capacitance of the ferroelectric film 22 and the capacitance of the ferroelectric film 22 in which data "0" is written, the read voltage VR
Is applied to the first wiring 25 connected to the control gate electrode, the voltage induced on the first intermediate gate electrode 18 shows a sufficient difference depending on the data “1” and the data “0”.
That is, the data readout accuracy can be kept good.

Next, in step ST14, the ferroelectric film 2
After the baking of No. 2, the data "1" of all ferroelectric FETs is erased in step ST15. In this example, data "0" is written to all ferroelectric FETs. At this time, in order to rewrite the data “1” held in the ferroelectric film 22 in which the hysteresis curve is deviated due to the induction of imprint to the data “0”, FIG.
As shown in (2), a negative voltage having an absolute value larger than -1 V may be applied to the ferroelectric film 22 so that the polarization state moves from the point a to the point b '. This operation is performed by setting the first wiring 25 connected to the control gate electrode 23 to the ground potential,
1V is applied to the second wiring 26 connected to the intermediate gate electrode 21.
It can also be implemented by applying the above voltage. Also,
A similar effect can be obtained by heating the ferroelectric film 22 of the ferroelectric FET to a temperature higher than the phase transition temperature of the ferroelectric.

However, it is also possible to use the ferroelectric FET as a memory cell while the ferroelectric film 22 has a downward polarization. In that case, the ferroelectric film 2
2 can be defined as data “0”, and a state in which almost no polarization exists in the ferroelectric film 22 can be defined as data “1”.

As described above, if imprinting is induced in advance while data "1" is held, the level of the read signal of data "1" does not change from the initial state due to imprinting. . Also, for the data “0”, in the present embodiment, the state where the polarization is almost zero corresponds to this, so that imprint is unlikely to occur. Therefore, according to the present embodiment, the imprint hardly progresses in any state of the data “1” and the data “0”, so that the level of the read signal does not change from the initial value. The effect of the ferroelectric FET of the present embodiment is that the ferroelectric FET of the present embodiment is arranged in a matrix,
Of the control gate electrode 23 of the first wiring 25 serving as a word line
And a memory cell array in which the drain region 16 of the ferroelectric FET is connected to a bit line.

(Other Embodiments) FIG. 12 is a sectional view of a ferroelectric FET having a so-called MFMIS structure. As shown in FIG. 1, the ferroelectric FET includes a silicon oxide film 12 provided on a silicon substrate 11, and an intermediate gate electrode 31 provided on the silicon oxide film 12 and made of a conductive material such as Pt. A ferroelectric film 32 provided on the intermediate gate electrode 31 and made of a metal oxide such as zircon-lead titanate (PZT) or bismuth strontium tantalate (SBT); and provided on the ferroelectric film 32. Control gate electrode 33 made of a conductive material such as Pt, and intermediate gate electrode 3 in silicon substrate 11.
1 is provided with a source region 15 and a drain region 16 provided on both sides, respectively. A region of the silicon substrate 11 below the silicon oxide film 12 is a channel region 17. Further, the control gate electrode 33 is connected to the first wiring 35, and the intermediate gate electrode 31
Are connected to the second wiring 36.

Using such a ferroelectric FET as a memory cell of a semiconductor memory device, as in the second embodiment,
Data can be written, rewritten, and read, and the same effects as in the second embodiment can be exhibited. In addition, as in the third embodiment, a process for causing the ferroelectric film 32 to imprint downward polarization is performed using the ferroelectric FET shown in FIG. 12 as a memory cell of a semiconductor memory device. be able to.

[0100]

According to the present invention, the state in which one polarization remains when no voltage is applied to the ferroelectric film is defined as a first logical value, and the state in which the other polarization remains remains unchanged. The second logical value is defined as the state up to the state where almost no polarization remains.
Since the data is stored, the data can be read while distinguishing between the first logical value and the second logical value even when the polarization hardly remains.
Data reading accuracy can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a ferroelectric FET having an MFIS structure according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a method of setting a gate bias at the time of reading according to the first embodiment.

FIGS. 3A, 3B, and 3C show readings when the residual polarization in the ferroelectric film of the ferroelectric FET according to the first embodiment is downward, upward, and almost zero, respectively. It is an energy band diagram at the time.

FIG. 4 is a sectional view of a memory cell of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a hysteresis characteristic diagram for describing a data write operation in a second embodiment on voltage-polarization coordinates.

FIG. 6 is a flowchart illustrating an example of a manufacturing process of a ferroelectric FET of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a hysteresis characteristic diagram showing a change in a hysteresis characteristic of a ferroelectric film 22 in a heat treatment step of a third embodiment.

FIG. 8 is a sectional view of a conventional MFISFET type ferroelectric FET.

FIGS. 9A, 9B, and 9C are energy band diagrams when the residual polarization in the ferroelectric film of the conventional ferroelectric FET is downward, upward, and almost zero, respectively. .

FIG. 10 is a characteristic diagram showing a relationship between a voltage applied to a gate electrode of a ferroelectric FET and a current between a source and a drain.

FIG. 11 is a hysteresis characteristic diagram for explaining the disturb phenomenon.

FIG. 12 is a cross-sectional view showing an example in which the second embodiment is applied to a ferroelectric FET having an MFMIS structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Silicon oxide film 13 Ferroelectric film 14 Gate electrode 15 Source region 16 Drain region 17 Channel region 18 First intermediate gate electrode 21 Second intermediate gate electrode 22 Ferroelectric film 23 Control gate electrode 25 First wiring 26 Second Wiring

Claims (20)

[Claims] An electric field effect comprising: a semiconductor substrate; a ferroelectric film and a gate electrode provided on the semiconductor substrate; and a source region and a drain region provided on both sides of the gate electrode in the semiconductor substrate. A first transistor formed on the ferroelectric film in response to a positive voltage from the gate electrode to the semiconductor substrate;
And a second polarization generated in the ferroelectric film in response to a negative voltage from the gate electrode to the semiconductor substrate, when no voltage is applied to the ferroelectric film. The state in which one of the first and second polarizations remains remains as the first logical value, and the polarization almost remains from the state in which the other of the first and second polarizations remains. A semiconductor memory device characterized in that data of one of the first logical value and the second logical value is stored in the ferroelectric film, with a state up to a state not being taken as a second logical value. . 2. The semiconductor memory device according to claim 1, wherein a bias voltage is applied to said gate electrode when data in said ferroelectric film is read. . 3. The semiconductor memory device according to claim 2, wherein the other polarization becomes zero in the ferroelectric film by repeating the read operation accompanied by the application of the bias voltage.
When data is read, a current substantially equal to the current value when the one polarization is written is applied to the source region.
The state flowing between the drain regions is defined as a first logical value, and the current from the current value between the source region and the drain region when the other polarization is written to the current value when the other polarization becomes substantially zero. Characterized in that the state in which the current flows is a second logical value. 4. A field effect transistor having a semiconductor substrate, a ferroelectric film and a gate electrode provided on the semiconductor substrate, and a source region and a drain region provided on both sides of the gate electrode in the semiconductor substrate. Wherein the first ferroelectric film is formed on the ferroelectric film according to a positive voltage from the gate electrode to the semiconductor substrate.
And a second polarization generated in the ferroelectric film in response to a negative voltage from the gate electrode to the semiconductor substrate, when no voltage is applied to the ferroelectric film. The state in which one of the first and second polarizations remains remains as the first logical value, and the state in which the polarization hardly remains in the ferroelectric film as the second logical value. A semiconductor memory device, wherein data of one of a first logical value and a second logical value is stored in the ferroelectric film. 5. The semiconductor memory device according to claim 4, wherein said ferroelectric film has said first logical value data and said second logical value data having different absolute values for said gate electrode. A semiconductor memory device which is written by applying a voltage. 6. The semiconductor memory device according to claim 4, further comprising: a gate insulating film provided on said semiconductor substrate; and an intermediate gate electrode provided on said gate insulating film. The ferroelectric film is provided on the intermediate gate electrode, and the gate electrode is provided on the ferroelectric film. When data is written, a voltage is applied between the gate electrode and the intermediate gate electrode. The first or second polarization can be left in the ferroelectric film by a voltage to be applied. When reading data, the intermediate gate electrode is floated and a bias voltage is applied to the gate voltage. A semiconductor memory device characterized in that it is configured to be capable of: 7. The semiconductor memory device according to claim 4, wherein a gate insulating film provided on the semiconductor substrate; a first intermediate gate electrode provided on the gate insulating film; A second intermediate gate electrode provided separately from and electrically connected to the first intermediate gate electrode, wherein the ferroelectric film is provided on the second intermediate gate electrode; When the data is written, the voltage applied between the gate electrode and the second intermediate gate electrode causes a remanent polarization in the ferroelectric film, while the data is written on the ferroelectric film. And a bias voltage applied to the gate voltage with the first and second intermediate gate electrodes floating when reading the data. 8. A semiconductor device comprising: a ferroelectric film and a gate electrode provided on a semiconductor substrate; and a source region and a drain region provided on both sides of the gate electrode in the semiconductor substrate.
The first ferroelectric film is formed on the ferroelectric film according to a positive voltage from the gate electrode to the semiconductor substrate.
For driving a semiconductor memory device having a field-effect transistor configured to generate a second polarization generated in the ferroelectric film in response to a negative voltage applied to the semiconductor substrate from the gate electrode. Wherein a state in which one of the first and second polarizations remains when no voltage is applied to the ferroelectric film is defined as a first logical value, A method of reading data from the ferroelectric film, wherein a second logical value is used as a second logical value from a state in which the other polarization remains to a state in which almost no polarization remains. 9. The method of driving a semiconductor memory device according to claim 8, wherein a bias voltage is applied to said gate electrode when reading data in said ferroelectric film. . 10. The method for driving a semiconductor memory device according to claim 9, wherein the one of the polarizations in the ferroelectric film becomes weaker toward 0 by repeating the read operation accompanied by the application of the bias voltage. When reading data, a state in which a current value substantially equal to the current value when the one polarization is written flows between the source region and the drain region is defined as a first logical value, and the other polarization is defined as a first logical value. A state in which a current in a range from the current value between the source region and the drain region at the time of writing to the current value when the other polarization becomes substantially zero is defined as a second logical value. A method for driving a semiconductor memory device. 11. The method of driving a semiconductor memory device according to claim 9, wherein the bias voltage applied to the gate electrode is such that data in the ferroelectric film has a first logical value and a second logical value. A difference between currents flowing between the source region and the drain region sometimes being substantially the maximum. 12. A ferroelectric film, comprising: a ferroelectric film and a gate electrode provided on a semiconductor substrate; and source and drain regions provided on both sides of the gate electrode in the semiconductor substrate. Is generated in the ferroelectric film in response to a positive voltage applied to the semiconductor substrate from the gate electrode, and is generated in the ferroelectric film in response to a negative voltage applied to the semiconductor substrate from the gate electrode A method of driving a semiconductor memory device including a field-effect transistor configured to generate a second polarization, wherein the first and second voltages are not applied to the ferroelectric film. A state in which one of the polarizations remains remains as a first logical value, and a state in which the polarization hardly remains in the ferroelectric film as a second logical value stores data in the ferroelectric film. , When reading the data of the serial ferroelectric film is a driving method of a semiconductor memory device and applying a bias voltage to the gate electrode. 13. The method of driving a semiconductor memory device according to claim 12, wherein at the time of writing data to said ferroelectric film, said first logic value is written and said second logic value is written.
A method of driving a semiconductor memory device, wherein an absolute value of a voltage applied to the gate electrode is made different from when a logical value is written. 14. The method of driving a semiconductor memory device according to claim 12, further comprising: a gate insulating film provided on said semiconductor substrate; and an intermediate gate electrode provided on said gate insulating film. The ferroelectric film is provided on the intermediate gate electrode, and the gate electrode is provided on the ferroelectric film. When writing data, the gate electrode and the intermediate gate electrode A method for driving a semiconductor memory device, wherein a voltage is applied between the gate electrodes and a bias voltage is applied to the gate voltage while the intermediate gate electrode is floating when data is read. 15. The method for driving a semiconductor memory device according to claim 12, wherein a gate insulating film provided on said semiconductor substrate, and a first intermediate gate electrode provided on said gate insulating film. ,
A second intermediate gate electrode provided separately from and electrically connected to the first intermediate gate electrode, wherein the ferroelectric film is provided on the second intermediate gate electrode; The electrode is provided on the ferroelectric film, and applies a voltage between the gate electrode and the second intermediate gate electrode when writing data, while the first and second electrodes are used when reading data. (2) A method for driving a semiconductor memory device, wherein a bias voltage is applied to the gate voltage with the intermediate gate electrode floating. 16. The method of driving a semiconductor memory device according to claim 12, wherein the data of the second logical value is written to the ferroelectric film. Wherein a bias voltage is applied to the gate electrode so that a voltage applied to the gate electrode is substantially equal to a coercive voltage of the ferroelectric film. 17. The method of driving a semiconductor memory device according to claim 12, wherein the intermediate gate electrode is formed after writing data to the ferroelectric film or immediately before reading data. A method for driving a semiconductor memory device, wherein the semiconductor memory device is floated after being grounded once. 18. The method of driving a semiconductor memory device according to claim 12, wherein when reading data written in the ferroelectric film, the data is applied to the ferroelectric film. A method for driving a semiconductor memory device, characterized in that a voltage is applied to the gate electrode so that a voltage is lower than a coercive voltage of the ferroelectric film. 19. A ferroelectric film, comprising: a ferroelectric film and a gate electrode provided on a semiconductor substrate; and a source region and a drain region provided on both sides of the gate electrode in the semiconductor substrate. Is generated in the ferroelectric film in response to a positive voltage applied to the semiconductor substrate from the gate electrode, and is generated in the ferroelectric film in response to a negative voltage applied to the semiconductor substrate from the gate electrode (A) forming a memory cell having a field-effect transistor configured to generate a second polarization; and a voltage having the same polarity as a voltage applied to the ferroelectric film for reading data. (B) releasing the voltage to leave the first polarization in the ferroelectric film after applying
Heating the ferroelectric film for a certain period of time to increase the coercive voltage required to reverse the hysteresis characteristic of the ferroelectric film from the first polarization to the second polarization. And (c) making the hysteresis characteristic of the ferroelectric film asymmetrical. 20. The method according to claim 19, further comprising, after the step (b), erasing the first polarization remaining in the ferroelectric film. Manufacturing method of a semiconductor memory device.