JP3805659B2 - Driving method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including a ferroelectric capacitor and a driving method thereof.
[0002]
[Prior art]
A semiconductor memory device including a ferroelectric capacitor is expected as a nonvolatile memory that can provide an unlimited number of readings.
[0003]
Hereinafter, a conventional semiconductor memory device having a ferroelectric capacitor will be described with reference to FIG.
[0004]
As shown in FIG. 8, a source region 2 and a drain region 3 are formed on the surface portion of the silicon substrate 1. Between the source region 2 and the drain region 3 on the silicon substrate 1, a strong oxide made of a metal oxide such as a silicon oxide film 4, zircon-lead zirconate titanate (PZT) or bismuth strontium tantalate (SBT). A dielectric film 5 and a gate electrode 6 are sequentially formed, and a ferroelectric FET is constituted by these.
[0005]
In this configuration, the direction of polarization of the ferroelectric film 5 can be set upward or downward, and the gate electrode 6 of the silicon substrate 1 corresponds to two states (upward or downward) of this polarization. The depth of the interface potential in the lower region can be set to two different states. Since the depth of the interface potential corresponds to the resistance between the source and the drain of the ferroelectric FET, the resistance between the source and the drain is either a high value or a low value depending on the polarization direction of the ferroelectric film 5. It becomes. As long as the polarization of the ferroelectric film 5 is maintained, the upward or downward polarization state is maintained (stored), so that the ferroelectric FET can be used as a nonvolatile memory device.
[0006]
In the ferroelectric FET having such a configuration, for example, a state in which the polarization of the ferroelectric film 5 is downward is associated with data “1”, and a state in which the polarization is upward is associated with data “0”. For example, when a ground potential is applied to the lower surface of the silicon substrate 1 and a strong positive voltage is applied to the gate electrode 6, the polarization of the ferroelectric film 5 can be set downward, and the ground potential is applied to the lower surface of the silicon substrate 1. When a strong negative voltage is applied to the gate electrode 6, the polarization of the ferroelectric film 5 can be set upward. Note that after the polarization of the ferroelectric film 5 is set downward or upward, the potential of the gate electrode 6 is set to the ground potential.
[0007]
FIGS. 9A, 9B and 9C show energy band diagrams when the conductivity type of the silicon substrate 1 is p-type and the conductivity type of the source region 2 and the drain region 3 is n-type. 9A shows the case where the polarization is downward (data “1”), FIG. 9B shows the case where the polarization is upward (data “0”), and FIG. Indicates the energy state of thermal equilibrium. 9A to 9C, 11 indicates the conduction band of the gate electrode 6, 12 indicates the energy band of the ferroelectric film 5, 13 indicates the energy band of the silicon oxide film 4, and 14 indicates silicon. An energy band of the substrate 1 is shown, and 15 is an energy band of a depletion layer formed near the surface of the silicon substrate 1. A white arrow indicates the direction of polarization of the ferroelectric film 5.
[0008]
When the polarization is downward (in the case of data “1”), as shown in FIG. 9A, the negatively ionized depletion layer 15 extends to a deep region in the silicon substrate 1. Potential drops below ground potential.
[0009]
On the other hand, when the polarization is upward (in the case of data “0”), holes as p-type carriers are accumulated on the surface of the silicon substrate 1 as shown in FIG. Since no depletion layer is formed, the interface potential of the silicon substrate 1 becomes the ground potential.
[0010]
As described above, since the interface potential on the lower side of the gate electrode 6 in the silicon substrate 1 differs depending on the direction of polarization, if a potential difference is given between the drain and source, the current flowing between the drain and source differs depending on the direction of polarization. become. That is, when the interface potential of the silicon substrate 1 is lower than the ground potential (data “1” state), the drain and the source have a low resistance (ON state), and thus a large current flows between the drain and the source. On the other hand, in the state where the interface potential of the silicon substrate 1 is the ground potential (data “0” state), the drain-source has a high resistance (OFF state), so that almost no current flows between the drain-source. . By detecting the current value between the drain and the source in this way, it is possible to know whether the ferroelectric FET is in the data “1” state or the data “0” state.
[0011]
In this manner, since it is possible to know whether the ferroelectric FET is in the data “1” state or the data “0” state, when the data is read from the ferroelectric FET, the ferroelectric film 5 Since the polarization is not reversed, so-called nondestructive data reading becomes possible. That is, after the data is read, an operation for restoring the direction or size of polarization, that is, a rewriting operation is not required.
[0012]
Thus, since the ferroelectric FET can perform a nondestructive read operation, the problem of fatigue and deterioration of the polarization of the ferroelectric film that occurs in the destructive read operation accompanied by polarization inversion does not occur. Accordingly, the ferroelectric FET is expected as a nonvolatile memory that can provide an unlimited number of readings.
[0013]
[Problems to be solved by the invention]
However, normally, the ferroelectric film 5 in the ferroelectric FET is a semiconductor having a large number of defect levels, and electrons and holes can easily move inside the ferroelectric film 5.
[0014]
Therefore, as shown in FIG. 9A, when the ferroelectric FET is in the ON state, electrons are injected from the conduction band 11 of the gate electrode 6 into the ferroelectric film 5, so that the charge at the beginning of the polarization is medium. As a result, the bottom of the V-shaped potential gradually rises, and a transition is made to a thermal equilibrium energy state as shown in FIG.
[0015]
On the other hand, as shown in FIG. 9B, when the ferroelectric FET is in the OFF state, holes are injected from the conduction band 11 of the gate electrode 6 into the ferroelectric film 5, so that the charge at the head of polarization is medium. Since the sum of the Λ-shaped potential is gradually lowered, the energy state of the thermal equilibrium shown in FIG.
[0016]
As a result, the interface potential of the silicon substrate 1 becomes the same level even though the polarization is directed in different directions such as upward or downward, so that the two states can be distinguished by the current between the drain and the source. There is a problem that it is difficult.
[0017]
This problem can be explained by the hysteresis curve 20 of the ferroelectric capacitor and the load line 21 of the gate capacitance of the ferroelectric FET drawn on the polarization-voltage (QV) plane shown in FIG. The structure of the ferroelectric FET shown in FIG. 8 is that when a virtual electrode is interposed between the ferroelectric film 5 and the silicon oxide film 4, the ferroelectric capacitor and the metal-oxide film-silicon (MOS) capacitor are provided. It can be regarded as a series circuit.
[0018]
In this series circuit, when the polarization is in the downward state (the state of data “1”) (the state corresponding to the energy band diagram of FIG. 8A), the polarization immediately after the data writing is at point 22, but the ferroelectric substance A negative bias voltage from the origin O to the point 22 is applied to the film 5. Since this bias voltage causes the injection of electrons into the ferroelectric film 5, the polarization moves from the point 22 to the origin O.
[0019]
On the other hand, when the polarization is in the upward state (the state of data “0”) (the state corresponding to the energy band diagram of FIG. 8B), the polarization immediately after the data writing is at the point 23, but the ferroelectric film 5 A positive bias voltage from origin O to point 23 is applied to. Since this bias voltage causes hole injection into the ferroelectric film 5, the polarization moves from the point 23 to the origin O.
[0020]
Thus, in the conventional ferroelectric FET, the difference between the data “1” and the data “0” is the difference in potential induced between the ferroelectric film 5 and the silicon oxide film 4 due to the direction of polarization. The potential induced between the ferroelectric film 5 and the silicon oxide film 4 becomes a driving force for injecting electrons or holes that eliminate the induced potential. That is, in the ferroelectric FET, there is a problem that voltage disappearance due to injection of electrons or holes into the ferroelectric film 5 cannot be avoided.
[0021]
In view of the above, an object of the present invention is to make it possible to read data held in a ferroelectric capacitor even if a potential difference applied to the ferroelectric capacitor disappears due to injection of electrons or holes. To do.
[0022]
[Means for Solving the Problems]
In order to achieve the above object, a first semiconductor memory device according to the present invention is formed on a semiconductor substrate, and includes a ferroelectric film, a first electrode formed on the ferroelectric film, and a ferroelectric film. A ferroelectric capacitor having a second electrode formed under the dielectric film; and a direction of polarization of the ferroelectric film from the first electrode to the second electrode or from the second electrode to the first A first state in which the ferroelectric film has a polarization value almost saturated, or a direction of polarization of the ferroelectric film is the same direction as the first state, and the ferroelectric film Means for writing the first state or data corresponding to the second state to the ferroelectric capacitor by generating a second state in which the film has a substantially zero polarization value; By detecting whether the state is the second state or the second state, the ferroelectric key And a means for reading data stored in Pashita.
[0023]
According to the first semiconductor memory device, the two directions in which the ferroelectric capacitor holds different data (for example, data “1” and data “0”) have the same direction of polarization of the ferroelectric film. The first state (for example, the state of data “1”) in which the ferroelectric film has a substantially saturated polarization value and the second state (for example, in the case of data “0”) in which the ferroelectric film has a substantially zero polarization value. Therefore, even if the potential difference applied to the ferroelectric capacitor disappears due to the injection of electrons or holes, the data held in the ferroelectric capacitor can be read out.
[0024]
In the first semiconductor memory device, the means for writing data applies a voltage between the first signal line connected to the first electrode and the second signal line connected to the second electrode. It is preferable that the first state or the second state is generated in the ferroelectric capacitor.
[0025]
In this way, the operation of writing the data “1” or the data “0” to the ferroelectric capacitor by causing the first state or the second state to occur in the ferroelectric capacitor can be performed easily and directly. Can do.
[0026]
In the first semiconductor memory device, the means for reading data induces an electric field in the same direction as the polarization direction of the ferroelectric film between the first electrode and the second electrode in the ferroelectric film. It is preferable to have means for generating such a voltage.
[0027]
In this way, even if a read voltage is applied to the ferroelectric capacitor, the direction of polarization of the ferroelectric film does not change, so the ferroelectric capacitor can continue to hold data, and the polarization of the ferroelectric capacitor It is possible to reduce fatigue deterioration.
[0028]
In the first semiconductor memory device, the means for reading data applies a read voltage to both ends of a capacitive load connected in series to the ferroelectric capacitor and a series circuit composed of the ferroelectric capacitor and the capacitive load. Means for detecting the voltage induced in the capacitive load by dividing the read voltage based on the ratio between the capacitance value of the ferroelectric capacitor and the capacitance value of the capacitive load, It is preferable to detect whether the state is the first state or the second state.
[0029]
In this way, the voltage induced in the capacitive load when the read voltage is applied to both ends of the series circuit composed of the ferroelectric capacitor and the capacitive load is held in the ferroelectric capacitor. Since the stored data can be read, the read operation is simplified.
[0030]
In the first semiconductor memory device, means for reading data includes a field effect transistor formed on the semiconductor substrate and having a gate electrode connected to the second electrode, and the first electrode and the semiconductor substrate or the field effect transistor. Means for applying a read voltage between the source electrode of the transistor and the read voltage is divided based on a ratio of a capacitance value of the ferroelectric capacitor and a gate capacitance value of the field effect transistor to be induced in the gate electrode. Thus, it is preferable to detect whether the ferroelectric capacitor is in the first state or the second state by detecting a change appearing in the channel conductance of the field effect transistor.
[0031]
In this way, a change in voltage induced in the gate electrode of the field effect transistor when a read voltage is applied between the first electrode and the semiconductor substrate or the source electrode of the field effect transistor is determined. Since it can be detected as a change in the channel conductance of the transistor, the read operation is simple and reliable.
[0032]
In the first semiconductor memory device, the means for reading data includes a bit line connected to the second electrode and a means for applying a read voltage between the first electrode and the bit line. Is divided based on the ratio between the capacitance value of the ferroelectric capacitor and the capacitance value of the bit line, and detects the voltage induced in the bit line, whereby the ferroelectric capacitor is in the first state or the second state. It may be a means for detecting whether this is the state.
[0033]
A second semiconductor memory device according to the present invention includes a ferroelectric film, a first electrode formed on the ferroelectric film, and a second electrode formed below the ferroelectric film. A memory cell block in which a plurality of memory cells each having a body capacitor and a cell selection transistor connected in series to a ferroelectric capacitor are connected, and a memory cell block Common node connected to The direction of polarization of the ferroelectric film of the ferroelectric capacitor selected by the cell selection transistor among the plurality of ferroelectric capacitors is directed from the first electrode to the second electrode. Or the first state in which the ferroelectric film is in the direction from the second electrode to the first electrode and the ferroelectric film has a substantially saturated polarization value, or the polarization of the ferroelectric film of the selected ferroelectric capacitor The second state is the same direction as the first state and the ferroelectric film has a substantially zero polarization value, thereby causing the selected ferroelectric capacitor to have the first state or Means for writing data corresponding to the second state;
The common node And a means for applying a read voltage between the capacitive load and the capacitance value of the ferroelectric capacitor selected by the cell selection transistor among the plurality of ferroelectric capacitors and the capacitive load Whether the selected ferroelectric capacitor is in the first state or the second state by detecting the voltage induced in the capacitive load by being divided based on the ratio to the capacitance value of Means for reading out data stored in the selected ferroelectric capacitor by detection.
[0034]
According to the second semiconductor memory device, the two directions in which the ferroelectric capacitor holds different data (for example, data “1” and data “0”) have the same direction of polarization of the ferroelectric film. The first state (for example, the state of data “1”) in which the ferroelectric film has a substantially saturated polarization value and the second state (for example, in the case of data “0”) in which the ferroelectric film has a substantially zero polarization value. Therefore, even if the potential difference applied to the ferroelectric capacitor disappears due to injection of electrons or holes, it is possible to realize a memory cell array that can read data held in the ferroelectric capacitor. it can.
[0035]
The first semiconductor memory device driving method according to the present invention is formed on a semiconductor substrate, under the ferroelectric film, the first electrode formed on the ferroelectric film, and the ferroelectric film. A step of writing data to a ferroelectric capacitor having a second electrode formed on the substrate, and a step of reading data stored in the ferroelectric capacitor, wherein the step of writing data comprises polarization of the ferroelectric film. Is a first state in which the direction from the first electrode toward the second electrode or the direction from the second electrode toward the first electrode and the ferroelectric film has a substantially saturated polarization value, or the ferroelectric film The second state is generated in the same direction as the first state and the ferroelectric film generates a second state having a substantially zero polarization value, so that the ferroelectric capacitor corresponds to the first state or the second state. Including the process of writing the data to be read. Out step, by detecting whether the ferroelectric capacitor is or second in the first state condition, comprising the step of reading the data stored in the ferroelectric capacitor.
[0036]
According to the driving method of the first semiconductor memory device, the two directions in which the ferroelectric capacitor holds different data (for example, data “1” and data “0”) are the same in the polarization direction of the ferroelectric film. The first state (for example, the state of data “1”) where the ferroelectric film has a substantially saturated polarization value and the second state (for example, the data “1” where the ferroelectric film has a substantially zero polarization value). Therefore, even if the potential difference applied to the ferroelectric capacitor disappears due to the injection of electrons or holes, the ferroelectric capacitor can continue to hold data. It is possible to reduce the fatigue deterioration of polarization.
[0037]
In the driving method of the first semiconductor memory device, in the data writing step, a voltage is applied between the first signal line connected to the first electrode and the second signal line connected to the second electrode. Preferably, the method includes a step of applying and causing the ferroelectric capacitor to generate the first state or the second state.
[0038]
In this way, the operation of writing the data “1” or the data “0” to the ferroelectric capacitor by causing the first state or the second state to occur in the ferroelectric capacitor can be performed easily and directly. Can do.
[0039]
In the driving method of the first semiconductor memory device, in the step of reading data, the potential of the second signal line is set to the ground potential, and then the connection between the second electrode and the second signal line is disconnected. A step of reading data stored in the ferroelectric capacitor by setting the two electrodes in a floating state and then detecting whether the ferroelectric capacitor is in the first state or the second state. It is preferable to include.
[0040]
As described above, once the potential of the second signal line is set to the ground potential, the potential of the second electrode is determined. Therefore, the second electrode is formed by the write operation or the read operation performed before the read operation. Unnecessary charges accumulated in the substrate are removed. In addition, when the read voltage is applied after the connection between the second electrode and the second signal line is cut to leave the second electrode in a floating state, the ferroelectric capacitor is in the first state or Whether the state is the second state can be reliably detected.
[0041]
In the driving method of the first semiconductor memory device, the step of reading data includes an electric field in the same direction as the polarization direction of the ferroelectric film between the first electrode and the second electrode. It is preferable to include a step of generating a voltage that can be induced.
[0042]
In this way, even if a read voltage is applied to the ferroelectric capacitor, the direction of polarization of the ferroelectric film does not change, so the ferroelectric capacitor can continue to hold data.
[0043]
In the first method for driving a semiconductor memory device, the step of reading data is performed by applying a read voltage to both ends of a series circuit including a ferroelectric capacitor and a capacitive load connected in series to the ferroelectric capacitor. Whether the ferroelectric capacitor is in the first state by detecting a voltage induced in the capacitive load by dividing the voltage based on a ratio between the capacitance value of the ferroelectric capacitor and the capacitance value of the capacitive load Or it is preferable to include the process of detecting whether it is a 2nd state.
[0044]
In this way, the voltage induced in the capacitive load when the read voltage is applied to both ends of the series circuit composed of the ferroelectric capacitor and the capacitive load is held in the ferroelectric capacitor. Since the stored data can be read, the read operation is simplified.
[0045]
In the driving method of the first semiconductor memory device, the step of reading data includes a first electrode and a source electrode of a field effect transistor formed on the semiconductor substrate and having a gate electrode connected to the second electrode. A field-effect type is applied by applying a readout voltage to the semiconductor substrate and inducing the readout voltage to the gate electrode by dividing the readout voltage based on the ratio between the capacitance value of the ferroelectric capacitor and the gate capacitance value of the field-effect transistor. Preferably, the method includes detecting whether the ferroelectric capacitor is in the first state or the second state by detecting a change appearing in the channel conductance of the transistor.
[0046]
In this manner, when a read voltage is applied between the first electrode and the semiconductor substrate or the source electrode of the field effect transistor, a voltage induced in the gate electrode of the field effect transistor is reduced. Since it can be detected by detecting a change appearing in the channel conductance, the read operation is simple and reliable.
[0047]
In the first method for driving a semiconductor memory device, in the step of reading data, a read voltage is applied between the first electrode and the bit line connected to the second electrode, and the read voltage is a ferroelectric capacitor. Whether the ferroelectric capacitor is in the first state or the second state by detecting the voltage induced in the bit line by being divided based on the ratio between the capacitance value of the capacitor and the capacitance value of the bit line May be included.
[0048]
In the method for driving the first semiconductor memory device, when the ferroelectric capacitor is at least in the second state, the read voltage applied to the first electrode is removed in the step of reading data, and then the second electrode It is preferable to further include a step of setting the potential to the ground potential.
[0049]
In this way, the polarization of the ferroelectric film returns to the state before the data is read, so that the data read operation can be repeated even when the ferroelectric capacitor is in the second state.
[0050]
A second semiconductor memory device driving method according to the present invention includes a ferroelectric film, a first electrode formed on the ferroelectric film, and a second electrode formed below the ferroelectric film. Cell among a plurality of ferroelectric capacitors constituting a memory cell block in which a plurality of memory cells each having a ferroelectric capacitor and a cell selection transistor connected in series to the ferroelectric capacitor are connected in series A process of writing data to the ferroelectric capacitor selected by the selection transistor, and data stored in the ferroelectric capacitor selected by the cell selection transistor among the plurality of ferroelectric capacitors constituting the memory cell block And the step of writing data is a memory cell block. To the common node connected to When a write voltage is applied, the direction of polarization of the ferroelectric film of the ferroelectric capacitor selected by the cell selection transistor is the direction from the first electrode to the second electrode or from the second electrode to the first A first state in which the ferroelectric film has a polarization value almost saturated, or a direction of polarization of the ferroelectric film of the selected ferroelectric capacitor is the same as the first state. By generating a second state in which the ferroelectric film has a polarization value of substantially zero, the data corresponding to the first state or the second state is stored in the selected ferroelectric capacitor. A process of reading data, including a process of writing Is the common node Is applied between the capacitive load and the capacitive load, and the readout voltage is divided based on the ratio between the capacitance value of the ferroelectric capacitor selected by the cell selection transistor and the capacitance value of the capacitive load, and thus capacitive. By detecting the voltage induced in the load, it is stored in the ferroelectric capacitor by detecting whether the selected ferroelectric capacitor is in the first state or the second state. A step of reading out the existing data.
[0051]
According to the driving method of the second semiconductor memory device, the two directions in which the ferroelectric capacitor holds different data (for example, data “1” and data “0”) are the same in the polarization direction of the ferroelectric film. The first state (for example, the state of data “1”) where the ferroelectric film has a substantially saturated polarization value and the second state (for example, the data “1” where the ferroelectric film has a substantially zero polarization value). The data stored in the ferroelectric capacitor constituting the memory cell array is read even if the potential difference applied to the ferroelectric capacitor disappears due to the injection of electrons or holes. be able to.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
The semiconductor memory device and the driving method thereof according to the first embodiment of the present invention will be described below with reference to FIGS.
[0053]
FIG. 1 shows a cross-sectional structure of the semiconductor memory device according to the first embodiment. For example, a source region 101 and a drain region 102 made of an n-type impurity layer are formed on a surface portion of a p-type silicon substrate 100. Thus, a channel region 103 is formed between the source region 101 and the drain region 102 in the surface portion of the silicon substrate 100. A floating gate electrode 105 is provided between the source region 101 and the drain region 102 on the silicon substrate 100 via a gate insulating film 104 made of a silicon oxide film. The source region 101, the drain region 102, the channel region 103, the gate insulating film 104, and the floating gate electrode 105 constitute a field effect transistor transistor (hereinafter referred to as FET).
[0054]
A ferroelectric capacitor 113 is provided above the floating gate electrode 105 via an insulating film (not shown). The ferroelectric capacitor 113 is formed on the ferroelectric film 110 and the ferroelectric film 110. The first electrode 111 is formed, and the second electrode 112 is formed under the ferroelectric film 110. A first signal line 121 is connected to the first electrode 111, and a second signal line 122 is connected to the second electrode 112 and the floating gate electrode 105. That is, the second electrode 112 and the floating gate electrode 105 are connected via the second signal line 122. The ferroelectric film 110 is made of, for example, SBT and has a film thickness of, for example, 200 nm. In this case, the coercive voltage of the ferroelectric film 110 is approximately 1V.
[0055]
The semiconductor memory device according to the first embodiment is characterized in that a voltage for changing the polarization of the ferroelectric film 110 is changed between the first signal line 121 and the second signal line 122 during an operation of writing data. And the potential of the floating gate electrode 105 can be determined by the second signal line 122 before the data read operation.
[0056]
(Data write operation)
In the semiconductor memory device according to the first embodiment, the operation of writing data is performed in the direction in which the polarization direction of the ferroelectric film 110 is directed from the first electrode 111 toward the second electrode 112 (downward direction) or A first state (for example, data “1”) is generated in a direction (upward direction) from the second electrode 112 to the first electrode 111 and the ferroelectric film 110 has a substantially saturated polarization value. Or the second state (for example, data “0”) in which the direction of polarization of the ferroelectric film 110 is the same as that of the first state and the ferroelectric film 110 has a substantially zero polarization value. This is done by generating. That is, the state of data “1” and the state of data “0” are distinguished by two states having the same polarization direction but different polarization values.
[0057]
A specific example of the data writing operation will be described below with reference to a hysteresis curve drawn on the QV plane shown in FIG. In FIG. 2, the solid line shows the hysteresis curve of the ferroelectric film 110 of the semiconductor memory device according to the first embodiment, and the broken line shows the hysteresis curve of the ferroelectric film 5 of the conventional ferroelectric FET.
[0058]
In the following description, it is assumed that the potential of the silicon substrate 100 is always the ground potential, and the polarization value when the polarization direction is downward is positive.
[0059]
In the semiconductor memory device according to the first embodiment, the polarization value of the ferroelectric film 110 before the data is written is substantially zero, so the position of the polarization is in the vicinity of the origin O.
[0060]
When data “1” is written to the ferroelectric film 110, for example, the potential of the second signal line 122 is set to the ground potential, and the potential of the first signal line 121 is set to 3V. In this way, the polarization of the ferroelectric film 110 changes from the origin O to the point a along the solid line. ₁ Move up. Thereafter, when the potential of the first signal line 121 is set to the ground potential, the polarization is changed along the solid line to the point a. ₁ To point a ₀ The ferroelectric film 110 is about 10 μC / cm ² Are stored as data “1”.
[0061]
Next, when data “1” is rewritten to data “0”, the potential of the first signal line 121 is set to about −1V while the potential of the second signal line 122 is set to the ground potential. In this way, the polarization of the ferroelectric film 110 is caused by the point a along the solid line. ₀ To point b ₁ Move up. Thereafter, when the potential of the first signal line 121 is set to the ground potential, the polarization is along the solid line at the point b. ₁ To point b ₀ Move to. Note that point b ₀ Are positive and near the origin O. Thereby, the ferroelectric film 110 is positive and about 0 μC / cm. ² Is stored as data “0”.
[0062]
In order to write data “0”, instead of setting the potential of the second signal line 122 to the ground potential and setting the potential of the first signal line 121 to about −1V, the first signal line The potential of 121 may be set to the ground potential, and the potential of the second signal line 122 may be set to 1V.
[0063]
In the first embodiment, in order to write the data “0”, it is not necessary to set the potential of the second signal line 122 to the ground potential and the potential of the first signal line 121 to −3V. . The reason is that in the present invention, the charge due to polarization is positive and about 0 μC / cm. ² Is defined as data “0”, the polarization value when data “0” is written is approximately 0 μC / cm. ² This is because it is sufficient.
[0064]
(Data read operation)
In the semiconductor memory device according to the first embodiment, the operation of reading data is performed in a first state where the ferroelectric film 110 has a substantially saturated polarization value (for example, a state where data “1” is held). Or whether the ferroelectric film 110 is in the second state (for example, the state holding data “0”) having a substantially zero polarization value.
[0065]
Hereinafter, a specific example of the data reading operation will be described.
[0066]
First, the potential of the second signal line 122 is set to the ground potential, and the potential of the floating gate electrode 105 is determined. This is for removing unnecessary charges accumulated in the floating gate electrode 105 by the write operation and the read operation performed until this read operation.
[0067]
Next, after the second signal line 122 is disconnected from the peripheral circuit, a predetermined read voltage V is applied to the first signal line 121. _R Apply. Read voltage V _R Is divided into a voltage applied to the ferroelectric film 110 and a voltage applied to the gate insulating film 105 based on the ratio between the capacitance value of the ferroelectric capacitor 113 and the gate capacitance value of the FET.
[0068]
Hereinafter, this operation will be described with reference to FIG. In FIG. 3, 131 is a first load line representing the gate capacitance of the FET when the potential of the first electrode 111 is 0V, and 132 is the potential of the first electrode 111 being V. _R It is the 2nd load line showing the gate capacity of FET when it is (about 2V).
[0069]
When the polarization value of the ferroelectric film 110 is large (when data “1” is held), the floating gate electrode 105 has V in FIG. _G1 Is generated. In this case, the direction of the electric field applied to the ferroelectric film 110 coincides with the direction of polarization holding the data “1”, and the polarization is a point a. ₀ To a ₂ Move up. Since the polarization value is almost saturated, the read voltage V _R However, the direction and magnitude of the polarization remain the same as before the reading operation.
[0070]
On the other hand, when the polarization value of the ferroelectric film 110 is small (when data “0” is held), the floating gate electrode 105 has a V of FIG. _G0 Is generated. Also in this case, the direction of the electric field applied to the ferroelectric film 110 coincides with the direction of polarization holding data “0”, and the polarization is the point b. ₀ To b ₂ Move up.
[0071]
By the way, when the data reading operation is repeated when the polarization value of the ferroelectric film 110 is small (when data “0” is held), the polarization value gradually increases, and data “1” and data “0” The difference in the polarization value from “is reduced, and the data cannot be distinguished.
[0072]
Therefore, the first signal line 121 is grounded with the second signal line 122 opened, and the read voltage V _R Remove. In this way, the ferroelectric film 110 has V _R The opposite of the potential difference, the polarization will follow the point b along the small hysteresis curve ₂ To point b _Three Through point b _Four Move to. Thereafter, when the second signal line 122 is grounded, the polarization is the point b. _Four To point b ₀ Therefore, the state in which the polarization value of the ferroelectric film 110 is small (the state in which the data “0” is retained) is restored.
[0073]
Therefore, data can be read even if the data read operation is repeated when the polarization value of the ferroelectric film 110 is small (when data “0” is held).
[0074]
By the way, the read voltage V _R As is apparent from FIG. 3, the voltage applied to the floating gate electrode 105 of the FET by the application of V _G0 > V _G1 There is a relationship.
[0075]
According to the experiments by the present inventors, when the capacitance value of the ferroelectric capacitor is set to approximately four times the gate capacitance value of the FET, the read voltage V _R Is set to 2V, a voltage of approximately 0.5V is induced in the floating gate electrode 105, and V _G0 And V _G1 The difference from this was almost 60 mV.
[0076]
As described above, according to the first embodiment, the polarization is automatically restored to the original position after the read operation regardless of whether the data “1” or the data “0” is read. No operation is required, and a so-called non-destructive read operation can be realized.
[0077]
Further, according to the first embodiment, even if both data “1” and data “0” are read, the polarization is not reversed (the polarization does not become negative), so that the fatigue deterioration of the polarization is greatly reduced.
[0078]
Hereinafter, test results performed for evaluating the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 4 and 5. FIG.
[0079]
In the equivalent circuit shown in FIG. 4, when data “1” is written, a write voltage V between the first electrode and the second electrode of the ferroelectric capacitor CF is written. _W = 5V is applied, and when data “0” is written, the write voltage V is applied between the first electrode and the second electrode of the ferroelectric capacitor CF. _W = -1V is applied, and when reading data, the read voltage V is applied to the set line SET. _R = 2.2V is applied continuously in a pulsed manner, and a field effect transistor Q for reading is applied. _a Output V _OUT Was measured.
[0080]
FIG. 5 shows the number of reads and the output V when data is read using the equivalent circuit shown in FIG. _OUT Shows the relationship. As can be seen from FIG. 5, the read voltage V _R 10 ¹² Even when applied repeatedly, there is almost no change in the difference in output level in both data “1” and data “0”, and the difference in output level is almost constant, that is, the fatigue deterioration of polarization does not appear. It was proved.
[0081]
(Second Embodiment)
Hereinafter, a semiconductor memory device and a driving method thereof according to the second embodiment of the present invention will be described with reference to FIG.
[0082]
As shown in FIG. 6, the semiconductor memory device according to the second embodiment has the same configuration as that of the ferroelectric capacitor 113 according to the first embodiment, and is formed on the ferroelectric film and the ferroelectric film. Ferroelectric capacitor CF having a first electrode formed on the substrate and a second electrode formed below the ferroelectric film ₀ , CF ₁ , ..., CF _n And the source region of each ferroelectric capacitor CF ₀ , CF ₁ , ..., CF _n Cell select transistor Q connected to the second electrode of ₀ , Q ₁ , ..., Q _n And a memory cell block formed by connecting a plurality of memory cells connected in succession.
[0083]
One end of the memory cell block is a cell selection transistor Q ₀ , Q ₁ , ..., Q _n A first common node 201 commonly connected to each drain region of the first and second ferroelectric capacitors CF ₀ , CF ₁ , ..., CF _n A second common node 202 commonly connected to the first electrode, a control line 203 having one end connected to the other end of the first common node 201, and a gate electrode other than the first common node 201. A read transistor (capacitive load) 204 connected to the end, a block select transistor 205 having a drain region connected to the set line SET and a source region connected to the other end of the second common node 202, and a drain region The reset transistor 206 is connected to the other end of the control line 203 and the source region is connected to the reset line RST.
[0084]
The cell selection transistor Q ₀ , Q ₁ , ..., Q _n Each gate electrode has a word line WL ₀ , WL ₁ , ... WL _n Are connected, the drain region of the read transistor 204 is connected to the reset line RST, and the source region of the read transistor 204 is connected to the bit line BL.
[0085]
The reset line RST is connected to the source region of the read transistor 204, but is instead connected to the semiconductor substrate on which the read transistor 204 is formed (portion indicated by an upward arrow in FIG. 6). May be.
[0086]
(Data write operation)
Hereinafter, an operation of writing data will be described.
[0087]
First, the block selection transistor 205 is turned on to make the set line SET and the second common node 202 conductive, and the reset transistor 206 is turned on to make the reset line RST and the control line 203 conductive. In addition, the word line of the memory cell to which data is written is turned on, and the cell selection transistor constituting the memory cell to which data is written is turned on.
[0088]
Next, a potential difference is applied between the set line SET and the reset line RST, and the write voltage V is applied between the second common node 202 and the control line 203. _WR Is applied, a plurality of ferroelectric capacitors CF ₀ , CF ₁ , ..., CF _n The write voltage V between the first electrode and the second electrode of the selected ferroelectric capacitor _WR Is directly applied, so that data is written to the selected ferroelectric capacitor.
[0089]
Write voltage V _WR The size of the ferroelectric film is the same as that in the first embodiment, and the polarization of the ferroelectric film is in the direction from the first electrode toward the second electrode or in the direction from the second electrode toward the first electrode. And the ferroelectric film generates a first state (data “1” state) having a substantially saturated polarization value, or the polarization of the ferroelectric film is in the same direction as the first state. In addition, the ferroelectric film is generated by generating a second state (data “0” state) having a substantially zero polarization value.
[0090]
(Data read operation)
The data read operation will be described below.
[0091]
First, the block selection transistor 205 is turned on to connect the set line SET and the second common node 202. Further, after the reset transistor 206 is turned on and the control line 203 is once grounded, the reset transistor 206 is turned off and the connection between the control line 203 and the reset line RST is disconnected to bring the control line 203 to a floating potential. In addition, the word line of the memory cell from which data is read is turned on, and the cell selection transistor constituting the memory cell to which data is written is turned on.
[0092]
Next, a potential difference is applied between the set line SET and the reset line RST, and the read voltage V is applied between the second common node 202 and the reset line RST. _R Is applied to the read voltage V _R Is divided based on the ratio between the capacitance value of the selected ferroelectric capacitor and the gate capacitance value of the read transistor 204, and the divided voltage is applied to the gate electrode of the read transistor 204. That is, since a voltage determined according to data (“1” or “0”) stored in the selected ferroelectric capacitor is applied to the gate electrode of the read transistor 204, the voltage between the drain and source of the read transistor 204 The data stored in the selected ferroelectric capacitor can be read out by detecting the current flowing through, and thus the channel conductance of the read transistor 204.
[0093]
According to the second embodiment, as in the first embodiment, when reading either data “1” or data “0”, a rewrite operation is not required after the read operation, and a so-called nondestructive read operation is performed. Can be realized.
[0094]
Further, according to the second embodiment, since the polarization is not reversed after the data is read (the polarization does not become negative), the fatigue deterioration of the polarization is greatly reduced.
[0095]
Furthermore, since the read transistor 204 is shared by a plurality of ferroelectric capacitors, a highly integrated memory array with excellent area efficiency can be realized.
[0096]
(Modification of the second embodiment)
Hereinafter, a semiconductor memory device and a driving method thereof according to a modification of the second embodiment of the present invention will be described with reference to FIG.
[0097]
In the modification of the second embodiment, the first common node 201 becomes a bit line and the capacitive load connected to the other end of the first common node 201 is different from that of the second embodiment. Since only the difference is the same and the other configuration is the same as that of the second embodiment, only the capacitive load will be described below.
[0098]
A bit line capacitor 207 is connected to the first common node 201, and a sense amplifier 208 is connected to the other end of the first common node 201.
[0099]
In the data read operation, a read voltage V between the second common node 202 and the reset line RST. _R Is applied to the read voltage V _R Is divided based on the ratio between the capacitance value of the selected ferroelectric capacitor and the capacitance value of the bit line capacitance 207, and the divided voltage is applied to the sense amplifier 208. In other words, the sense amplifier 208 detects the voltage determined according to the data (“1” or “0”) stored in the selected ferroelectric capacitor, and is stored in the selected ferroelectric capacitor. Data can be read.
[0100]
【The invention's effect】
According to the first or second semiconductor memory device or the driving method of the first or second semiconductor memory device according to the present invention, two states in which the ferroelectric capacitor holds different data are changed in the polarization of the ferroelectric film. Are distinguished from each other by a first state in which the ferroelectric film has a polarization value that is substantially saturated and a second state in which the ferroelectric film has a polarization value that is substantially zero. Even if the potential difference applied to the body capacitor disappears due to the injection of electrons or holes, the ferroelectric capacitor can continue to hold data, and fatigue deterioration of the polarization of the ferroelectric can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a semiconductor memory device according to a first embodiment.
FIG. 2 is a diagram showing a relationship between the potential of the first electrode and the polarization of the ferroelectric film when data “1” or data “0” is written in the semiconductor memory device according to the first embodiment. .
FIG. 3 is a diagram showing the relationship between the potential of a floating gate electrode and the polarization of a ferroelectric film when reading data “1” or data “0” from the semiconductor memory device according to the first embodiment.
FIG. 4 is an equivalent circuit diagram of the semiconductor memory device according to the first embodiment.
FIG. 5 is a diagram showing the relationship between the number of reads and the output when a read voltage is applied in a pulse manner to the semiconductor memory device according to the first embodiment.
FIG. 6 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment.
FIG. 7 is a circuit diagram showing a configuration of a semiconductor memory device according to a modification of the second embodiment.
FIG. 8 is a cross-sectional view of a conventional semiconductor memory device.
FIGS. 9A to 9C are energy band diagrams between a gate electrode and a silicon substrate in a conventional semiconductor memory device.
FIG. 10 is a diagram showing the relationship between the potential of the gate electrode and the polarization of the ferroelectric film when data “1” or data “0” is written in the conventional semiconductor memory device.
[Explanation of symbols]
100 silicon substrate
101 Source area
102 Drain region
103 channel region
104 Gate insulation film
105 Floating gate electrode
110 Ferroelectric film
111 first electrode
112 second electrode
113 Ferroelectric capacitor
121 first signal
122 Second signal
131 First load line
132 Second load line
201 first common node
202 second common node
203 Control line
204 Read transistor
205 Block selection transistor
206 Reset transistor
207 bit line capacity
208 sense amplifier

Claims (5)

A ferroelectric formed on a semiconductor substrate and having a ferroelectric film, a first electrode formed on the ferroelectric film, and a second electrode formed below the ferroelectric film The data is stored in the ferroelectric capacitor by a step of writing data to the capacitor and detection means having a capacitive load connected to one of the first electrode and the second electrode of the ferroelectric capacitor. A step of detecting and reading data,
The step of writing the data includes
The direction of polarization of the ferroelectric film is a direction from the first electrode to the second electrode or a direction from the second electrode to the first electrode, and the ferroelectric film is substantially A first state having a saturated polarization value, or a second state in which the direction of polarization of the ferroelectric film is the same direction as the first state and the ferroelectric film has a polarization value of approximately zero And writing data corresponding to the first state or the second state to the ferroelectric capacitor by generating
The step of reading the data includes
Every time data is read once,
A read voltage is applied to both ends of a series circuit including the ferroelectric capacitor and the capacitive load, and the read voltage is divided based on a ratio between a capacitance value of the ferroelectric capacitor and a capacitance value of the capacitive load. A first step of reading the data by detecting a voltage applied to the capacitive load and detecting a polarization deviation of the ferroelectric film;
A second step of removing the read voltage after the first step;
After the second step, a third step of setting a potential difference between the first electrode and the second electrode of the ferroelectric capacitor generated after the second step to zero. By doing
Detecting by the detecting means whether the ferroelectric capacitor is in the first state or the second state, and reading data stored in the ferroelectric capacitor;
The magnitude of the read voltage applied in the first step is such that the polarization direction of the ferroelectric film does not change when the read voltage is applied,
In the semiconductor memory, the read voltage is removed in the second step, and then the polarized state in which the ferroelectric film is displaced is returned to the polarization state before the data is read in the third step. Device driving method.   The data writing means is configured to apply a voltage between a first signal line connected to the first electrode and a second signal line connected to the second electrode connected to the second electrode. 2. The method of driving a semiconductor memory device according to claim 1, wherein the first state or the second state is generated in the ferroelectric capacitor by applying the ferroelectric capacitor. The capacitive load is a field effect transistor connected to the second electrode;
The step of reading the data includes
When the voltage divided based on the ratio of the capacitance value of the ferroelectric capacitor and the gate capacitance value of the field effect transistor is applied to the gate electrode of the field effect transistor, the field effect is obtained. Detecting whether the ferroelectric capacitor is in the first state or the second state by detecting a current flowing between the drain region and the source region of the transistor. The method of driving a semiconductor memory device according to claim 1. The capacitive load is a bit line connected to the second electrode;
The step of reading the data includes
The read voltage is divided based on a ratio between a capacitance value of the ferroelectric capacitor and a capacitance value of the bit line, and a voltage induced in the bit line is detected, so that the ferroelectric capacitor is the first capacitor. 2. The method of driving a semiconductor memory device according to claim 1, further comprising a step of detecting whether the state is the second state or the second state. Each stores data according to the polarization deviation of the ferroelectric film, and is connected in parallel to each of the plurality of ferroelectric capacitors connected in series to each other and the plurality of ferroelectric capacitors. A plurality of selection transistors for selecting the ferroelectric capacitors to be read, and one end side of the plurality of ferroelectric capacitors connected in series, and the ferroelectric capacitors selected by the selection transistors are selected. A method for driving a semiconductor memory device having detection means for reading out the data by detecting a polarization deviation of the dielectric film and having a capacitive load,
The step of reading the data includes
Every time data is read once,
A read voltage is applied to both ends of a series circuit including the ferroelectric capacitor and the capacitive load, and the read voltage is divided based on a ratio between a capacitance value of the ferroelectric capacitor and a capacitance value of the capacitive load. A first step of reading the data by detecting a voltage applied to the capacitive load and detecting a polarization deviation of the ferroelectric film;
A second step of removing the read voltage after the first step;
After the second step, a third step of setting a potential difference between the first electrode and the second electrode of the ferroelectric capacitor generated after the second step to zero. Including
The magnitude of the read voltage applied in the first step is the direction of polarization of the ferroelectric film when applied between the one electrode and the other electrode of the ferroelectric capacitor. Is a size that does not change,
In the semiconductor memory, the read voltage is removed in the second step, and then the polarized state in which the ferroelectric film is displaced is returned to the polarization state before the data is read in the third step. Device driving method.

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