JP2006066932A - Method of manufacturing semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor memory device, having high accuracy of reading data, utilizing the polarization state of a ferroelectric film. <P>SOLUTION: In reading data, corresponding to the polarization state from the ferroelectric film 22 that can generate upward or downward residual polarization, a bias voltage is applied to a control gate electrode 23, to read the data. For example, supposing that the state that downward residual polarization exists represents data "1", and the state that upward or almost zero residual polarization exists represents data "0". In particular, by defining that the state that almost zero residual polarization exists represents data "0", the precision of reading is enhanced since the read current for data "0" is almost constant. Also the precision of reading is further improved, if imprinting is induced to one piece of the data (for example, data "1") in advance. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor memory device having a structure in which the potential of a channel region of a field effect transistor is changed using the hysteresis characteristics of a ferroelectric thin film.

  Conventionally, a field effect transistor including a nonvolatile memory portion made of a ferroelectric thin film in a gate, for example, a field effect transistor called MFISFET, MFSFET, MFMISFET, or the like (hereinafter referred to as “ 2. Description of the Related Art A semiconductor memory device including a “ferroelectric FET” is known.

  FIG. 8 is a cross-sectional view of a conventional MFISFET type ferroelectric FET. As shown in the figure, a conventional ferroelectric FET includes a silicon oxide film 102 provided on a silicon substrate 101 and a zircon-lead titanate (PZT) or tantalum provided on the silicon oxide film 102. Ferroelectric film 103 made of a metal oxide such as bismuth strontium oxide (SBT), gate electrode 104 made of a conductive material such as Pt, and source regions provided on both sides of gate electrode 104 in silicon substrate 101 105 and a drain region 106. A region located below the silicon oxide film 102 in the silicon substrate 101 is a channel region.

  In the structure shown in FIG. 8, the ferroelectric film 103 has an upward (a state in which a dipole moment having a positive polarity on the upper side) or a downward direction depending on the polarity of the voltage applied between the gate electrode and the silicon substrate. It has a hysteresis characteristic that polarization occurs (a state in which a dipole moment having a positive electrode on the lower side is generated) and polarization remains even after the application of voltage is stopped. When no voltage is applied to the gate electrode 104, the channel region 107 of the ferroelectric FET has two potential depths different from each other corresponding to the two different types of residual polarization states. Is in a state. On the other hand, the resistance value between the source and the drain of the ferroelectric FET changes according to the potential depth of the channel region 107. Therefore, the resistance between the source and the drain is determined to be either a high value or a low value according to the two types of remanent polarization states of the ferroelectric film 103, and the resistance between the source and the drain is different between the two types. The state indicating one of the values is held (stored) as long as the state of remanent polarization of the ferroelectric film 103 is held. Therefore, a nonvolatile memory device can be configured using a ferroelectric FET.

  Here, in the conventional nonvolatile memory device using the ferroelectric FET, for example, a state in which downward remanent polarization is generated in the ferroelectric film 103 is set as data “1”, and the ferroelectric film 103 is set in the ferroelectric film 103. The state in which upward remanent polarization occurs is associated with data “0”. In order to cause downward residual polarization in the ferroelectric film 103, for example, the back surface of the silicon substrate 101 is set to the ground potential, a positive voltage is applied to the gate electrode 104, and then the voltage of the gate electrode 104 is set to the ground potential. return. In order to generate upward remanent polarization in the ferroelectric film 103, for example, the back surface of the silicon substrate 101 is set to the ground potential, a negative voltage is applied to the gate electrode 104, and then the voltage of the gate electrode 104 is grounded. Return to potential.

  FIGS. 9A, 9B, and 9C show, in order, the gate electrode 104, the ferroelectric film 103, and the silicon oxide film when the remanent polarization in the ferroelectric film 103 is downward, upward, and substantially zero, respectively. FIG. 4 is an energy band diagram showing an energy band state in a cross section passing through 102 and a channel region 107. 9A to 9C, the silicon substrate 101 is a P-type substrate, and the source region 105 and the drain region 106 are N-type semiconductor regions. The arrows in FIGS. 9A and 9B indicate the direction of polarization of the ferroelectric.

  To obtain the state shown in FIG. 9A, a positive voltage is applied to the gate electrode 104 with respect to the silicon substrate 101. The ferroelectric film 103 and the silicon oxide film 102 between the gate electrode 104 and the silicon substrate 101 are distributed at a ratio with a potential difference applied between the gate electrode 104 and the silicon substrate 101. At this time, if a voltage is applied to the gate electrode 104 so that the potential difference distributed to the ferroelectric film 103 is larger than the polarization inversion voltage of the ferroelectric film 103, the polarization of the ferroelectric film 3 becomes downward. Then, when the applied voltage is removed and the gate electrode 104 is returned to the ground voltage, downward remanent polarization occurs as shown in FIG. When the remanent polarization is downward (data “1” state), the ferroelectric film 103, the electric field generated between the positive electrode induced at the lower end of the ferroelectric film 103 and the negative electrode induced at the upper end, The energy bands of the silicon oxide film 102 and the channel region 107 are bent as shown in FIG. At this time, the region in the vicinity of the interface between the channel region 107 and the silicon oxide film 102 is negatively ionized and the depletion layer expands to the depth of the substrate, and the potential in the region in the channel region 107 near the interface with the silicon oxide film 102 is greater than the ground potential. Also lower. That is, a so-called inversion layer is formed.

  On the other hand, in order to obtain the state shown in FIG. 9B, a negative potential difference in which the potential difference distributed to the ferroelectric film 103 on the gate electrode 104 with respect to the silicon substrate 101 is larger than the polarization inversion voltage of the ferroelectric substance. Apply voltage. In this case, when the application of voltage is stopped and the gate electrode 104 is returned to the ground potential, a downward residual polarization is generated in the ferroelectric film 103 as shown in FIG. 9B. When the remanent polarization is upward (in the state of data “0”), the ferroelectric film 103 and the silicon oxide are oxidized by an electric field generated by the negative electrode induced at the lower end of the ferroelectric film 103 and the positive electrode induced at the upper end. Although the energy bands of the film 102 and the channel region 107 are bent, holes that are majority carriers are accumulated in a region near the interface of the channel region 107 with the silicon oxide film 102, so that a depletion layer is not formed and the channel The potential of the region 107 is substantially equal to the ground potential.

  As described above, since the potential of the region near the interface of the channel region 107 differs depending on the direction of remanent polarization, if a potential difference is applied between the source region 105 and the drain region 106 which are N-type semiconductor regions, the remanent polarization direction Depending on the current value of the current flowing through, the values differ. That is, in the data “1” state in which the potential of the channel region 107 is lower than the ground potential, an inversion layer is formed in the channel region 107, so that the source-drain state is in a low resistance state (ON state). There is a large current. On the other hand, in the state of data “0” in which the potential of the channel region 107 is the ground potential, since no inversion layer is formed in the channel region, the source and drain are in a high resistance state (OFF state), and almost no current flows. Not flowing. By measuring the current value between the source and the drain in this way, it is possible to know whether the ferroelectric FET is in the data “1” state or the data “0” state depending on the magnitude of the current value. it can.

  As described above, in reading the data state of one ferroelectric FET, basically, it is not necessary to apply a bias to the gate electrode 104 only by providing a potential difference between the source and the drain. That is, the ON state of the ferroelectric FET corresponds to the depletion state of the MOS transistor.

  However, the conventional ferroelectric FET has the following problems.

  FIG. 10 is a characteristic diagram showing the relationship between the voltage Vg applied to the gate electrode 104 of the ferroelectric FET and the source-drain current Ids investigated by the inventors of the present invention. As shown in the figure, when data is read with the voltage applied to the gate electrode 104 set to 0, the current difference ΔI1 between the data “1” state and the data “0” state is small. This is presumably because only a weak inversion layer is formed in the channel region 107 when no voltage is applied to the gate electrode 104 as shown in FIG. As a result, when the polarization state of the ferroelectric film 103 changes with time, it may be difficult to reliably read out the data “1” state and the data “0” state.

  Further, as a problem different from the above, even if data “1” or data “0” is retained, if they are stored for a long period of time, the hysteresis curve is biased in the direction of polarization corresponding to the retained data. The phenomenon of imprinting sometimes appeared. This is because, in the ferroelectric film 103 that has been in one polarization state for a long period of time, the coercive voltage for inverting the polarization corresponding to the stored data is reduced and the polarization state is likely to occur. This is because the coercive voltage for reversing the reverse polarity polarization increases and the reverse polarity polarization hardly occurs. As a result of this imprint phenomenon, the remanent polarization value of the ferroelectric film 103 of the ferroelectric FET that has been retained for a long period of time is different from the initial remanent polarization value. Then, there is a possibility that the signal level (read current value) of the data read out after that is different from the initial signal level (read current value).

  An object of the present invention is to provide a method for manufacturing a semiconductor memory device capable of maintaining high read accuracy while having a structure in which the potential of the channel region of a field effect transistor is changed using the hysteresis characteristics of a ferroelectric thin film. It is to provide.

  A method of manufacturing a semiconductor memory device of the present invention includes a ferroelectric film and a gate electrode provided on a semiconductor substrate, and a source region and a drain region provided on both sides of the gate electrode in the semiconductor substrate. The ferroelectric film has a first polarization generated in the ferroelectric film according to a positive voltage from the gate electrode to the semiconductor substrate, and a negative voltage from the gate electrode to the semiconductor substrate. A step (a) of forming a memory cell including a field effect transistor configured to generate a second polarization generated in the ferroelectric film, and applied to the ferroelectric film for reading data; (B) after applying a voltage having the same polarity as the voltage and releasing the voltage to leave the first polarization in the ferroelectric film; and heating the ferroelectric film for a certain period of time. By the above A step of making the hysteresis characteristics of the ferroelectric film asymmetric by shifting the hysteresis characteristics of the dielectric film in a direction in which the coercive voltage necessary to invert the first polarization to the second polarization is increased; (C).

  By this method, since the polarization state in the ferroelectric film is imprinted in advance on the first logic value side, the data of the first logic value and the data of the second logic value are distinguished at the time of data reading. Easy to do.

  After the step (b), the method may further include a step of erasing the first polarization remaining in the ferroelectric film.

  According to the present invention, there is provided a method for manufacturing a semiconductor memory device capable of maintaining high read accuracy while having a structure in which the potential of the channel region of a field effect transistor is changed using the hysteresis characteristics of a ferroelectric thin film. Can be provided.

(First embodiment)
-Structure of ferroelectric FET-
FIG. 1 is a cross-sectional view of a ferroelectric FET having an MFIS structure according to a first embodiment of the present invention. As shown in the figure, the ferroelectric FET includes a silicon oxide film 12 provided on a silicon substrate 11, and zircon-lead titanate (PZT) or bismuth tantalate provided on the silicon oxide film 12. A ferroelectric film 13 made of a metal oxide such as strontium (SBT), a gate electrode 14 made of a conductive material such as Pt provided on the ferroelectric film 13, and a gate electrode 14 in the silicon substrate 11 A source region 15 and a drain region 16 are provided on both sides. A region of the silicon substrate 11 located below the silicon oxide film 12 is a channel region 17.

  In the structure shown in FIG. 1, the ferroelectric film 13 has an upward direction (a state in which a dipole moment is generated with the upper side being a positive electrode) or a downward direction depending on the polarity of the voltage applied between the gate electrode and the silicon substrate. It has a hysteresis characteristic that polarization occurs (a state in which a dipole moment having a positive electrode on the lower side is generated) and polarization remains even after the application of voltage is stopped. In a state where no voltage is applied to the gate electrode 14, the channel region 17 of the ferroelectric FET has two potential depths different from each other corresponding to the two different types of residual polarization states. Is in a state. On the other hand, the resistance value between the source and the drain of the ferroelectric FET changes according to the potential depth of the channel region 17. Therefore, the resistance between the source and the drain is determined to be either a high value or a low value according to the two types of remanent polarization states of the ferroelectric film 13, and the resistance between the source and the drain is different between two types. The state indicating one of the values is held (stored) as long as the residual polarization state of the ferroelectric film 13 is held. Therefore, a nonvolatile memory device can be configured using a ferroelectric FET. For example, data “1” (first logic value) indicates a state in which downward residual polarization occurs in the ferroelectric film 13, and data “0” indicates a state in which upward residual polarization occurs in the ferroelectric film 13. As (second logic value), a ferroelectric FET can be used as a memory cell.

  However, as already described in the related art, in the method of reading data without applying a bias to the gate electrode 14, the difference ΔI1 in the read current between the data “1” state and the data “0” state. Is small (see FIG. 10). Therefore, in the present embodiment, it is assumed that a bias is applied to the gate electrode 14 at the time of reading.

-Gate bias setting method-
FIG. 2 is a diagram for explaining a method of setting the gate bias (voltage applied to the gate electrode 13) ΔVg at the time of reading in the present embodiment. In the gate bias dependence characteristics of the source-drain current Ids of the ferroelectric FET as already described with reference to FIG. 10, the difference between the read currents in the data “1” state and the data “0” state is almost the maximum value. The value of the gate bias Vg that becomes ΔI2 is assumed to be ΔVg. Here, in the present embodiment, the gate voltage Vg at the time of reading is set to a position shifted from 0 by ΔVg. In other words, an offset voltage of ΔVg is applied to the gate electrode 14 in order to increase the S / N ratio of the read signal.

−Disturbance phenomenon−
However, according to this method, the offset voltage ΔVg is always applied to the gate electrode 14 of the ferroelectric FET during the read operation. For example, when a positive offset voltage ΔVg is applied to the gate electrode, if the remanent polarization is downward (data “1” state), the remanent polarization direction matches the polarization direction induced by the electric field of the gate bias. The polarization state is not affected by the gate bias. However, when the remanent polarization is upward (in the state of data “0”), the remanent polarization direction and the polarization direction induced by the electric field of the gate bias are reversed, and therefore by applying the offset voltage ΔVg to the gate electrode. The residual polarization in the ferroelectric film is slightly weakened. Further, when the read operation is repeated, the remanent polarization in the ferroelectric film gradually weakens every time the offset voltage ΔVg is applied to the gate electrode. Finally, as shown in FIG. The remanent polarization in the body membrane becomes almost zero. A phenomenon in which data is lost by repeatedly applying a voltage that applies an electric field in the direction of weakening remanent polarization to the gate voltage is called a disturb phenomenon.

  FIG. 11 is a hysteresis characteristic diagram for explaining the disturb phenomenon. In FIG. 11, the vertical axis represents the intensity of polarization expressed with the downward polarization as the positive direction, and the horizontal axis represents the voltage (gate bias) applied to the gate electrode. As shown in the figure, in the initial state, the downward polarization state (data “1” state) is at point A in the hysteresis curve, and the upward polarization state (data “0” state) is at point B. . When a positive gate bias is applied to the gate electrode 114 of the ferroelectric film whose polarization state is at the point A or B, the following behavior is exhibited. When the polarization state is at the point A, even if the gate bias is smaller than the coercive voltage, the polarization state moves from the point A to the point A ′ along the hysteresis curve. When returning, the polarization state at the point A ′ returns to the point A again. On the other hand, when the polarization state is at point B, even if the gate bias is smaller than the coercive voltage, the polarization state moves from point B to point B 'along the hysteresis curve. Even if it returns to zero, the polarization state at point B ′ no longer returns to point B, but moves to point B ″. In other words, upward polarization is applied by applying an offset voltage ΔVg (gate bias) to the gate electrode. Therefore, when the reading operation is repeated, the upward polarization gradually decreases as shown by the dotted line in FIG.

  When the polarization disappears due to the disturb phenomenon, the potential of the channel region of the ferroelectric FET that retains the data “0” in the conventional ferroelectric FET is as shown in FIG. In addition, since it changes so as to approach the potential of the data “1”, the source-drain current Ids corresponding to the state of the data “0” gradually changes from its initial value, which is an undesirable phenomenon in the design of the readout circuit. Presents.

-Reading method-
On the other hand, in the present embodiment, when reading the ferroelectric FET, the offset voltage ΔVg in the direction of applying downward polarization to the ferroelectric film 13 is applied to the gate electrode 14, so when reading the data The potential in the vicinity of the surface of the channel region 17 is different from that of the conventional ferroelectric FET as described below.

  FIGS. 3A, 3B, and 3C show the gate electrode 14, the ferroelectric film 13, and the silicon oxide film when the remanent polarization in the ferroelectric film 13 is downward, upward, and substantially zero, respectively. 12 is an energy band diagram showing an energy band state at the time of reading that occurs in a cross section passing through 12 and a channel region 17. FIG. 3A to 3C, the silicon substrate 11 is a P-type substrate, and the source region 15 and the drain region 16 are N-type semiconductor regions. The arrows in FIGS. 3A and 3B indicate the direction of remanent polarization of the ferroelectric.

  Also in the present embodiment, the procedure for causing polarization in the ferroelectric film 13 is the same as in the prior art, so that the gate electrode 14, the ferroelectric film 13, and the silicon oxide film are not applied to the gate electrode 14 in a state where no voltage is applied. 12 and the energy band state in the cross section passing through the channel region 17 are as shown in FIGS.

  On the other hand, when reading data, an offset voltage ΔVg is applied to the gate electrode 14 with respect to the silicon substrate 11 in the ferroelectric FET having the structure shown in FIG. At this time, the ferroelectric film 13 and the silicon oxide film 12 between the gate electrode 14 and the silicon substrate 11 are distributed at a certain ratio ΔVg between the gate electrode 14 and the silicon substrate 11.

  As shown in FIG. 3A, when the remanent polarization is downward (data “1” state), the polarization is further enhanced by the offset voltage ΔVg applied to the gate electrode 14. The energy band of the ferroelectric film 13, the silicon oxide film 12, and the channel region 17 is bent as shown in FIG. 3A by the positive electrode induced at the lower end. Further, the region in the vicinity of the interface with the silicon oxide film 12 in the channel region 17 is strongly negatively ionized and the depletion layer extends to the substrate deep, and the potential in the region in the vicinity of the interface with the silicon oxide film 12 in the channel region 17 is greater than the ground potential. Also lower. That is, a strong inversion layer is formed, and the ferroelectric FET exhibits an on-state current value.

  On the other hand, as shown in FIG. 3B, when the remanent polarization is upward (data “0” state), the polarization is weakened by the offset voltage ΔVg applied to the gate electrode 14. The induced negative electrode strength is reduced. Then, the energy bands of the ferroelectric film 13, the silicon oxide film 12, and the channel region 17 are bent as shown in FIG. 3B, and the potential of the region near the interface between the channel region 17 and the silicon oxide film 12 is low. Therefore, a weak inversion layer is formed in the channel region 17.

  Further, as shown in FIG. 3C, when the residual polarization disappears due to the disturbance, the energy band of the ferroelectric film 13, the silicon oxide film 12, and the channel region 17 is caused by the offset voltage ΔVg applied to the gate electrode. Is bent as shown in FIG. At this time, since the potential of the conduction band edge in the region near the interface between the channel region 17 and the surface of the silicon oxide film 12 is bent downward, a slightly stronger inversion layer is formed in the channel region 17 than shown in FIG. Is done.

  Thus, the potential of the region near the surface of the channel region 17 differs depending on the direction of remanent polarization. Therefore, if a potential difference is applied between the source region 15 and the drain region 16 that are N-type semiconductor regions, the remanent polarization direction Depending on the current value of the current flowing through, the values differ.

  That is, if the state shown in FIG. 3A is data “1”, a strong inversion layer is formed in this state, so that the source-drain state is in a low resistance state, and at the point y in FIG. A large current flows. On the other hand, if the state shown in FIG. 3B is data “0”, a small current flows at a point w in FIG. 2 because the source and drain are in a relatively high resistance state in this state. By measuring the current value between the source and the drain in this way, it is possible to know whether the ferroelectric FET is in the data “1” state or the data “0” state depending on the magnitude of the current value. it can.

  Further, in the state shown in FIG. 3C, the polarization in the ferroelectric film 13 becomes almost 0, and an inversion layer that is slightly stronger than that shown in FIG. 3B is formed. An intermediate current at v flows. Since this current value is sufficiently smaller than the current value at the point y, it is relatively easy to distinguish and detect the current values at the points w and v.

-Data logical value setting method-
Therefore, in the nonvolatile memory device using the ferroelectric FET of the present embodiment, reading is performed by applying an offset voltage (gate bias) ΔVg to the gate electrode 14, and the change in hysteresis characteristics due to disturbance shown in FIG. In FIG. 3B, the polarization becomes 0 by disturbance from the current value (current value at the point w in FIG. 2) in the upward polarization state (state shown in FIG. 3B) (shown in FIG. 3C). Range) up to the current value (current value at point v in FIG. 2) is determined as data “0”. Specifically, a state indicating a current value equal to or lower than the current value at the point v in FIG. 2 may be determined as data “0”. The current value (current value at the point y in FIG. 2) when the polarization is in the downward direction (the state shown in FIG. 3A) is “1” as in the conventional case.

  Table 1 shows the correspondence between the logic state and the polarization of the conventional ferroelectric FET and the ferroelectric FET according to the present embodiment by comparing the resistance between the source and the drain.

表１の本実施形態(１)における強誘電体ＦＥＴと従来の強誘電体ＦＥＴとの相違点は、ディスターブにより分極が消失した状態において、読み出しを行なう際に、従来の強誘電体ＦＥＴではチャネル領域１０７に弱い反転層しか形成されない（図９（ｃ）参照）のに対し、本発明の強誘電体ＦＥＴでは、ゲート電極１４に印加されるオフセット電圧ΔＶｇによって分極が生じるので、チャネル領域１７に比較的強い反転層が形成される（図３（ｃ）参照）という点である。その結果、ディスターブにより分極が消失した状態において、従来の強誘電体ＦＥＴにおいては、図２の点ｚから点ｕに変化したときの電流値と、図２の点ｘにおける電流値とを区別して検知しなければならないことになる。しかし、点ｕと点ｘとにおける電流値を区別して検知することは、実際上困難であり、読み出したデータの論理状態が不明であった。それに対し、本実施形態においては、図２の点ｙにおける電流値と点ｗから点ｖまでの範囲の電流値とを区別して検知すればよいので、読み出したデータが２つの論理状態のどちらかに明確に対応付けられる。すなわち、本実施形態によれば、ディスターブによって上向きの分極が消失した状態でも確実な論理状態の判定を行うことができる。

The difference between the ferroelectric FET in the present embodiment (1) in Table 1 and the conventional ferroelectric FET is that when reading is performed in a state where the polarization has been lost due to disturbance, the channel is not obtained in the conventional ferroelectric FET. Whereas only a weak inversion layer is formed in the region 107 (see FIG. 9C), in the ferroelectric FET of the present invention, polarization is generated by the offset voltage ΔVg applied to the gate electrode 14, and therefore the channel region 17 A relatively strong inversion layer is formed (see FIG. 3C). As a result, in the state in which the polarization has disappeared due to the disturbance, in the conventional ferroelectric FET, the current value when changing from the point z in FIG. 2 to the point u is distinguished from the current value at the point x in FIG. It must be detected. However, it is actually difficult to distinguish and detect the current values at points u and x, and the logical state of the read data is unknown. On the other hand, in the present embodiment, the current value at the point y in FIG. 2 and the current value in the range from the point w to the point v may be detected separately, so that the read data is one of the two logical states. Clearly associated with That is, according to the present embodiment, it is possible to reliably determine the logical state even when the upward polarization disappears due to the disturbance.

  In the present embodiment, in the ferroelectric FET as a memory cell, the state in which the downward residual polarization is generated in the ferroelectric film 13 is set as data “1”, and the upward residual polarization is generated in the ferroelectric film 13. The state where the residual polarization is generated or the state where the remanent polarization is almost zero is set as the data “0”. The data “1” may be used.

  In addition, since it is arbitrary which state is set to data “0” or data “1”, a downward remanent polarization is generated in the ferroelectric film 13 in the ferroelectric FET which is a memory cell in the present embodiment. Needless to say, the data “0” may be used as the data “0”, and the state in which the upward remanent polarization is generated in the ferroelectric film 13 or the state in which the remanent polarization is substantially 0 may be used as the data “1”.

  The silicon oxide film 12 is not necessarily required.

  Further, as shown in Table 1 (the present embodiment (2)), by adjusting the built-in potential as appropriate, even if a bias voltage is applied to the gate electrode 14 in a state where the remanent polarization is upward or disappears, the ferroelectric substance It is also possible to adjust so that the source-drain current Ids of the FET does not flow (off state) and the current flows (on state) only when the remanent polarization is downward. Also in this case, unlike the conventional method, at the time of data reading, when the polarization is in a downward state (data “1”), a large current Ids can be secured, so that the polarization is zero or upward ( The distinction from the current (zero) when the data is “0” is not ambiguous.

(Second Embodiment)
FIG. 4 is a cross-sectional view of a memory cell of a semiconductor memory device according to the second embodiment of the present invention. The memory cell of the semiconductor memory device in this embodiment is considered to be a ferroelectric FET having a so-called MFMIS structure.

  The ferroelectric FET includes a silicon oxide film 12 (gate insulating film) provided on a P-type silicon substrate 11 and a first intermediate made of a conductive material such as polysilicon provided on the silicon oxide film 12. A gate electrode 18 and an N-type source region 15 and a drain region 16 provided on both sides of the first intermediate gate electrode 18 in the silicon substrate 11 are provided. A region of the silicon substrate 11 located below the silicon oxide film 12 is a channel region 17. The second intermediate gate electrode 21 made of Pt or the like, and the thickness made of a metal oxide such as zircon-lead titanate (PZT) or bismuth strontium tantalate (SBT) provided on the second intermediate gate electrode 21 Includes a ferroelectric film 22 having a thickness of about 200 nm, and a control gate electrode 23 made of a conductive material such as Pt provided so as to face the second intermediate gate electrode 21 with the ferroelectric film 22 interposed therebetween. The control gate electrode 23 is connected to the first wiring 25, and the first intermediate gate electrode 18 and the second intermediate gate electrode 21 are connected to a common second wiring 26.

  In this structure, when the first intermediate gate electrode 18 and the second intermediate gate electrode 21 are considered as an integral body, the intermediate gate is interposed between the ferroelectric 13 and the silicon oxide film 12 in the ferroelectric FET shown in FIG. It can be regarded as an electrode provided with the first intermediate gate electrode 18 and the second intermediate gate electrode 21, that is, a MFMISFET. However, the first intermediate gate electrode 18 and the second intermediate gate electrode 21 may be integrated, or the first intermediate gate electrode 18 and the second intermediate gate electrode 21 are individually provided as shown in FIG. It may be provided.

  Here, when the material of the ferroelectric film 22 is SBT and the film thickness is about 200 nm, the coercive voltage of the ferroelectric film 22 is about 1V.

  Compared with the ferroelectric FET of the first embodiment, the structural features of the ferroelectric FET of this embodiment are necessary for changing the polarization state of the ferroelectric film 22 in this embodiment. A voltage that can be directly applied by the first wiring 25 connected to the control gate electrode 23 and the second wiring 26 connected to the second intermediate gate electrode 21, and the first intermediate The potential is that the potential of the gate electrode 18 can be determined by the second wiring 26 before the read operation.

  In addition, compared with the ferroelectric FET that is the ferroelectric FET of the first embodiment, the operational characteristics of the ferroelectric FET of the present embodiment are that in the present embodiment, in the data writing, When writing so as to generate downward residual polarization (data “1”) in the dielectric film 22 and when writing so as to generate upward residual polarization (data “0”) in the ferroelectric film 22, The absolute values of the voltages applied to the ferroelectric films 22 are different.

  In this embodiment, although the illustration of the energy band structure in the ferroelectric FET is omitted, it is assumed that the first intermediate gate electrode 18 and the second intermediate gate electrode 21 are integrated in the structure shown in FIG. In the energy band diagrams shown in FIGS. 3A to 3C, since the conductor member is merely interposed between the ferroelectric film 13 and the silicon oxide film 12, the data read operation is performed in the first embodiment. It can be considered in the same way as the form. However, when the polarization of the ferroelectric film 22 is caused, a voltage is applied between the control gate electrode 23 and the second intermediate gate electrode 21, which is different from the first embodiment.

  FIG. 5 is a hysteresis characteristic diagram for explaining the data writing operation in the present embodiment on the voltage-polarization coordinates. In FIG. 5, the horizontal axis represents the voltage applied between the control gate 23 and the second intermediate gate electrode 21, and the vertical axis represents the polarization generated in the ferroelectric film 22 with the downward direction being positive. In the following description, the potential of the silicon substrate 11 is always the ground potential.

  As shown in FIG. 5, since the polarization of the ferroelectric film 22 before data is written is almost zero, the polarization state is in the vicinity of the origin O. In order to write data “1” in the ferroelectric film 22, for example, the second wiring 26 connected to the second intermediate gate electrode 21 is set to the ground potential, and the first wiring 25 connected to the control gate electrode 23 is used. When a voltage of 3 V is applied to the electrode, the polarization state moves along the solid line from the origin O to the point a ″. After that, when the first wiring 25 connected to the control gate electrode 23 is set to the ground potential, the polarization state is From the point a ″ to the point a, the ferroelectric film 22 holds about 10 μC / cm 2 of charge (residual polarization) as data “1” in a state of zero voltage.

  Subsequently, in order to rewrite data “1” to data “0”, a voltage −3 V required to invert the polarization state to the saturation state is applied to the first wiring 25 connected to the control gate electrode 23. Instead, a voltage of about -1V is applied. That is, in the present invention, the data “0” is defined from the negative saturation state (about −10 μC / cm 2) to almost 0 (about 0 μC / cm 2) as the charge due to the polarization. Can be set to approximately 0 μC / cm 2. Therefore, when a voltage of about −1 V is applied to the first wiring 25 connected to the control gate electrode 23, the polarization state moves from the point a to the point b ′ as shown in the locus shown in FIG. This operation can also be realized by setting the first wiring 25 connected to the control gate electrode 23 to the ground potential and applying a voltage of 1 V to the second wiring 26 connected to the second intermediate gate electrode 21. After that, when the first wiring 25 connected to the control gate electrode 23 is set to the ground potential, the polarization state moves from the point b ′ to the point b, and the ferroelectric film 22 has about 0 μC / The charge of cm2 is held as data “0”.

  That is, in the present embodiment, the polarization (residual polarization) generated in the ferroelectric film 22 when the negative voltage is released after the negative voltage is applied to the ferroelectric film 22 in which the positive remanent polarization is generated is almost the same. When it becomes 0, a voltage substantially equal to the negative voltage (coercive voltage) is applied to rewrite data from “1” to “0”.

  However, even if a weak negative voltage that has a larger absolute value than the coercive voltage (in this embodiment, -1 V) and does not reach the saturation state is applied between the second intermediate gate electrode 21 and the control gate electrode 23, The effect of improving the reading accuracy described later can be exhibited to some extent.

  Further, even when data “0” is written to the ferroelectric film 22 from a state in which no data is written to the ferroelectric film 22, the coercive voltage (about −1 V) shown in FIG. 5 is applied to the ferroelectric film 22. It is preferable to apply.

  After the data is written, the second wiring 26 connected to the second intermediate gate electrode 21 is set to the ground potential, and the potential of the first intermediate gate electrode 18 connected thereto is determined. Subsequently, the second wiring 26 connected to the second intermediate gate electrode 21 is electrically cut off from a peripheral circuit (not shown) using a switching transistor or the like.

  Alternatively, immediately before reading out data, first, the second wiring 26 connected to the second intermediate gate electrode 21 is set to the ground potential, and the potential of the first intermediate gate electrode 18 connected thereto is determined. This is for removing unnecessary charges accumulated in the first intermediate gate electrode 18 as a leakage current or the like in the writing and reading operations executed until this reading or in a stationary state. Subsequently, the second wiring 26 connected to the second intermediate gate electrode 21 is electrically cut off from a peripheral circuit (not shown) using a switching transistor or the like. Thereafter, in order to read data, the read voltage VR corresponding to the offset voltage ΔVg described in the first embodiment is applied to the first wiring 25 connected to the control gate electrode 23. This read voltage VR is divided into a voltage applied to the ferroelectric film 22 and a voltage applied to the silicon oxide film 12. At this time, when the polarization of the ferroelectric film 22 is downward (data “1”), the direction of polarization caused by the voltage applied to the ferroelectric film 22 and the direction of polarization (charge) retained Therefore, as described in the first embodiment, even if the read voltage VR is removed, the direction and magnitude of the polarization do not change.

  On the other hand, when the polarization of the ferroelectric film 22 is upward (data “0”), according to the writing method of the first embodiment, the direction of polarization generated by the voltage applied to the ferroelectric film 22 and the retention Since the direction of polarization (charge) is reversed, the ferroelectric film 22 is disturbed by the application of the read voltage VR. As a result, the polarization disappears due to the disturbance, and the source-drain current Ids with respect to the data “0” changes accordingly.

  However, in the writing method of this embodiment, a state where the polarization is about 0 μC / cm 2 is held as data “0” from the beginning. Furthermore, in this embodiment, the read voltage VR applied to the first wiring 25 connected to the control gate electrode 23 is set so that the voltage applied to the ferroelectric film 22 does not exceed the coercive voltage. Therefore, the polarization does not disappear, and the state of the data “0” is not reversed to the data “1”. Therefore, even when data “0” is repeatedly read, the source-drain current Ids does not change. Specifically, the ratio of the voltage applied to the ferroelectric film 22 and the voltage applied to the silicon oxide film 12 is constituted by the second intermediate gate electrode 21, the ferroelectric film 22 and the control gate electrode 23. It is determined by the ratio of the capacitance of the capacitor and the capacitance of the capacitor formed by the first intermediate gate electrode 18, the silicon oxide film 12 and the silicon substrate 11. By adjusting the capacitance ratio and the read voltage VR, the voltage applied to the ferroelectric film 22 at the time of data reading can be made equal to or lower than the coercive voltage of polarization in the ferroelectric film 22.

  In the data storage state, the first wiring 25 connected to the control gate electrode 23 and the second wiring 26 connected to the second intermediate gate electrode 21 in the last stage of the data writing operation prior to this. Are grounded together, thereby making the bias applied to the ferroelectric film 22 zero. As a result, the polarization does not change under the influence of the bias during data retention.

  Therefore, according to the present invention, data “1” is made to correspond to the state in which the remanent polarization is downward, and data “0” is made to correspond to the range in which the remanent polarization does not reach the upward saturated state. Since storage and reading are performed, a change in read current caused by disturbance when data is “0” can be reduced, and read accuracy can be improved.

  In particular, as in the present embodiment, by making data “0” correspond to a state in which the polarization is substantially zero, the effect of improving the reading accuracy can be remarkably exhibited.

  In the present embodiment, writing and rewriting are performed so that the polarization is substantially zero when the data is “0”. However, the present invention is not limited to such an embodiment, and the data “1” is used. It is also possible to set the polarization to be substantially zero when

  In the present embodiment, the present invention is applied to the ferroelectric FET having the MFMIS structure. However, even if the present invention is applied to the ferroelectric FET having the MFIS structure shown in FIG. it can.

  In this embodiment, the capacitance value of the paraelectric capacitor constituted by the first intermediate gate electrode 18, the silicon oxide film 12 and the silicon substrate 11 does not change, but the control gate electrode 23, the ferroelectric film 22 and The capacitance value of the ferroelectric capacitor constituted by the second intermediate gate electrode 21 changes between the position of the point a and the position of the point b shown in FIG. That is, the capacitance value of the capacitor corresponds to the slope on the hysteresis characteristic curve. The voltage applied between the control gate electrode 23 and the silicon substrate 11 is distributed to the paraelectric capacitor and the ferroelectric capacitor. Therefore, the larger the capacitance value of the ferroelectric capacitor, the smaller the distribution ratio of the voltage applied between the control gate electrode 23 and the silicon substrate 11 to the ferroelectric capacitor. Thus, since the distribution ratio of the voltage value applied to the control gate electrode 23 changes in accordance with the change in the capacitance value of the ferroelectric capacitor, the current value changes and the data can be more easily distinguished. .

(Third embodiment)
Next, a third embodiment relating to a configuration for preventing imprint will be described.

  According to the second embodiment, it is possible to suppress a change in bias at the time of reading due to disturbance. However, as described in the related art, the source-drain read after being held for a long time by imprinting It is difficult to prevent the level of the intercurrent current Ids from being different from the initial level.

  Therefore, in this embodiment, the ferroelectric film 22 is once written so that the polarization state of the ferroelectric film 22 is a point a (data “1”) shown in FIG. Trigger prints. Therefore, the feature of the semiconductor memory device of the present embodiment over the conventional method of manufacturing a semiconductor memory device is that a process of inducing imprinting after writing data “1” is added in the normal manufacturing process of the semiconductor memory device. There is in being.

  FIG. 6 is a flowchart showing an example of the manufacturing process of the ferroelectric FET (see FIG. 4) of the semiconductor memory device in the present embodiment.

  First, in step ST11, a wafer diffusion process is performed. In this step, the silicon oxide film 12 and the first intermediate gate electrode 18 are formed, the source region 15 and the drain region 16 are formed by ion implantation of impurities into the silicon substrate 11, and the second on the first intermediate gate electrode 18. An intermediate gate electrode 21, a ferroelectric film 22, and a control gate electrode 23 are formed, and wirings 25 and 26 are formed on an interlayer insulating film (not shown).

  Next, in step ST12, the electrical function of the ferroelectric film of the ferroelectric FET is inspected. In this step, it is inspected whether various characteristics such as voltage-polarization characteristics of the ferroelectric film 22 are appropriate.

  Next, in step ST13, data “1” is written to all the ferroelectric FETs. That is, downward polarization is caused in the ferroelectric film 22. After that, by impressing the ferroelectric film 22 of the ferroelectric FET, imprinting is induced in the direction of data “1”. At this time, for example, when heating is performed at 150 ° C. for about 10 hours, the hysteresis curve of the ferroelectric film 22 is shifted in the direction of the initial data “1”, that is, in the direction in which downward polarization increases (that is, in This excursion almost stops from a certain point in time. That is, the progress of the imprint beyond that is extremely small.

  FIG. 7 is a hysteresis characteristic diagram showing a change in the hysteresis characteristic of the ferroelectric film 22 in step ST13. In FIG. 7, the horizontal axis represents the voltage applied between the control gate electrode 23 and the second intermediate gate electrode 21, and the vertical axis represents the polarization generated in the ferroelectric film 22 with the downward direction being positive. As shown in the figure, the initial hysteresis characteristic of the ferroelectric film 22 is a curve represented by a one-dot chain line in the figure, but when imprinting is induced, the hysteresis characteristic of the ferroelectric film 22 is The characteristic shifts to the curve shown by the broken line in the middle. When data “1” is held in the ferroelectric film 22, the hysteresis curve after imprinting is induced is that the coercive voltage (the voltage value at the point b ′) is the resistance in the initial hysteresis characteristic. It changes so as to deviate from the voltage by about −0.2 V in the voltage axis direction. Even after imprinting is induced in the ferroelectric film 22, the slope of the curve from point a to point a "and the slope of the curve from point b to point a" (that is, data "1" is written). Since there is a sufficient difference between the capacitor capacity of the ferroelectric film 22 and the capacitor capacity of the ferroelectric film 22 in which data “0” is written, the read voltage VR is connected to the control gate electrode. When applied to the first wiring 25, the voltage induced in the first intermediate gate electrode 18 is sufficiently different depending on the data “1” and the data “0”. That is, it is possible to maintain good data reading accuracy.

  Next, after the ferroelectric film 22 is baked in step ST14, the data “1” of all the ferroelectric FETs is erased in step ST15. In this example, data “0” is written in all the ferroelectric FETs. At this time, in order to rewrite the data “1” held in the ferroelectric film 22 in which the hysteresis curve is deviated by induction of imprinting, to the data “0”, as shown in FIG. A negative voltage having an absolute value larger than −1 V may be applied to the ferroelectric film 22 so as to move from to b ′. This operation can also be performed by setting the first wiring 25 connected to the control gate electrode 23 to the ground potential and applying a voltage of 1 V or more to the second wiring 26 connected to the second intermediate gate electrode 21. Further, the same effect can be obtained by heating the ferroelectric film 22 of the ferroelectric FET above the phase transition temperature of the ferroelectric.

  However, it is also possible to use the ferroelectric FET as a memory cell in a state where downward polarization exists in the ferroelectric film 22. In this case, the state in which downward polarization remains in the ferroelectric film 22 can be set as data “0”, and the state in which the polarization hardly exists in the ferroelectric film 22 can be set as data “1”.

  As described above, if imprinting is induced in advance in a state where the data “1” is held, the level of the read signal of the data “1” does not change from the initial state due to the imprinting. For data “0”, in the present embodiment, since the state of almost zero polarization is associated with this, imprint is unlikely to occur. Therefore, according to the present embodiment, since the imprint hardly progresses in any state of data “1” and data “0”, the level of the read signal does not change from the initial value. Further, the effect of the ferroelectric FET of the present embodiment is that the ferroelectric FET of the present embodiment is arranged in a matrix, and the control gate electrode 23 of the ferroelectric FET is formed on the first wiring 25 serving as a word line. This is also obtained when a memory cell array is formed in which the drain regions 16 of the ferroelectric FETs are connected to the bit lines.

(Other embodiments)
FIG. 12 is a cross-sectional view of a ferroelectric FET having a so-called MFMIS structure. As shown in the figure, the ferroelectric FET includes a silicon oxide film 12 provided on the silicon substrate 11, and an intermediate gate electrode 31 made of a conductive material such as Pt provided on the silicon oxide film 12. A ferroelectric film 32 made of a metal oxide such as zircon-lead titanate (PZT) or bismuth strontium tantalate (SBT), and provided on the ferroelectric film 32. The control gate electrode 33 made of a conductive material such as Pt, and the source region 15 and the drain region 16 provided on both sides of the intermediate gate electrode 31 in the silicon substrate 11 are provided. A region of the silicon substrate 11 located below the silicon oxide film 12 is a channel region 17. The control gate electrode 33 is connected to the first wiring 35, and the intermediate gate electrode 31 is connected to the second wiring 36.

  Using such a ferroelectric FET as a memory cell of a semiconductor memory device, data can be written, rewritten, and read as in the second embodiment, and the same effects as in the second embodiment can be achieved. can do. In addition, the ferroelectric FET shown in FIG. 12 is used as a memory cell of the semiconductor memory device, and processing for causing imprinting to downward polarization in the ferroelectric film 32 is performed as in the third embodiment. be able to.

  A method of manufacturing a semiconductor memory device according to the present invention is a semiconductor capable of maintaining high read accuracy while having a structure in which the potential of the channel region of a field effect transistor is changed using the hysteresis characteristics of a ferroelectric thin film. Useful as a method for manufacturing a semiconductor memory device having a structure in which the potential of the channel region of a field effect transistor is changed using the hysteresis characteristics of a ferroelectric thin film It is.

1 is a cross-sectional view of a ferroelectric FET having an MFIS structure according to a first embodiment of the present invention. It is a figure for demonstrating the setting method of the gate bias at the time of read of 1st Embodiment. (A), (b), and (c) are energy bands at the time of reading when the remanent polarization in the ferroelectric film of the ferroelectric FET of the first embodiment is downward, upward, and substantially zero, respectively. FIG. FIG. 6 is a cross-sectional view of a memory cell of a semiconductor memory device in a second embodiment of the present invention. FIG. 11 is a hysteresis characteristic diagram for explaining a data writing operation on the voltage-polarization coordinates in the second embodiment. It is a flowchart figure which shows an example of the manufacturing process of ferroelectric FET of the semiconductor memory device in the 3rd Embodiment of this invention. It is a hysteresis characteristic figure which shows the change of the hysteresis characteristic of the ferroelectric film 22 in the heat treatment process of 3rd Embodiment. It is sectional drawing of the conventional MFISFET type ferroelectric FET. (A), (b), and (c) are energy band diagrams when the remanent polarization in the ferroelectric film of the conventional ferroelectric FET is downward, upward, and substantially zero, respectively. It is a characteristic view showing the relationship between the voltage applied to the gate electrode of the ferroelectric FET and the current between the source and drain. It is a hysteresis characteristic diagram for explaining this disturb phenomenon. It is sectional drawing which shows the example which applied 2nd Embodiment to the ferroelectric FET which has MFMIS structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Silicon substrate 12 Silicon oxide film 13 Ferroelectric film 14 Gate electrode 15 Source region 16 Drain region 17 Channel region 18 First intermediate gate electrode 21 Second intermediate gate electrode 22 Ferroelectric film 23 Control gate electrode 25 First wiring 26 Second wiring

Claims (2)

A ferroelectric film and a gate electrode provided on the semiconductor substrate; and a source region and a drain region provided on both sides of the gate electrode in the semiconductor substrate, wherein the ferroelectric film comprises the gate electrode To the first polarization generated in the ferroelectric film in response to a positive voltage with respect to the semiconductor substrate, and the second polarization generated in the ferroelectric film in response to a negative voltage from the gate electrode to the semiconductor substrate. Forming a memory cell comprising a field effect transistor configured to produce:
(B) applying a voltage having the same polarity as the voltage applied for reading data to the ferroelectric film and then releasing the voltage to leave the first polarization in the ferroelectric film; ,
By heating the ferroelectric film for a certain period of time, the hysteresis characteristics of the ferroelectric film are biased in a direction in which the coercive voltage required to invert the first polarization to the second polarization increases. And a step (c) of making the hysteresis characteristic of the ferroelectric film asymmetric. The method of manufacturing a semiconductor memory device according to claim 1.
A method of manufacturing a semiconductor memory device, further comprising the step of erasing the first polarization remaining in the ferroelectric film after the step (b).

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