JP2001293218A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inexpensively realize an environment capable of further efficiently performing a test on game control operation. SOLUTION: A pattern control board is mounted with a test signal output circuit 120 for externally outputting a test signal from a testing CPU and connectors 121 to 126. The test signal output circuit 120 is mounted with two I/O expanders 120A and 120B. The I/O expanders are output port ICs having plural I/O ports. Thus, even if there are a large number of test signals, the size of the test signal output circuit 120 for outputting the test signals does not become large. The I/O expanders are LSIs, and the size is small. Then, even if the I/O expanders are constituted so that a large number of test signals can be outputted, the base board size does not become large so much, and a cost does not increase so much.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko game machine, a coin game machine, a slot machine, etc., in which a game is played in accordance with a player's operation. A gaming machine in which a game is played in accordance with a game machine.

[0002]

2. Description of the Related Art As an example of a gaming machine, a variable display device having a variable display section whose display state can be changed is provided, and when a display result of the variable display section becomes a predetermined specific display mode, a game is played. Is configured to shift to a jackpot game state that is advantageous to the player. The variable display device includes a plurality of variable display units, and is generally configured to display the display results of the plurality of variable display units at different times. On the variable display section, for example, a plurality of identification information such as symbols are variably displayed. The fact that the display result of the variable display unit is a combination of predetermined specific display modes is usually referred to as “big hit”. In addition, the game value is a right to make the state of the variable prize ball device provided in the game area of the gaming machine advantageous for a player who is easy to win a hit ball, or a right for the player to be in an advantageous state. Or to generate.

[0003] When a big hit occurs, for example, a big winning opening is opened a predetermined number of times, and the state shifts to a big hit game state in which a hit ball is easy to win. Then, in each open period, when a predetermined number (for example, 10) of winning prizes is won, the winning prize opening is closed. The number of opening of the special winning opening is fixed to a predetermined number (for example, 16 rounds). An opening time (for example, 29.5 seconds) is determined for each opening, and if the opening time elapses even if the number of winnings does not reach a predetermined number, the winning opening is closed. Further, if a predetermined condition (for example, winning in a V zone provided in the special winning opening) is not satisfied at the time when the special winning opening is closed, the big hit game is performed even if the predetermined number of times is not reached. The state ends.

[0004] In addition, among the combinations of the display modes of "outside" other than the combination of "big hit", at the stage where a part of the display results of the plurality of variable display portions has not been derived and displayed yet, the display results are already displayed. The state in which the display mode of the variable display unit that is derived and displayed satisfies the display condition that is a combination of the specific display modes is referred to as “reach”. A player plays a game while enjoying how to generate a big hit.

The progress of a game in a game machine is controlled by game control means such as a game control microcomputer. The identification information, the character image, and the background image displayed on the variable display device are controlled by display control means operating according to display control command data from the game control means. The identification information, the character image, and the background image displayed on the variable display device generally include a display control microcomputer and a video display processor (FIG. 1) that generates image data in accordance with instructions from the microcomputer and transfers the image data to the variable display device side. VDP), and the display control microcomputer has a large program capacity.

Therefore, the game control microcomputer of the game control means having a limited program capacity cannot control the identification information and the like displayed on the variable display device, and the display control is different from the microcomputer of the game control means. Microcomputer (display control means). The game control means for controlling the progress of the game transmits a command for display control to the display control means mounted on the symbol control board. Then, the display control means generates image data such as information.

A gaming machine is provided with a game control board on which a game control microcomputer is mounted and a symbol control board on which a microcomputer for display control is mounted. A board on which a computer is mounted may be provided. Hereinafter, the board on which the microcomputer is mounted may be referred to as an electrical component control board, and the microcomputer mounted on the electrical component control board may be referred to as an electrical component control microcomputer. Control means realized by the electric component control microcomputer is called electric component control means.

[0008]

At the stage of developing a gaming machine having a variable display device, it is necessary to confirm how the identification information and the like displayed on the variable display device fluctuate and whether the fluctuation period is as designed. There is a need to. Since the variation pattern of the identification information is enormous, the number of labor and period required for the test are also large. That is, improving the test efficiency of the identification information and the like displayed on the variable display device is a major issue in the game machine development stage and the like. Further, it is desired that not only the identification information displayed on the variable display device but also various game control states be externally output efficiently at low cost.

Accordingly, an object of the present invention is to provide a gaming machine capable of realizing an environment in which a test relating to a game control operation can be performed more efficiently at low cost.

[0010]

A gaming machine according to the present invention comprises:
A game machine in which a player can perform a predetermined game, a game control means for controlling the progress of the game, an electric component control means for controlling an electric component provided in the game machine, and A test signal generating means for generating a test signal capable of identifying a control state, and an output port IC having a plurality of output ports and outputting a signal generated by the test signal generating means are provided. .

The test signal generation means may be configured to select an output port for outputting the generated test signal.

The electric component is a display device, the electric component control means is a display control means for controlling the display device, and a signal generated by the test signal generating means determines whether or not the display control means performs variable display. May be included.

The test signal generated by the test signal generating means is:
The display device may be configured to include a signal indicating the type of display result on the display device.

The display control means controls display of a special symbol used for displaying a big hit and a normal symbol used for displaying a small hit, and the test signal generating means sets a special symbol and a normal symbol. May be configured to output test signals for each of the above with different output ports.

The electric component control means may include an electric component control microcomputer, and the test signal generation means may include a test signal generation microcomputer different from the electric component control microcomputer.

A microcomputer for generating a test signal includes:
It may be configured to execute the test signal creation processing based on information output from the electrical component control microcomputer.

The electric part control means controls the electric parts based on a command from the game control means, and the electric part control microcomputer outputs the command as information to a test signal preparation microcomputer, and generates a test signal preparation signal. The microcomputer for use may be configured to execute a test signal creation process based on a command output from the electrical component control microcomputer.

The game control microcomputer can output a game state test signal for identifying that it is in a state that can be controlled to a game state advantageous to the player. The output timing of the test signal may be adjusted so as not to cause inconsistency with the output timing of the game state test signal to be output.

The game control microcomputer can output a game state test signal for identifying that the state can be controlled to a game state that is advantageous to the player, and the microcomputer for generating a test signal can be provided to the player. The output timing of the test signal is adjusted so that a determination signal of a display result that enables identification of whether or not the game state can be controlled to an advantageous game state is output after the game state test signal is output from the game control microcomputer. May be configured.

The microcomputer for generating a test signal includes:
It is preferable to adjust the output timing of the test signal so that the output timing of the test signal is delayed by a time equal to or longer than the time from when the game control microcomputer executes the command output process to when the game state test signal output process is executed.

[0021]

An embodiment of the present invention will be described below with reference to the drawings. First, the overall configuration of a pachinko gaming machine, which is an example of a gaming machine, will be described. 1 is a front view of the pachinko gaming machine 1 as viewed from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. 3 is a rear view of the pachinko gaming machine 1 as viewed from the back. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine, and may be, for example, a coin gaming machine.

As shown in FIG. 1, the pachinko gaming machine 1
It has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2, there is a hit ball supply tray 3. Below the hitting ball supply tray 3, a surplus ball receiving tray 4 for storing game balls overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing a hitting ball are provided. Behind the glass door frame 2,
The game board 6 is detachably attached. A game area 7 is provided on the front of the game board 6.

In the vicinity of the center of the game area 7, a variable display section (special symbol display device) 9 for variably displaying a plurality of types of symbols and an ordinary symbol display (ordinary symbol display device) 10 using 7-segment LEDs are provided. A variable display device 8 is provided. In this embodiment, the variable display section 9 has, for example, three symbol display areas of “left”, “middle”, and “right”. On the side of the variable display device 8, a passing gate 11 for guiding a hit ball is provided. The hit ball that has passed through the passing gate 11 is guided to the starting winning opening 14 via the ball exit 13. In a passage between the passage gate 11 and the ball outlet 13, there is a gate switch 12 for detecting a hit ball that has passed through the passage gate 11. In addition, the winning ball that entered the starting winning port 14 is
It is guided to the back of the game board 6 and is detected by the starting port switch 17. In addition, a variable winning ball device 15 that performs opening and closing operations is provided below the starting winning port 14. The variable winning ball device 15 is opened by the solenoid 16.

Below the variable winning ball device 15, there is provided an opening / closing plate 20 which is opened by a solenoid 21 in a specific game state (big hit state). In this embodiment, the opening and closing plate 20 serves as a means for opening and closing the special winning opening. The winning ball that enters one (V zone) of the winning balls guided from the opening / closing plate 20 to the back of the game board 6 is detected by the V count switch 22. The winning ball from the opening / closing plate 20 is detected by the count switch 23. Variable display device 8
A start winning prize storage display 18 having four display sections for displaying the number of winning balls entering the starting winning prize port 14 is provided below. In this example, the start winning prize storage display 18 increases the number of lit display units by one each time there is a starting prize, with the upper limit being four. Then, each time the variable display of the variable display unit 9 is started, the number of the lit display units is reduced by one.

The gaming board 6 is provided with a plurality of winning ports 19 and 24, and the winning of the game balls to the respective winning ports 19 and 24 is determined by correspondingly provided winning port switches 19a and 19a.
24a. At the left and right sides of the game area 7, there are provided decorative lamps 25 which are displayed blinking during the game, and at the lower part there is an out port 26 for absorbing hit balls which have not won. Also, on the upper left and right sides outside the game area 7,
Two speakers 27 that emit sound effects are provided.
A game effect LED 28a and game effect lamps 28b and 28c are provided on the outer periphery of the game area 7.

In this example, one of the speakers 27
Is provided with a prize ball lamp 51 which is lit when a premium ball is paid out, and a ball out lamp 52 which is lit up when the supply ball is out is provided near the other speaker 27. Further, FIG. 1 also shows a card unit 50 which is installed adjacent to the pachinko gaming table 1 and enables lending of a ball by inserting a prepaid card.

The card unit 50 has a usable indicator lamp 151 for indicating whether or not the card is usable. If there is a fraction (a number less than 100 yen) in the balance information recorded in the card, the fraction is displayed. Fraction display switch 1 for displaying on a frequency display LED provided near hit ball supply tray 3
52, a connecting stand direction indicator 15 indicating which side of the pachinko gaming machine 1 the card unit 50 corresponds to
3. Card insertion indicator 154 indicating that a card has been inserted into card unit 50, card insertion slot 155 into which a card as a recording medium is inserted, and a card reader provided on the back of card insertion slot 155 A card unit lock 156 is provided to release the card unit 50 when checking the mechanism of the writer.

The hitting ball fired from the hitting ball launching device enters the game area 7 through the hitting ball rail, and thereafter, enters the game area 7
Come down. When a hit ball is detected by the gate switch 12 through the passing gate 11, the number displayed on the variable display (ordinary symbol display) 10 changes continuously. Further, when a hit ball enters the starting winning opening 14 and is detected by the starting opening switch 17, if the change of the symbol can be started,
The symbol in the variable display section 9 starts rotating. If it is not possible to start changing the symbol, the start winning memory is increased by one.

The rotation of the image in the variable display section 9 stops when a certain time has elapsed. If the combination of images at the time of stop is a combination of big hit symbols, the game shifts to a big hit game state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or until a predetermined number (for example, 10) of hit balls is won. Then, when a hit ball wins in the specific winning area while the opening and closing plate 20 is opened and is detected by the V count switch 22, a continuation right is generated and the opening and closing plate 20 is opened again. Generation of the continuation right is permitted a predetermined number of times (for example, 15 rounds).

If the combination of images in the variable display section 9 at the time of stoppage is a combination of big hit symbols with probability fluctuation, the probability of the next big hit increases. That is, a high probability state, which is more advantageous for the player, is obtained. When the stop symbol on the ordinary symbol display 10 is a predetermined symbol (hit symbol = small hit symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol on the ordinary symbol display 10 hits the symbol is increased, and the opening time and the number of times the variable winning ball device 15 is opened are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. On the back side of the variable display device 8, as shown in FIG. 2, a ball storage tank 38 is provided above the mechanism plate 36, and when the pachinko gaming machine 1 is installed on the gaming machine installation island, the game balls from above. Ball storage tank 3
8 is supplied. The game ball in the ball storage tank 38 reaches the ball payout device through the guiding gutter 39.

On the mechanism plate 36, a variable display control unit 29 for controlling the variable display section 9 via the relay board 30, and a game control board (main board) covered with a board case 32 and mounted with a game control microcomputer and the like. ) 31, a relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a prize ball board 37 on which a payout control microcomputer or the like for controlling payout of game balls is mounted. is set up. Further, the mechanism plate 36 includes
A ball launching device 34 for launching a ball into the game area 7 by using the rotating force of a motor, a decorative lamp 25, and a game effect LED
28a, gaming effect lamps 28b, 28c, prize ball lamp 5
1 and a lamp control board 35 for sending a signal to the out-of-ball lamp 52 are provided.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine 1 as viewed from the rear. On the back of the game board 6, FIG.
As shown in the figure, the winning ball set cover 4 for guiding the winning ball winning each winning port and the winning ball device along a predetermined winning path.
0 is provided. Of the winning balls guided to the winning ball collection cover 40, those winning through the opening / closing plate 20 are controlled so that the ball payout device 97 pays out a relatively large number of prize balls (for example, 15). The winnings through the starting winning opening 14 are controlled so that the ball payout device (not shown in FIG. 3) pays out a relatively small number of prize balls (for example, 6). Then, the winning prize through the other prize port 24 and the winning ball device is controlled so that the ball payout device pays out a relatively medium number of prize balls (for example, 10). Note that FIG. 3 illustrates the relay board 33 as an example.

Signals from the winning opening switches 19a and 24a, the starting opening switch 17 and the V count switch 22 are sent to the main board 31 in order to control the winning ball payout.
When the starting port switch 17 is turned on, for example, “6” is output as a prize ball number signal, and when the count switch 23 is turned on, “15” is output as a prize ball number signal, for example. When the winning opening switches 19a and 24a are turned on, for example, "10" is output as the prize ball number signal.

FIG. 4 is a block diagram showing an example of a circuit configuration of the main board 31. FIG. 4 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the emission control board 91, and the symbol control board 80.
The pachinko machine 1 is provided on the main board 31 according to the program.
And a switch circuit 58 for giving signals from the gate switch 12, the starting port switch 17, the V count switch 22, the count switch 23, the winning port switches 19a and 24a, and the prize ball count switch 301A to the basic circuit 53. And a solenoid circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the opening and closing plate 20 in accordance with a command from the basic circuit 53.

According to the data supplied from the basic circuit 53, jackpot information indicating the occurrence of a jackpot, effective start information indicating the number of start winning balls used to start image display on the variable display section 9, and probability fluctuation have occurred. And an information output circuit 64 that outputs probability change information or the like indicating the fact to a host computer such as a hall management computer.

The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as an example of a storage means used as a work memory, a CPU 56 for performing a control operation according to the program, and an I / O port unit 5.
7 inclusive. In this embodiment, the ROM 54 and the RAM 5
5 is built in the CPU 56. That is, the CPU 5
Reference numeral 6 denotes a one-chip microcomputer. In addition, 1
The chip microcomputer has at least the RAM 55
And the ROM 54 and the I / O port unit 57 may be external or internal.

Further, the main board 31 includes a system reset circuit 65 for resetting the basic circuit 53 when the power is turned on, and an I / O port unit 57 which decodes an address signal provided from the basic circuit 53 and decodes the address signal. Kano I /
An address decode circuit 67 for outputting a signal for selecting the O port is provided. Note that the ball payout device 9
There is also switch information input to the main board 31 from 7,
In FIG. 4, they are omitted.

A hit ball launching device that hits and launches a game ball is driven by a drive motor 94 controlled by a circuit on a launch control board 91. Then, the driving force of the driving motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

In this embodiment, the lamp control means mounted on the lamp control board 35 is used to display the start memory display 18, the gate passage memory display 41 and the decoration lamp 25 provided on the game board. Controls the game and the game effect lamp / LED 28 provided on the frame side.
a, 28b, and 28c, display control of the award ball lamp 51, and the ball out lamp 52 are performed. The display control of the variable display unit 9 for variably displaying special symbols and the ordinary symbol display 10 for variably displaying ordinary symbols is performed by display control means mounted on the symbol control board 80.

FIG. 5 is a block diagram showing a portion of the main board 31 relating to a test signal output. In the main board 31, signals from each sensor are input to the input port 577 and also supplied to the test signal output circuit 71.
In this embodiment, the sensor is a gate switch 12, a starting port switch 17, a count switch 23,
V count switch 22 and winning opening switch 19a,
24a, but also includes various switch information and sensor output information input to the main board 31. An input circuit 578 shown in FIG. 5 is a circuit corresponding to the switch circuit 58 in FIG.

The output buffer 61 outputs a signal output from the CPU 56 via the output port 570 to the payout control board 3.
7, a driver circuit and a buffer circuit. In the payout control board 37, the payout control CPU inputs a payout control signal from the main board 31 via an input circuit. The output buffer 62 controls various lamps / LEDs based on a signal output from the CPU 56 via the output port 570.
Drive.

The output buffer 63 sends the display control command output from the CPU 56 via the output port 570 to the symbol control board 80. In the symbol control board 80, the display control CPU inputs a display control command via an input buffer, and based on the display control command,
The variable display unit 9 and the ordinary symbol display 10 are driven.

The test signal output circuit 71 of the main board 31 performs processing such as amplifying each input signal and outputs the test signal to the test signal terminals 72 and 73 as a test signal. Test signal terminal 7
Reference numerals 2 and 73 each include a signal pin to which a probe from the test device can be connected and a connector to which a cable from the test device can be connected. When a connector is used, a male connector is used. If the male type is used, the connector provided at the end of the cable extending from the test device or the like can be a female type, and the possibility of breakage of the connector at the end of the cable from the test device or the like is reduced. The test signal terminal 7
The components 2 and 73 may be mounted on the main board 31 or may be mounted on a relay board or the like to reduce the cost of the main board 31 during mass production. When a connector is used, a wiring pattern for connecting the connector may be prepared on the main board 31, and the connector may be mounted only during the test.

From the test signal terminals 72 and 73, for example, the following signals are output.

There are shot ball signals 1 and 2 which are signals which are turned on when a game ball shot on the game board is detected. Further, there are prize ball signals 1 to 3 which are signals which are turned on when a game ball paid out from the ball payout device 97 is detected.

In a gaming machine provided with a tulip-type accessory, a tulip-type accessory 1 prize signal, which is a signal that is turned on when a game ball is awarded to the winning opening, is formed.
There is a tulip-style character 4 winning signal. Further, there are a normal winning opening 1 winning signal to a normal winning opening 15 winning signal which is a signal which is turned on when a game ball wins in each normal winning opening. In this embodiment, it is an output signal of a switch for detecting a game ball having won each of the winning ports 19a and 24a.

In a gaming machine provided with an interlocking accessory, there are interlocking accessory 1 prize signals to interlocking accessory 4 prize signals, which are signals that are turned on when a game ball is won in the winning opening. In addition, there are special electric auditors 'prize signal 1 to special electric auditors' prize signal 3 which are signals that are turned on when a game ball is awarded to the special winning opening. In this embodiment, a signal corresponding to turning on of the count switch 23 is the special electric auditors' prize signal 1. Further, there is a specific area passage signal which is a signal indicating that the game ball has passed the specific area of the special winning opening. In this embodiment, a signal corresponding to the output of the V count switch 22 is a specific area passing signal.

There are a starting port 1 prize signal to a starting port 3 prize signal which are turned on when a game ball is won in each starting winning port. In this embodiment, the signal corresponding to the output of the starting winning port 17 is the starting port 1 winning signal. Also,
In the case where a linked ball is provided, there are a gate passing signal related to the linked bar 1 to a gate passing signal related to the linked bar 4 which is a signal that is turned on when a game ball passes through a gate related to those. Further, a gate passing signal related to the ordinary motor-operated object 1 to a gate passing signal related to the ordinary motor-operated accessory 4, which is a signal that is turned on when a game ball passes through a gate related to the ordinary motor-operated accessories, when they are provided. There is.

The gate 1 passing signal relating to the ordinary symbol to the gate 3 passing signal relating to the ordinary symbol are signals which are turned on when the game ball passes the gate which is a condition for starting the variation of the ordinary symbol. In this embodiment, the signal corresponding to the output of the gate switch 12 is the gate 1 passing signal for a normal symbol. Further, there is a special electric accessory opening signal which is a signal which is turned on at the start of opening of the special winning opening and turned off when the special winning opening is closed. Further, there is a special electric accessory in-operation signal which is a signal which is turned on when the special electric accessory is activated and turned off when the special electric accessory is closed. Then, there is a normal symbol hit signal which is a signal which is turned on when the normal symbol is determined by a winning combination and turned off when the operation of the normal electric accessory ends.

There is an ordinary electric accessory opening signal which is a signal which is turned on when the ordinary electric accessory (corresponding to a start winning port in this embodiment) starts to be opened and turned off when the ordinary electric accessory is closed. In addition, there is a normal electric accessory operating signal, which is a signal that is turned on when the ordinary electric accessory is activated and turned off when the ordinary electric accessory is closed.

There are a tulip-type accessory 1 enlargement signal to a tulip-type accessory 4 enlargement signal, which are signals that are turned on at the start of enlargement of the entrance of each tulip-type accessory and turned off at the end of enlargement. Further, there are interlocking accessory 1 open signals to interlocking accessory 4 open signals, which are signals that are turned on at the start of expansion of the entrance of each interlocking role and turned off at the end of expansion. Further, there is an accessory continuous operation device operation signal which is a signal which is turned on when the operation of the accessory continuous operation device is started and turned off when the operation is completed. Then, there is a special symbol jackpot signal which is a signal which is turned on when the special symbol is determined as the big hit symbol and turned off at the end of the big hit operation.

There is a special symbol middle hit signal which is a signal which is turned on at the start of a middle hit operation (a big win opening time of 1.5 seconds to 6 seconds) by a symbol other than the big hit symbol and turned off at the end of the hit operation. In addition, there is a special symbol small hit signal which is a signal which is turned on at the start of a small hit operation by a symbol other than the big hit symbol (a big winning opening time of 0.5 seconds to 1.5 seconds) and turned off at the end of the hit operation. . Furthermore, there is a special symbol hit signal which is a signal which is turned on at the start of a hit operation (a big winning opening time of 0.5 seconds or less) by a symbol other than the big hit symbol and turned off at the end of the hit operation.

There is a special symbol hold first signal, which is a signal that is turned on while the number of stored special symbol change operation reservations is one or more and turned off when the number of special symbol change operation is zero. There is a special symbol hold second signal, which is a signal that turns on while the number of stored symbols is 2 or more and turns off when the number of stored symbols is 1 or less, and the number of stored special symbol changes is 3 or more. There is a special symbol hold third signal which is a signal that is turned on while it is off and turns off when it becomes 2 or less. It turns on while the number of stored operation numbers of special symbol fluctuations is 4 and turns on when it becomes 3 or less. There is a special symbol hold fourth signal which is a signal to be turned off. In this embodiment, the first to fourth starting winning storage signals correspond to the first special symbol holding signal to the fourth special symbol holding signal.

There is a first normal symbol hold signal which is a signal which is turned on while the number of stored normal symbol change operation suspension numbers is 1 or more and turned off when it becomes 0, and the number of normal symbol fluctuation operation suspensions. There is a second signal, a normal symbol hold signal, which is a signal that turns on when the number of stored symbols is 2 or more and turns off when the number of stored symbols becomes 1 or less. There is a third symbol of the normal symbol hold, which is a signal that turns on while it is off and turns off when it becomes 2 or less. There is a normal symbol hold fourth signal which is a signal to be turned off. In this embodiment, the first to fourth gate passage storage signals correspond to the first to fourth normal symbol holding signals.

There is a special symbol high probability state signal which is a signal which is turned on when the lottery probability relating to the special symbol is in the high probability state. Further, there is a special symbol variation time reduction state signal which is a signal that is turned on when the variation time relating to the special symbol is in the reduction state. Further, there is a normal symbol high probability state signal which is a signal that is turned on when the lottery probability of the normal symbol is in the high probability state. In addition, there is a normal symbol variation time reduction state signal that is a signal that is turned on when the variation time relating to the ordinary symbol is in a reduced state. Further, there is a normal electric accessory opening extended state signal which is a signal that is turned on when the time of opening or the like related to the ordinary electric accessory is extended.

There is a gaming machine error state signal which is a signal which is turned on when an abnormal state of the gaming machine is detected. In addition, there is a gate passing signal that is a signal that is turned on when a game ball passes through a gate other than the gate related to the linked accessory, the gate related to the ordinary electric accessory, and the gate related to the ordinary symbol.

FIG. 6 is a block diagram showing an example of a circuit configuration in the symbol control board 80. Display control CPU 101
Operates according to a program stored in the ROM 151, and when a strobe signal is input from the main board 31 via the input buffer circuit 105, the input buffer circuit 105
, A display control command is received.

The display control CPU 101 controls the display of the screen displayed on the variable display unit 9 and the ordinary symbol display 10 according to the received display control command.
Specifically, a command corresponding to the display control command is sent to VDP1.
Give to 03. The VDP 103 has ROMs 153 and 154
Read the required data from The VDP 103 controls the variable display unit 9 and the ordinary symbol display 1 according to the input data.
Image data to be displayed at 0 is generated, and the image data is stored in the VRAM 152. And the VRAM 15
2 is converted into an image signal, and the output circuit 1
It is output to the variable display unit 9 and the ordinary symbol display 10 via 55. If the probability variation determiner 81 for performing the notification effect for determining whether or not to set the high probability state is provided separately, the display control CPU 101 and the VDP
103 also controls the display of the probability variation determiner 81.

In this embodiment, the symbol control board 80
The test CPU 161 and the test signal output circuit 120
Is installed. In this example, the test CPU 161
Is a CPU having a built-in ROM and RAM, and creates a test signal to be supplied to a test device or the like connected outside the gaming machine. A part of the test signal is transmitted to the main board 31.
Is also output from

The test signal output circuit 120 has an I / O port. The design control board 80 includes a test CP.
Connectors 121 to 126 for outputting a test signal from U161 to the outside are mounted. Note that connector 1
21 to 126 may be attached only at the time of testing. By doing so, the cost can be reduced at the mass production stage.

Next, the operation of the gaming machine will be described. FIG.
9 is a flowchart showing a main process executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main processing, the CPU 56 first performs necessary initialization (step S1).

Then, it is confirmed whether or not the data protection processing of the backup RAM area (for example, the power failure occurrence NMI processing such as the addition of parity data) has been performed when the power is turned off (step S2). In this embodiment, when an unexpected power failure occurs, a process for protecting data in the backup RAM area is performed. The case where such protection processing has been performed is regarded as backup. After confirming that there is no backup, the CPU 56 executes an initialization process (steps S2 and S3).

When the backup is confirmed, the CPU 5
6 performs a game state restoring process for returning the internal state to the state when the power is turned off (step S6). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the program returns to that address.

When the execution of the initialization process (Step S3) is completed, the main process proceeds to a loop process in which the timer interrupt flag is monitored (Step S9). In the loop, a display random number update process (step S8) for determining a special symbol, such as a missing symbol, is also executed.

When detecting that the timer interrupt flag is set in step S9, the CPU 56 resets the timer interrupt flag (step S1).
0), a game control process and a test signal output process (step S12) are executed (step S11). In this embodiment, the internal timer times out every 2 ms, and a timer interrupt flag is set in a timer interrupt process based on the time up. Therefore, by the above control, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interruption processing, and the game control processing is executed in the main processing. However, the game control processing may be executed in the timer interruption processing.

In the test signal output process, for example, a test signal output from the test signal terminal 73 shown in FIG. 5 is generated. That is, in the test signal output processing, the CPU 56 creates a game state signal capable of identifying game control states that are variously changed in the game control processing, and outputs the created game state signal as a test signal. Examples of the game control state include a jackpot state and an error state.

FIG. 8 is a flowchart showing the game control processing in step S11. In the game control process, C
First, the PU 56 inputs the states of the gate sensor 12, the start-up opening sensor 17, the count sensor 23, and the winning opening switches 19a and 24a via the switch circuit 58, and determines whether or not there is a winning for each winning opening or the winning device. (Switch processing: step S21).

Next, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S22).

Next, a process of updating each counter indicating a random number for determination such as a random number for big hit determination used in game control is performed (step S23). The CPU 56 further includes:
A process for updating a display random number such as a random number for determining the type of stop symbol is performed (step S24).

Further, the CPU 56 performs a special symbol process (step S25). In the special symbol process control, a corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to a gaming state. Then, the value of the special symbol process flag is updated during each processing according to the gaming state. Also, a normal symbol process is performed (step S26). In the ordinary symbol process process, a corresponding process is selected and executed according to an ordinary symbol process flag for controlling the ordinary symbol display device 10 by the 7-segment LED in a predetermined order. Then, the value of the normal symbol process flag is updated during each process according to the gaming state.

The CPU 56 performs a process of setting a control command sent to the payout control board 37 or the like in a predetermined area of the RAM 55 and sending the control command (command control process: step S27).

Next, the CPU 56 performs a data output process of outputting data such as jackpot information, start information, and probability fluctuation information supplied to the hall management computer (step S29).

Further, the CPU 56 issues a drive command to the solenoid circuit 59 when a predetermined condition is satisfied (step S30). The solenoid circuit 59 drives the solenoids 16 and 21 in response to the drive command, and brings the variable winning ball device 15 or the open / close plate 20 into an open state or a closed state.

Further, the CPU 56 sets the number of prize balls based on the detection output of the switches 17, 23, 19a, 24a for detecting a winning in each winning opening (step S31). Specifically, a payout control command is output to the payout control board 37 in response to the winning detection. Dispensing control board 37
The payout control CPU mounted on the device drives the ball payout device 97 in accordance with the payout control command.

FIG. 9 is a flowchart showing an example of a special symbol process program executed by the CPU 56. The special symbol process process shown in FIG. 9 is a specific process of step S25 in the flowchart of FIG. When performing the special symbol process, the CPU 56
After performing the variation reduction timer subtraction process (step S310), steps S300 to S309 are performed according to the internal state.
Is performed. The fluctuation shortening timer is a timer for setting the fluctuation time when the fluctuation time of the special symbol is shortened.

Special symbol change waiting process (step S30)
0): The start winning port 14 (in this embodiment, the winning port of the variable winning ball device 15) is hit and the start port sensor 17 is turned on. When the starting port sensor 17 is turned on, the starting winning memory number is increased by + if the starting winning memory number is not full.
1 and a big hit determination random number is extracted.

Special symbol determination processing (step S301):
When the state in which the variable display of the special symbol can be started, the number of start winning prize stored is confirmed. If the starting prize memory number is not 0,
It is determined whether to make a big hit or an out according to the value of the extracted big hit determining random number.

Stop symbol setting processing (step S302):
The stop symbol of the left and right middle symbols is determined.

Reaching operation setting processing (step S30)
3): Whether or not to perform the reach operation is determined according to the value of the reach determination random number, and the fluctuation period at the time of reach is determined according to the value of the reach type determination random number.

All symbols change start processing (step S30)
4): In the variable display section 9, control is performed so that all symbols start to change. At this time, with respect to the symbol control board 80,
The left and right middle final stop symbols and information instructing the variation mode are transmitted. When processing is completed, the internal state (process flag)
Is updated to shift to step S305.

All symbols stop wait processing (step S30)
5): When a predetermined time (time indicated by the fluctuation shortening timer in step S310) elapses, control is performed so that all the symbols displayed on the variable display unit 9 are stopped. And
If the stop symbol is a combination of big hit symbols, the internal state (process flag) is updated so as to shift to step S306. If not, the internal state is updated to shift to step S300.

Grand opening opening process (step S30)
6): Control for opening the special winning opening is started. Specifically, the counter and the flag are initialized, and the solenoid 21 is driven to open the special winning opening. Also, a big hit flag (a flag indicating that a big hit is being made) is set. Upon completion of the process, the internal state (process flag) is updated so as to shift to step S307.

Processing during opening of the special winning opening (step S30)
7): Control for sending display control command data for the special winning opening round display to the symbol control board 80, processing for confirming establishment of the closing condition of the special winning opening, and the like are performed. When the final closing condition of the special winning opening is satisfied, the internal state is updated to shift to step S308.

Specific area effective time processing (step S30)
8): The presence or absence of passage of the V count switch 22 is monitored, and a process of confirming that the big hit game state continuation condition is satisfied is performed. If the condition of the jackpot game state continuation is satisfied and there is still a remaining round, the internal state is changed to step S30.
Update to move to 6. If the big hit game state continuation condition is not satisfied within the predetermined effective time, or if all rounds have been completed, the internal state is updated to shift to step S309.

Big hit end processing (step S309): A display for notifying the player that the big hit gaming state has ended is performed. When the display is completed, the internal state is updated so as to shift to step S300.

FIG. 10 is a flowchart showing the ordinary symbol process (step S26). In the ordinary symbol process process, the CPU 56 executes one of the processes shown in steps S62 to S66 according to the value of the ordinary symbol process flag after executing the gate switch process of step S61.

In the gate switch process, the ON state of the gate switch 12 based on the passing of the ball through the passing gate 11 which is a condition for starting the symbol change is detected. Gate switch 1
If 2 is on, it is checked whether or not the gate passage storage counter has reached the maximum value ("4" in this example). If not, the value of the gate passage storage counter is incremented by one. In addition, the LED of the passage storage display 41 is turned on according to the value of the gate passage storage counter. And CPU5
Reference numeral 6 extracts the value of the random number for hit determination and stores the value.

In the ordinary symbol change waiting process of step S62, the CPU 56 determines that the value of the ordinary symbol passing storage counter is 0.
Otherwise, the value of the normal symbol process flag is updated. If the value of the normal symbol passing storage counter is 0, nothing is performed.

In the ordinary symbol determination processing of step S63,
The CPU 56 determines the hit / miss based on the value of the extracted hit determination random number. Then, the normal symbol display unit 10 executes a normal symbol change process. In this embodiment, a specific normal symbol change processing control is executed by the display control means. When the display control means receives the display control command indicating the start of the normal symbol change, the display control means starts the normal symbol change. When the display control command indicating the stop of the normal symbol fluctuation is received, the fluctuation of the normal symbol is stopped, and the notified stopped symbol is displayed. Therefore, in the ordinary symbol variation process of step S64, it is confirmed whether or not the ordinary symbol variation time timer has timed out. If the timeout has occurred, the normal symbol process flag is updated to a value indicating the normal symbol stop processing.

In the ordinary symbol stop processing of step S65,
Control for transmitting a display control command indicating a normal symbol fluctuation stop is performed. Then, when it is determined to be a hit, the normal electric accessory hit flag is set and the normal symbol process flag is updated to a value indicating the start winning opening opening / closing process. When it is determined to be a loss, the normal symbol process flag is updated to a value indicating the normal symbol change waiting process. In the start winning opening opening / closing process in step S66, control for opening the starting winning opening (variable winning ball device 15) for a predetermined number of times is performed.

FIG. 11 is an explanatory diagram showing an example of the contents of the display control command. In the example shown in FIG. 11, commands 8000 (H) to 8022 (H), 8100 (H) to
8122 (H) is a symbol control command for designating a variation pattern of the special symbol in the variable display section 9 for variably displaying the special symbol. Note that the command for designating the variation pattern also serves as the variation start instruction. Command 88XX (X
(= 4 bit arbitrary value) is a symbol control command related to the variation pattern of the ordinary symbol variably displayed on the ordinary symbol display 10. The command 89XX is a symbol control command for designating a stop symbol of an ordinary symbol. Command 8AX
X (X = arbitrary value of 4 bits) is a symbol control command for instructing to stop variable display of a normal symbol.

Commands 91XX, 92XX and 93X
X is a symbol control command for designating a left-middle-right stop symbol of a special symbol. The command A0XX is a symbol control command for instructing stoppage of the variable display of the special symbol.
The command BXXX is a symbol control command sent from the start of the big hit game to the end of the big hit game. The commands C000 to EXXXX are symbol control commands relating to the change of the special symbol and the display state of the variable display section 9 irrespective of the jackpot game. Upon receiving the above-described display control command from the game control means of the main board 31, the display control means of the symbol control board 80 changes the display state of the variable display unit 9 and the ordinary symbol display 10 according to the contents shown in FIG. change.

FIG. 12 shows the main board 31 to the symbol control board 8.
FIG. 8 is an explanatory diagram showing an example of a command form of a display control command sent to 0. In this embodiment, the display control command has a 2-byte configuration, and the first byte is MODE.
(Command classification), and the second byte indicates EXT (command type). The command form shown in FIG. 12 is an example, and another command form may be used.
The first bit (bit 7) of MODE data is always "1"
And the first bit (bit 7) of the EXT data is always "0".

FIG. 13 is a timing chart showing the relationship between the 8-bit control signal constituting the display control command for the symbol control board 80 and the INT signal (strobe signal). As shown in FIG. 13, when a predetermined period elapses after the MODE or EXT data is output to the output port, the CPU 56 outputs the signal INT indicating the data output.
Turn on the signal. When a predetermined period elapses therefrom, the INT signal is turned off.

FIG. 14 is a flowchart showing the main processing executed by the display control CPU 101 mounted on the symbol control board 80. In the main processing, the display control CP
The U101 first performs an initial value setting process such as clearing the RAM area (step S701). After that, the display control CPU 101 shifts to a loop process for checking the monitoring of the timer interrupt flag (step S702).

In this embodiment, the display control CPU 1
01 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is 2
ms. And when a timer interrupt occurs,
The display control CPU 101 sets a timer interrupt flag in the timer interrupt processing.

The display control CPU 101 proceeds to step S7.
In 02, when it is detected that the timer interrupt flag has been set, the timer interrupt flag is reset (step S703), and an image control process for performing display control according to a command from the game control means (step S70)
Execute 4). In the image control process, the display control CPU 101 performs image control on a special symbol, a normal symbol, and a probability change symbol.

The display control CPU 101 performs a process for generating a test signal (step S70).
5). That is, in response to receiving a command for controlling the special symbol, the ordinary symbol, and the probable change determination symbol, or outputting the information corresponding to the control state of the special symbol, the ordinary symbol, and the probable variation determination symbol to the test CPU 161. Display control CPU1
01 and the test CPU 161 are:
The processing may be performed through an I / O port, or the test CPU 16 may be connected to the bus of the display control CPU 101.
1 may be connected. Further, other data transmitting / receiving means may be employed.

FIG. 15 is a flowchart showing a display control command receiving process by the interrupt process. The display control INT signal from the main board 31 is input to an interrupt terminal of the display control CPU 101. Therefore, I from the main substrate 31
When the NT signal is turned on, the display control CPU 101
Is interrupted. Then, the reception processing of the display control command shown in FIG. 15 is started.

In the display control command receiving process, the display control CPU 101 first saves each register in the stack (step S850). Next, data is read from the input port assigned to the input of the display control command data (step S851). And 2
It is determined whether or not this is the first byte of the display control command having the byte configuration (step S852). The first bit of the received command is “1” whether or not it is the first byte.
It is confirmed by whether or not. The first bit is "1"
Should be the MODE byte (first byte) of the display control command having a 2-byte configuration (FIG. 1).
2). Therefore, if the first bit is “1”, the display control CPU 101 determines that a valid first byte has been received and stores the received command in the confirmed command buffer indicated by the command reception number counter in the reception buffer area (step S853).

If it is not the first byte of the display control command, it is checked whether the first byte has already been received (step S854). Whether or not the data has already been received is confirmed based on whether or not valid data is set in the reception buffer.

If the first byte has already been received,
It is checked whether the first bit of the received 1 byte is “0”. And if the first bit is “0”,
Assuming that the valid second byte has been received, the received command is stored in the fixed command buffer indicated by the command reception number counter +1 in the reception buffer area (step S855). The first bit should be “0” in the EXT byte (second byte) of the display control command having the 2-byte configuration (see FIG. 12). If it is determined in step S854 that the first byte has already been received, the process ends if the first bit of the data received as the second byte is not “0”.

When the second byte of command data is stored in step S855, 2 is added to the command reception number counter (step S856). Then, it is checked whether or not the command reception counter is 12 or more (step S857), and if it is 12, the command reception number counter is cleared (step S858). After that, the saved register is restored (step S859),
Interrupt permission is set (step S859).

In this example, a ring buffer type reception buffer capable of storing six 2-byte display control commands is used. Therefore, the reception buffer is buffer 1
It consists of a 12-byte area of ~ 12. Then, a command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11.

The display control command has a two-byte configuration, and the first byte (MODE) and the second byte (EXT) can be immediately distinguished on the receiving side. In other words, the receiving side can immediately detect whether the data as MODE or the data as EXT has been received by the first bit. Therefore, as described above, it can be easily determined whether or not appropriate data has been received. Then, the incorrect data is erased by being overwritten with the next reception data in the reception buffer.

FIG. 16 is a flowchart showing an example of the special symbol display processing. The special symbol display process is a process included in step S704 of the main process shown in FIG. In special symbol display processing, display control C
The PU 101 first checks whether or not the special symbol is changing on the variable display unit 9 (step S141). If it is changing, it is confirmed whether or not a display control command indicating a special symbol change stop has been received (step S142). If it has not been received, the special symbol variation process is continued (step S144).

When the display control command indicating the special symbol stop is received, in step S143, if the display control command including the information of the big hit is received at the start of the change, the special symbol corresponding to the big hit is received. The symbol confirmation display is performed. Also, if a display control command including information indicating a loss has been received at the start of the change,
A special symbol confirmation display of the symbol corresponding to the loss is executed.

If it is determined in step S141 that the special symbol is not fluctuating, it is checked whether or not the special symbol confirmation display is being displayed on the variable display section 9 (step S145). If not, it is confirmed whether or not a display control command indicating the start of the special symbol change has been received (step S14).
6). If it has been received, the special symbol variation process is started (step S147). During the change of the special symbol, the display control CPU 101 performs display such that each symbol displayed in the three display areas of the variable display section 9 changes.

If it is determined in step S145 that the special symbol confirmation display is being displayed, it is confirmed whether or not a display control command indicating stoppage of the special symbol has been received (step S14).
8). If it has not been received, the special symbol confirmation display is continuously performed (step S150). When the display control command indicating the special symbol stop has been received, the special symbol determination display ends (step S149).

FIG. 17 shows a probable change notification symbol (probability change determination symbol).
It is a flowchart which shows an example of a display process. The probable change notification symbol display process is a process included in step S704 of the main process shown in FIG. In this embodiment, after the end of the change of the special symbol, an effect for reporting a certainty change is performed using the variable display unit 9. Then, when the game control means determines that the probability is to change, the display control CPU 101 sets the result of the effect to a display result corresponding to the probability change entry.

In the probability variation notification symbol display process, the display control CPU 101 first confirms whether or not a determination result designation command (probability variation) has been received (step S141).
a). Upon receiving the determination result designation command (probable change), the display control CPU 101 determines a stop symbol indicating the probable change (step S142a) and starts changing the probable change notification symbol (step S143a). During the change of the probable change notification symbol, the display control CPU 101 performs display such that each symbol displayed in the three display areas of the variable display unit 9 changes, for example.

In step S141a, if the judgment result designation command (probable change) has not been received, it is confirmed whether or not the judgment result designation command (non-probable change) has been received (step S144a). Upon receiving the determination result designation command (non-probable change), the display control CPU 101 determines a stop symbol indicating the non-probable change (step S145a),
The change of the probable change notification symbol is started (step S146).
a).

In step S144a, if the judgment result designation command (non-probable change) has not been received, it is confirmed whether or not the probable change notification symbol is changing (step S14).
7a). If it is changing, it is checked whether the changing time has elapsed (step S148a). If the fluctuating time has elapsed, the notification symbol is confirmed and displayed (step S149).
a). In this case, if the judgment result designation command (probable change) has been received, a notification design confirmation display of the symbol corresponding to the probable change big hit is performed. If the judgment result designation command (non-probable change) has been received, a notification symbol confirmation display of the symbol corresponding to the probable change loss is performed. In the determination in step S148a, if the fluctuation time has not elapsed, the notification symbol fluctuation processing is continued (step S150a).

If it is determined in step S147a that the probable change notification symbol is not fluctuating, it is checked whether or not the notification symbol confirmation display is being displayed on the variable display section 9 (step S151).
a). If the display is not being performed, it is determined whether the display time has elapsed (step S152a). If the display time has elapsed, the notification symbol confirmation display is terminated (step S15).
3a). If the display time has not elapsed, the notification symbol confirmation display is continuously performed (step S154a).

FIG. 18 is a flowchart showing an example of the ordinary symbol display processing. The normal symbol display process is a process included in step S704 of the main process shown in FIG. In a normal symbol display process, a display control CPU
The first step 101 is to check whether or not the ordinary symbol is changing on the ordinary symbol display 10 (step S151).
If not, it is confirmed whether or not a display control command indicating the start of normal symbol change has been received (step S15).
2). If it has been received, the normal symbol variation process is started (step S153). During the change of the ordinary symbol, the display control CPU 101 causes the ordinary symbol display device 10, for example, to display a count-up every 0.1 seconds. By using the VDP 103, more complicated ordinary symbol display can be performed.

In step S151, if the ordinary symbol is changing, it is checked whether or not a display control command indicating the end of the ordinary symbol change (ordinary symbol stop) has been received (step S154). If it has not been received, the normal symbol variation process is continued (step S156). When the display control command indicating the end of the ordinary symbol change is received, the symbol change of the ordinary symbol display 10 is stopped with the stop symbol already received (step S155).

As described above, in this embodiment, the display control CPU 101 mounted on the symbol control board 80 is
The display control of the variable display unit 9 for variably displaying the special symbol and the probability change notification symbol and the ordinary symbol display 10 for variably displaying the ordinary symbol are performed. Then, the CPU 56 of the main board 31
At the start of the change of the display on the variable display section 9,
At the end of display, a corresponding display control command is sent to the symbol control board 80. In addition, the display control command is sent to the symbol control board 80 at the start and end of the change of the display on the ordinary symbol display 10.

The display control CPU 101 can recognize the fluctuation time and the display time of each symbol based on each command.
Since the CPU 56 of the main board 31 sends a command so that the fluctuation time can be specified, the CPU 56 does not need to send a command indicating other detailed control. For example,
There is no need to send a command indicating the changed symbol every 0.1 seconds or 0.2 seconds.

FIG. 19 shows the symbol control board 8 shown in FIG.
3 is a block diagram illustrating a configuration example of a test signal output circuit 120 at 0. FIG. The test signal output circuit 120 includes a plurality of I / O expanders. As shown in FIG. 19, in this example, two I / O expanders 120
A, 120B are mounted. The I / O expander is an output port IC having a plurality of I / O ports.

FIG. 20 is a block diagram showing an example of an I / O expander that can be used in this embodiment. The I / O expanders shown in FIG.
It has output ports 0 to 3 having three output bits. Each bit of output port 0 is set to P00-P0
7. Each bit of the output port 1 is P10 to P17, each bit of the output port 2 is P20 to P27, and each bit of the output port 3 is P30 to P37.

The I / O expander is reset (RES)
ET) input terminal, and when a low level is input to the reset input terminal, all outputs (P00 to P07, P10
To P17, P20 to P27, and P30 to P37) are set to low level. The address decoder is a test CPU.
A signal for selecting output port 0 to output port 3 is generated according to the address signals (A0 to A7) from 161 and the address setting signal (CSIO). For example,
To set the output port 0 bit to high level,
From the test CPU 161, an address signal designating the address assigned to the output port 0 is output, and data with the corresponding bit set to “1” is output to the data bus. Further, the low active CSIO is set to the low level, and the low active WR signal is set to the low level.

The output signals from the output ports 0 to 3 are latched in the output ports 0 to 3, so that the test CPU 161 can read the output state. For example, when reading the output state of the output port 0, the test CPU 161 outputs
An address signal designating an address assigned to CSIO is output, and CSIO in a low active state is output.
Is set to low level, and the RD signal which is low active is set to low level. Then, a control signal for reading is output from the address decoder to the output port 0, so that the output state of the output port 0 is output from the output port 0 to the data bus.

The I / O expander has a chip select function for an external expansion device. That is, when the address decoder inputs the address signal to the external extension device, it sets the corresponding chip select signals CE0 to CE7 to low level.

FIGS. 21 to 26 are explanatory diagrams showing examples of the test signal terminals 121 to 126 on the symbol control board 80 shown in FIG. In this example, the test signal terminal 121
To 126 are each realized by a 68-pin connector.

Test signal terminal 121 and test signal terminal 1
Reference numeral 22 denotes a connector for outputting a test signal for a normal symbol. In the test signal terminal 121, the first pin is connected to P3 of the output port 3 of the I / O expander 120A.
From 0, a test signal is output. This test signal is usually a signal during symbol fluctuation. The fifth pin has an I / O expander 1
A test signal is output from P31 of the output port 3 of 20A. This test signal is usually a symbol confirmation signal. The ninth pin is connected to P3 of the output port 3 of the I / O expander 120A.
2 outputs a test signal. This test signal is a symbol display error signal. Test signals are output to the 17th and 18th pins from P33 and P34 of the output port 3 of the I / O expander 120A. These test signals are usually the first and second digit changing signals of the symbol.

In the test signal terminal 122, the first pin is connected to P35 of the output port 3 of the I / O expander 120A.
Outputs a test signal. This test signal is a symbol data signal of the first digit of the symbol. A test signal is output to the fifth pin from P36 of the output port 3 of the I / O expander 120A. This test signal is a symbol data signal of the second digit of the ordinary symbol.

Test signal terminal 123 and test signal terminal 1
Reference numeral 24 denotes a connector for outputting a test signal relating to a special symbol. In the test signal terminal 123, the first pin is connected to P0 of the output port 0 of the I / O expander 120A.
6 outputs a test signal. This test signal is a special symbol changing signal. The fifth pin has an I / O expander 1
A test signal is output from P07 of output port 0 of 20A. This test signal is a special symbol confirmation signal. The ninth pin is connected to P1 of the output port 1 of the I / O expander 120A.
6 outputs a test signal. This test signal is a variable display section error signal. Pins 17, 18, and 19 have I /
P17, P2 of output port 1 of O expander 120A
6, and a test signal is output from P27. These test signals are the changing signals of the first digit, the second digit and the third digit of the special symbol.

At the test signal terminal 124, the first to fifth
Test signals are output to the pins from P00 to P04 of the output port 0 of the I / O expander 120A. These test signals are data signals indicating the symbol type of the first digit of the special symbol. The ninth to thirteenth pins have an I / O expander 12
A test signal is output from P10 to P14 of the output port 1 of 0A. These test signals are data signals indicating the symbol type of the second digit of the special symbol. The 17th to 21st pins are connected to P20 to P20 of the output port 2 of the I / O expander 120A.
A test signal is output from P24. These test signals are data signals indicating the symbol type of the third digit of the special symbol.

Test signal terminal 125 and test signal terminal 1
Reference numeral 26 denotes a connector for outputting a test signal relating to the probability change notification. In the test signal terminal 125, the first pin is connected to P0 of the output port 0 of the I / O expander 120B.
From 0, a test signal is output. This test signal is a signal indicating that the notification means is changing, that is, a test signal indicating that a certainty change notification effect is being performed. A test signal is output to the fifth pin from P02 of the output port 0 of the I / O expander 120B. This test signal is a signal for notifying the notifying means, that is, a test signal indicating that a symbol for determining whether or not the probable change notification effect has been completed and whether or not to make a probable change is displayed. Thirteenth
A test signal is output to the pin from P04 of the output port 0 of the I / O expander 120B. This test signal is a special symbol probability change right signal, that is, a test signal indicating that the probable change is being performed. The 17th and 18th pins are connected to P05 and P06 of the output port 0 of the I / O expander 120B as a spare.

In the test signal terminal 126, the first to fourth
Test signals are output to the pins from P10 to P13 of the output port 1 of the I / O expander 120B. These test signals are test means data signals, that is, test signals indicating symbols as a result of the probable change notification effect. The ninth pin to the first pin
Pin 2 is connected to P14 to P17 of output port 1 of I / O expander 120B as a spare.

As shown in FIGS. 19 and 20, in this embodiment, an output port IC (I / O expander) is used to output a test signal from a signal generating means for generating a test signal. Since the I / O expander has a plurality of built-in I / O ports, the size of the test signal output circuit 120 that outputs the test signals does not increase even if there are many test signals. The I / O expander is an LSI, and its size is small. Then, even if a large number of test signals can be output, the substrate size does not increase so much and the cost does not increase much.

As shown in FIGS. 21 to 26, the test signal for the ordinary symbol and the test signal for the special symbol are:
Output from another output port. Specifically, the test signal for the normal symbol is the I / O expander 120A.
Is output from the output port 3. The test signals for the special symbols are output ports 0 to 0 of the I / O expander 120A.
2 output. In this way, if the output port is separated, it becomes easy to divide the test signal into a connector for a normal pattern and a connector for a special pattern, and as a result, a test signal and a special signal for the normal pattern can be obtained in the test apparatus. It is easy to input the test signal for the symbol separately.

FIG. 27 is a timing chart showing an example of the output timing of the test signal relating to the probability change notification. In this example, when the display control command relating to the probability change notification is received in the symbol control board 80, the fact is indicated by the display control C.
The PU 101 notifies the test CPU 161. In FIG. 27, STB is a strobe signal indicating that the display control command has been output to the signal line, and the display control CPU 101 introduces the strobe signal to the interrupt terminal, and the display control command is transmitted by the interrupt processing. Receive.
Further, in this embodiment, since the display control command has a 2-byte configuration, two STBs are actually output, but FIG. 27 shows only one STB. In this case, specifically, the display control command is a determination result designation (probable change) or a determination result designation (non-probable change). Also,
The example shown in FIG. 27 is an example in a case where a display control command for designating the determination result (probable change) is received.

Display Control CP on Symbol Control Board 80
U101 performs a probabilistic change notification effect by the probability fluctuation determination device in response to the display control command. In this embodiment,
The predetermined judgment symbol is changed for 22 s on the variable display section 9. This time is constant regardless of the result of the judgment symbol. By doing in this way, it becomes easy to calculate the average time displayed and displayed by the determination symbol during the game of a certain time, and it becomes easy to set the specifications of the gaming machine, thereby improving the development efficiency. During this time, the test CPU 161 turns on the determination device moving image changing signal (notifying device changing signal). When the display control CPU 101 completes the probable variation notification effect, the determination device determination signal (reporting device determination signal) is turned on for 50 ms, and displayed on the probability variation determination device (the variable display unit 9 in this example). Data indicating the fixed symbol is output as the determination device moving image data (determination unit data). Then, when the display control command for specifying the determination result (probable change) has been received, the special symbol probability change right signal is turned on.

As described above, the judgment device moving image changing signal, the judgment device decision signal, the special symbol probability change right signal, and the judgment device moving image data are output to the output port 0 or the output port 1 of the I / O expander 120B. ,further,
The test signal is output from the test signal terminals 125 and 126 to the outside of the gaming machine as a test signal. For example, when the test device is connected to a gaming machine, the test device receives each test signal.

FIG. 28 is a timing chart showing the state of the test signal when the probability change state ends when a big hit occurs next. As shown in FIG. 28, when a big hit occurs, a display control command indicating a symbol hit start display is transmitted from the main board 31 to the symbol control board 80, followed by a display control command indicating a symbol change stop. You. When the display control command indicating the big hit start display is received, the display control C
The PU 101 performs a big hit display on the special symbol display device (the variable display unit 9 in this example). At that timing, the test CPU 101 turns off the special symbol probability change right signal. FIG. 28 shows that a delay occurs from the start of the big hit display of the special symbol display device to the OFF state of the special symbol probability varying right signal due to a processing delay or the like.

FIG. 29 is a timing chart showing a state of the test signal when the certain symbol change is performed a predetermined number of times after the certain symbol change state is reached and the certain symbol change state ends. As shown in FIG. 29, from the main board 31 to the symbol control board 80,
When the display control command indicating the end of the probable change state is transmitted, the test CPU 101 recognizes the fact via the display control CPU 101 and turns off the special symbol probability change right signal. Here, a case where the end of the probable change state is notified by a display control command of low probability color designation is illustrated.

FIG. 30 is a timing chart for explaining the output timing of the special symbol change signal and the special symbol determination signal. When a big hit occurs, a big hit flag is set inside the game control means, and a big hit signal as a test signal is sent from the main board 31 to the test signal terminal 73, for example.
(See FIG. 5). The big hit flag is an internal flag for each processing routine in the game control means to recognize that a big hit has occurred. The big hit flag is determined by the game control process (step S1) shown in FIG.
1) Specifically, it is set in the special symbol process processing (step S25) shown in FIG. The big hit signal is output in the test signal output process (step S12) shown in FIG. At this time, a delay occurs from the point in time when the special symbol process processing is executed to the point in time when the test signal output processing is executed.

Since the big hit flag is set when the control for stopping the fluctuation of the special symbol is performed, at that time, the main board 31 and the symbol control board 8 are set.
A display control command for instructing 0 to stop the fluctuation has been sent. On the symbol control board 80, the display control C
When the PU 101 receives the display control command, the PU 101 notifies the test CPU 101 of the reception. Test CPU 10
1 turns off the special symbol changing signal in response to the notification, and turns on the symbol determination signal for a predetermined period.

Then, as shown by the broken line and A in FIG. 30, there is a possibility that the special symbol determination signal is turned on before the big hit signal is turned on. It is to be noted that the first digit symbol data to the third digit symbol data are output almost at the same time when the special symbol determination signal is turned on.

If the special symbol determination signal is turned on before the big hit signal is turned on, there is a possibility that inconsistency may occur in a test apparatus for introducing those signals. That is, when the first to third digit symbol data are the same data (that is, the big hit state), the special symbol determination signal is turned on in the test apparatus, so the first to third digit symbol data is set. Was confirmed to be the same data, but a situation may occur where the jackpot signal was not turned on.

In this embodiment, the test CPU 161
Delays the output timing of the special symbol changing signal and the special symbol determination signal to such an extent that the above situation does not occur. In the example shown in FIG. 30, the delay is 2 ms. That is,
In FIG. 30, when a big hit occurs as shown by B, when the special symbol determination signal is turned on,
It is controlled so that the big hit signal is always on.

That is, the test CPU 161 outputs the special symbol determination signal for a time equal to or longer than the time from when the CPU 56 of the main board 31 executes the display control command output processing relating to the fluctuation stop until the execution of the jackpot signal output processing. Delays turning on.

As described above, the test CPU 161 outputs the signal for confirming the display result of the special symbol indicating whether or not the game can be shifted to the jackpot game state which is advantageous to the player with a delay of a predetermined time. become. It should be noted that such delay control is not limited to a fixed signal relating to a special symbol,
Usually, it is also performed for a decision signal relating to a symbol.

Hereinafter, the control of the display control CPU 101 and the test CPU 161 for outputting each of the test signals described above will be described. As shown in FIG. 14, the display control CPU 101 executes an information output process (step S705).

In the information output process, the display control CPU
101 outputs, for example, a display control command received from the main board 31 to the test CPU 101, and also outputs various control timings and the like relating to the probability change notification to the test CPU 101.
Output to The control timings and the like related to the certainty variation notification include start / end timings of the certainty variation notification effect and a confirmed symbol. When an inappropriate display control command is received from the main board 31, such a command has been overwritten and erased in the reception buffer.
It is not output to the PU 101. Main board 31
The display control command received from the test CPU
161, the display control CPU 101
Does not require any special processing, so that the control load for outputting the test signal can be reduced.

Of course, the display control command from the main board 31 is not directly notified from the display control CPU 101 to the test CPU 101, but data determined in advance corresponding to the display control command is used for the test. You may output to CPU101.

Further, the information output processing is not particularly provided, and during the image control processing (step S704), the test CPU 101
May be notified of the test signal creation timing. For example, regarding the special symbol, in the special symbol display processing shown in FIG. 16, when it is confirmed that the display control command indicating the start of the fluctuation is received, the fact is notified to the test CPU 161 or the display control command indicating the stop of the fluctuation is displayed. After confirming that the
It may be notified to U161. Further, regarding the probability variation notification, in the probability variation notification symbol display process shown in FIG. 17, when the determination result designation command is received, the information indicating that the probability variation reporting effect is started is notified to the test CPU 161 or the display time is confirmed. Then, the test CPU 161 may be notified of information indicating that the probable change notification effect is to be ended.

FIG. 31 is a flowchart showing an example of the operation of the test CPU 161. Here, a case where a test signal relating to the special symbol shown in FIG. 30 is created will be described as an example. The test CPU 161 includes the display control CPU 101.
It is determined whether or not information regarding the start of fluctuation has been received from (step S201). If the signal has been received, after a delay time of 2 ms (step S202), the special symbol changing signal is set to a high level (ON state) (step S203).

If information about the left and right fixed symbols has been received from the display control CPU 101 (step S
204, S206, S208) The first digit, the second digit or the third digit of the symbol data is output (steps S205, S205).
207, S209).

It is confirmed whether or not information regarding the fluctuation stop has been received from the display control CPU 101 (step S21).
1). If it is received, after a delay time of 2 ms (step S212), the special symbol changing signal is set to low level (off state) (step S213), and the special symbol determination signal is set to high level (step S213). S
214).

Furthermore, it is confirmed whether or not information for canceling the symbol determination is received from the display control CPU 101 (step S215). If it has been received, the special symbol determination signal is set to low level (step S216). Note that the test CPU 161 may independently set the special symbol determination signal to a low level using a timer.

Further, it is determined whether or not error occurrence information of the variable display section has been received from the display control CPU 101 (step S217). If it has been received, the variable display section error signal is set to high level (step S218). And
It is confirmed whether or not error release information of the variable display unit has been received from the display control CPU 101 (step S219). If it has been received, the variable display unit error signal is set to low level (step S220).

As described above, the special symbol changing signal and the special symbol determination signal are output at the timing as shown in FIG. The test signal CPU 161
Are, as can be seen from FIGS. 23 and 24, the first to third digits.
When outputting the symbol data of the digit, the output ports 0 to 3 of the I / O expander 120A are selected to output the data. Also, when outputting the special symbol changing signal and the special symbol determination signal, the output port 0 of the I / O expander 120A is selected to output data. That is, the test signal CPU 161 selects a port that matches the output signal. This applies to other test signals.

In this embodiment, on the symbol control board 80, in addition to the display control CPU 101, the test CPU 1
61 is provided, and the test CPU 161
A test signal is created according to information from the PU 101. Therefore, even if a large number of test signals can be output to the outside of the gaming machine, the load on the display control CPU 101 does not increase. In addition, if the test signal is shared by each model, the test CPU 161 can be used in common by each model, and it is not necessary to develop a signal creation unit for creating a test signal. As a result, the development period of the gaming machine can be shortened.

In the above embodiment, the case where the test signal is output to the outside of the gaming machine has been described as an example. However, since the test signal is a signal indicating the control state of each electric component in the gaming machine, It can also be used for other applications. For example, the present invention can be applied to information output to a hall computer installed in a game arcade.

Further, in the above embodiment, the symbol control board 80 has been described as an example.
If a test microcomputer (signal generation microcomputer) is installed in addition to the electric component control microcomputer, it becomes easy to externally output information indicating the control state of the electric component from another electric component control board.

Furthermore, in another electric component control board,
If an I / O expander is installed, the size of the board does not increase and the cost of the board does not increase even when information indicating a large number of control states is externally output.

In the above embodiment, the test CPU 161 is provided on the symbol control board 80 so that the load on the display control CPU 101 is not increased. However, if the capacity of the display control CPU 101 is high, the display control CPU CPU
The 101 may perform the test signal output control. FIG.
It is a block diagram which shows the example of a structure of such a symbol control board 80. In this case, the display control CPU 101 executes the processing executed by the test CPU 161 described above.

Further, in the above embodiment, the I / O expander is applied to the case where the information indicating the control state of the electric component is externally output. However, the I / O expander is used for other signal output. You can also. FIG. 33 is a block diagram showing an example in which the I / O expander is applied to a control output from the CPU 56 of the main board 31.

In the example shown in FIG. 33, two I / O expanders 571 and 572 are used. The output port 573 is, for example, an 8-bit I / O port. The I / O expanders 571 and 572 and the output port 573 correspond to the output port portion of the I / O port 57 shown in FIG. 4 and the output port 570 shown in FIG.
Corresponding to

In the example shown in FIG. 33, the output port 0 of the I / O expander 571 is used to output an 8-bit display control command to the symbol control board 80. The output port 1 is used to output an 8-bit audio control command to the audio control board 70. The output port 2 is used to output an 8-bit lamp control command to the lamp control board 35. Output port 3
Is used to output an 8-bit payout control command to the payout control board 37.

The four bits at the output port 573 are used to output a strobe signal (STB signal) indicating that a display control command, a voice control command, a lamp control command, and a payout control command have been output.

Output port 0 of I / O expander 572 is used to output board side information. The board-side information is a signal output to the information terminal board via the information output circuit 64 shown in FIG. 4, and in addition to the signals shown in FIG. There are information, information common signal, and the like.

Output port 1 of I / O expander 572 is used to output a solenoid signal. In the example shown in FIG. 4, it is used to output signals to a solenoid 16 for opening and closing the variable winning ball device 15 and a solenoid 21 for opening and closing the special winning opening. If the game machine is provided with other solenoids, it is also used to output signals to those solenoids.

The output ports 2 and 3 of the I / O expander 572 are used for outputting a test signal, for example.

With the configuration as shown in FIG. 33, only three output port ICs are required, even though a large number of control signals are output from the main board 31 to each part of the gaming machine. That is, the size of the main substrate 31 can be reduced, and the cost of the main substrate 31 can be reduced. Although FIG. 33 shows the case where the I / O expander is applied to the main board 31, the I / O expander may be used in another electric component control board in the gaming machine.

The pachinko gaming machine 1 of each of the above embodiments
Is a first-class pachinko gaming machine in which a predetermined game value can be given to a player when a stop symbol of a special symbol variably displayed on the variable display portion 9 based on a start winning prize is a predetermined symbol combination. However, if there is a prize in a predetermined area of the electric accessory that is opened based on a winning start, a second-type pachinko gaming machine that can give a predetermined game value to a player, or is variably displayed based on a starting prize. The present invention can be applied to a third-type pachinko gaming machine in which a predetermined right is generated or continued when there is a prize for a predetermined electric accessory which is opened when a symbol combination of a predetermined symbol is released.

Further, the present invention is not limited to pachinko gaming machines, but can be applied to slot machines and the like in the case where an electric component control board for controlling an electric component performing some operation is provided. .

[0171]

As described above, according to the present invention, a game machine is controlled by an electric component control means for controlling an electric component provided in the game machine, and a test signal for enabling a control state of the electric component to be identified. , And an output port IC having a plurality of output ports for outputting the signals generated by the test signal generating means, thereby preventing the electric component control board from being enlarged. Thus, there is an effect that an environment in which a test relating to the game control operation can be performed more efficiently can be realized at low cost.

When the test signal generating means is configured to select an output port for outputting the generated test signal, the test signal for identifying the control state of the electric component is set to an appropriate port. Can be output via

The electric component is a display device. The electric component control means is a display control means for controlling the display device. The test signal generated by the test signal generation means determines whether or not the display control means performs variable display. In the case of including the signal indicating the above, it is possible to improve the test efficiency of a display device having many types of control states in the gaming machine.

The test signal created by the test signal creation means is
When the display device is configured to include a signal indicating the type of the display result, the display result of the display device can be easily recognized outside the gaming machine.

The display control means controls the display of the special symbol and the ordinary symbol, and the test signal generating means outputs the test signal for each of the special symbol and the ordinary symbol by different output ports. In this case, it is easy to connect the output terminal for the normal symbol and the output terminal for the special symbol separately. It becomes easy to identify.

If the electric component control means includes an electric component control microcomputer and the test signal generation means includes a test signal generation microcomputer different from the electric component control microcomputer, the test signal generation means may include a test signal generation microcomputer. Can be shared by all models, the microcomputer for test signal creation can be commonly used by each model.

A microcomputer for generating a test signal is
When the test signal generation processing is executed based on information output from the electric component control microcomputer, the test signal generation microcomputer easily generates the processing content of the electric component control microcomputer. It can be reflected in the test signal.

The electric component control microcomputer outputs a command from the game control means as information to the test signal generation microcomputer, and the test signal generation microcomputer outputs a command based on the command output from the electric component control microcomputer. When the configuration is such that the test signal generation processing is performed by the electronic component control microcomputer, the electric component control microcomputer does not need to perform any special processing when the test signal that can identify the control state of the electric component is generated. However, the load on the microcomputer for controlling the electric components does not increase.

[0179] The game control microcomputer can output a game state test signal for identifying that the state can be controlled to a game state advantageous to the player. In the case where the output timing of the test signal is adjusted so as not to cause inconsistency with the output timing of the game state test signal to be output, the test signal is generated in an inconsistent state. Can be prevented.

[0180] The game control microcomputer can output a game state test signal for identifying that the state can be controlled to a game state advantageous to the player, and the microcomputer for generating a test signal can be provided to the player. The output timing of the test signal is adjusted so that a determination signal of a display result that enables identification of whether or not the game state can be controlled to an advantageous game state is output after the game state test signal is output from the game control microcomputer. If configured for
It is prevented that a test signal is created in an inconsistent state with respect to occurrence of a state advantageous to the player such as a big hit.

A microcomputer for generating a test signal is
In the case where the game control microcomputer is configured to adjust the output timing of the test signal so as to delay the output time of the game state test signal by more than the time from executing the output process of the command until executing the output process of the game state test signal. This prevents a test signal in an inconsistent state from being created due to a difference in processing timing of the game control microcomputer.

[Brief description of the drawings]

FIG. 1 is a front view of a pachinko gaming machine viewed from the front.

FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine.

FIG. 3 is a rear view of the gaming board of the pachinko gaming machine as viewed from the rear.

FIG. 4 is a block diagram illustrating an example of a circuit configuration on a main board.

FIG. 5 is a block diagram showing a portion related to a test signal output of the main board.

FIG. 6 is a block diagram showing an example of a circuit configuration in a symbol control board.

FIG. 7 is a flowchart showing a main process executed by a CPU on a main board.

FIG. 8 is a flowchart showing a game control process.

FIG. 9 is a flowchart showing a special symbol process process.

FIG. 10 is a flowchart showing a normal symbol process process.

FIG. 11 is an explanatory diagram showing an example of the content of a display control command.

FIG. 12 is an explanatory diagram illustrating an example of a command form of a display control command.

FIG. 13 is a timing chart showing a relationship between a control signal and an INT signal.

FIG. 14 is a flowchart illustrating main processing executed by the display control CPU 101;

FIG. 15 is a flowchart illustrating a command receiving process.

FIG. 16 is a flowchart showing a special symbol display process.

FIG. 17 is a flowchart illustrating a probability change notification symbol display process.

FIG. 18 is a flowchart showing a normal symbol display process.

FIG. 19 is a block diagram illustrating a configuration example of a test signal output circuit in the symbol control board.

FIG. 20 is a block diagram illustrating an example of an I / O expander.

FIG. 21 is an explanatory diagram showing an example of a test signal terminal on the symbol control board.

FIG. 22 is an explanatory diagram showing an example of a test signal terminal on the symbol control board.

FIG. 23 is an explanatory diagram showing an example of a test signal terminal on the symbol control board.

FIG. 24 is an explanatory diagram showing an example of a test signal terminal on the symbol control board.

FIG. 25 is an explanatory diagram showing an example of a test signal terminal on the symbol control board.

FIG. 26 is an explanatory diagram illustrating an example of a test signal terminal on the symbol control board.

FIG. 27 is a timing chart showing an example of an output timing of a test signal relating to the probability change notification.

FIG. 28 is a timing chart showing a state of a test signal when a probability change state ends when a big hit occurs.

FIG. 29 is a timing chart showing a state of a test signal in a case where a probable change state ends when a special symbol is changed a predetermined number of times.

FIG. 30 is a timing chart for explaining output timings of a special symbol change signal and a special symbol determination signal.

FIG. 31 is a flowchart illustrating an example of the operation of the test CPU.

FIG. 32 is a block diagram showing another example of the circuit configuration in the symbol control board.

FIG. 33 is a block diagram illustrating an example in which an I / O expander is applied to a control output of a main board.

[Description of Signs] 9 Variable display unit 10 Normal symbol display 31 Game control board (main board) 56 CPU 71 Test signal output circuit 72, 73 Test signal terminal 80 Symbol control board 101 Display control CPU 120 Test signal output circuit 120A , 120B I / O expander 121-126 Test signal terminal 161 Test CPU

Claims (11)

[Claims] 1. A game machine in which a player can play a predetermined game, a game control means for controlling the progress of the game, and an electric component control means for controlling an electric component provided in the game machine. A test signal generating means for generating a test signal capable of identifying a control state of an electric component; and an output port IC having a plurality of output ports for outputting the test signal generated by the test signal generating means. A gaming machine comprising: 2. The gaming machine according to claim 1, wherein the test signal generating means selects an output port for outputting the generated test signal. 3. The electric component is a display device, the electric component control means is a display control means for controlling the display device, and the test signal generated by the test signal generation means is adapted to allow the display control means to display a variable display. 3. The gaming machine according to claim 1, further comprising a signal indicating whether or not the game is being performed. 4. The gaming machine according to claim 3, wherein the test signal generated by the test signal generating means includes a signal indicating a type of a display result on the display device. 5. The display control means performs display control of a special symbol used for displaying a big hit and a normal symbol used for displaying a small hit. 5. The gaming machine according to claim 3, wherein a test signal relating to each of the normal symbols is output with a different output port. 6. The electrical component control microcomputer includes an electrical component control microcomputer, and the test signal creating unit includes a test signal creating microcomputer different from the electrical component control microcomputer. Gaming machine. 7. The test signal generating microcomputer executes a test signal generating process based on information output from the electrical component control microcomputer.
The gaming machine described. 8. An electric component control means controls an electric component based on a command from the game control means, and an electric component control microcomputer outputs the command as information to a test signal generation microcomputer, 8. The gaming machine according to claim 7, wherein the signal creating microcomputer executes a test signal creating process based on the command output from the electrical component control microcomputer. 9. A game control microcomputer for controlling a game progress, wherein the game control microcomputer comprises:
It is possible to output a game state test signal that enables the player to identify a state that can be controlled to a game state that is advantageous to the player, and the test signal generating means outputs the game state test signal output from the game control microcomputer. 9. The gaming machine according to claim 1, wherein the output timing of the test signal is adjusted so that no conflict occurs with the timing. 10. A game control microcomputer for controlling the progress of a game, the game control microcomputer being capable of outputting a game state test signal for identifying that the state can be controlled to a game state advantageous to a player. The test signal creating microcomputer outputs a display result determination signal that enables identification of whether or not the game state can be controlled to a game state advantageous to the player, after the game state control signal is output from the game control microcomputer. The gaming machine according to claim 1, wherein an output timing of the test signal is adjusted so as to be output. 11. The microcomputer for generating a test signal is configured to delay the test signal so as to delay the time longer than the time from when the game control microcomputer executes the command output processing to when the game state test signal output processing is executed. The gaming machine according to claim 10, wherein the output timing is adjusted.