JP2001292039A - Front end distortion compensation circuit and power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a conventional front end distortion compensator circuit that cannot cancel an intermodulation distortion component generated by an amplifier. SOLUTION: This front end distortion compensator circuit is provided with an input terminal 101 that receives a prescribed signal, a diode 106 as a nonlinear element connected directly to the input terminal 101, a bias supply circuit consisting of a resistor 104, a power terminal 103 and a capacitor 105 to apply a voltage to the diode 106, specific frequency suppression means 108, 109 that are directly connected across the diode 106 not through any other element and suppress part of or all frequencies from a frequency equivalent to DC up to a frequency equivalent to an occupied bandwidth of the input signal received at the input terminal 101 and/or at least one harmonic frequency of the carrier of the input signal and an output terminal 102 that outputs a signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In an amplifier, there is a problem of occurrence of intermodulation distortion caused by amplitude / phase distortion between input and output. The present invention relates to a distortion compensation circuit for suppressing the occurrence of such intermodulation distortion.

[0002]

2. Description of the Related Art As a distortion compensation method for suppressing the occurrence of intermodulation distortion by compensating for amplitude / phase distortion between an input and an output of an amplifier, there is a predistortion compensation system. FIG. 5 is a diagram showing the configuration and principle of the predistortion compensation system. First, the configuration of the predistortion compensation system in FIG. It is assumed that the input signal is composed of signals having two different frequency components.

[0003] A signal is input from an input terminal 501 and input to a distortion generating circuit (distortion compensating circuit) 502 using diodes, transistors, and the like. The signal passes through the distortion generating circuit 502 and is output in a state where intermodulation distortion having an amplitude / phase relationship that cancels out the intermodulation distortion component generated in the amplifier 503 provided later is input to the amplifier 503. Is done.

FIGS. 5B and 5C show the relationship between the input signal and the spectrum of the intermodulation distortion component of the distortion generation circuit 502 and the spectrum of the intermodulation distortion component of the amplifier 503, respectively. The input signal spectrum is an input signal spectrum of the distortion generating circuit 502, and includes two basic signal frequencies f1 and f2 shown in FIG. Note that the frequency f1 in FIG.
Although the magnitude of the amplitude at f2 is described as being the same as the magnitude of the amplitude at the corresponding frequency in FIG. 5B, the magnitude of the amplitude is assumed to be the same for convenience of explanation, and the amplitude is actually increased. Have been.

An amplifier 503 output to an output terminal 504
As shown in FIG. 5 (c), in addition to the fundamental signal frequencies f1 and f2, the output signal spectrum of FIG. 5 shows a third-order intermodulation distortion component having a frequency of 2f1-f2, 2f2-f1, and a distortion generated by the amplifier 503. A third-order intermodulation distortion component having a frequency of 2f1-f2 or 2f2-f1 generated by the generation circuit 502 and a frequency of 3f1-2 generated by the amplifier 503.
The fifth-order intermodulation distortion components of f2, 3f2-2f1, and the frequencies 3f1-2f2, 3f generated by the distortion generation circuit 502
A fifth-order intermodulation distortion component of 2-2f1 exists.

[0006] As shown in FIG.
If an intermodulation distortion component that cancels out the intermodulation distortion component generated by the amplifier 503 is generated in advance in 2, an output signal without distortion is obtained at the output terminal 504.

[0007]

However, for example, since the conventional distortion generating circuit 502 is the predistortion compensating circuit shown in FIG. 9, the distortion generating circuit 502 generates the input signal as shown in FIG. The difference frequency (f2-f1), its harmonic 2 (f2-f1), and the signal components 2f1, 2f2, (f1 +
f2) and the like occur.

[0008] Those (f2-f1), 2 (f2-f
1) 2f1, 2f2, (f1 + f2) signal components,
Since the basic signal frequencies f1 and f2 affect each other,
Even if the amplitude of the input signal or the magnitude of the voltage applied to the circuit is changed, 2f1-f2, 2f2-f1, 3f1-2f
For each of the frequencies 2 and 3f2-2f1, the amplitude of the signal component generated by the distortion generation circuit 502 and the amplifier 503
Could not be substantially matched with the amplitude of the signal component generated in step (1). FIG. 10 shows (f2-f1), 2
The signal components output from the distortion generating circuit 502 after the signal components (f2−f1), 2f1, 2f2, and (f1 + f2) and the basic signal frequencies f1 and f2 influence each other.

Here, FIG. 6A shows, among the signals output from the amplifier 503, the basic signal frequencies f1 and f2, and
An example is shown of a third-order intermodulation distortion component of frequencies 2f1-f2, 2f2-f1, and a fifth-order intermodulation distortion component of frequencies 3f1-2f2, 3f2-2f1.

As shown in FIG. 6A, the frequency 2f1-
the magnitude of the amplitude of the signal component generated by the distortion generating circuit 502 in the third-order intermodulation distortion component of f2, 2f2-f1,
The magnitude of the amplitude of the signal component generated by the amplifier 503 is different, and similarly, the frequencies 3f1-2f2, 3f2-2f1
Since the magnitude of the amplitude of the signal component generated by the distortion generation circuit 502 in the fifth-order intermodulation distortion component of FIG.
As shown in (b), the signal actually output from the amplifier 503 has third-order intermodulation distortion components of frequencies 2f1-f2 and 2f2-f1, and similarly, 5th-frequency components of frequencies 3f1-2f2 and 3f2-2f1. There is a disadvantage that the secondary intermodulation distortion component remains and distortion suppression is not sufficiently performed.

The magnitude of the amplitude at the frequencies f1 and f2 in FIG. 6B is described as being the same as the magnitude of the amplitude at the corresponding frequency in FIG. 6A.
For convenience of explanation, the magnitudes of the amplitudes are the same, and the amplitude is actually amplified.

The present invention has been made to solve such a problem, and provides a predistortion compensation circuit for generating an intermodulation distortion component capable of substantially canceling out an intermodulation distortion component generated in an amplifier. It is intended to do so.

[0013]

In order to solve this problem, a first aspect of the present invention (corresponding to claim 1) is to provide an input terminal for inputting a predetermined signal and a direct or indirect connection with the input terminal. A nonlinear element, a bias supply circuit for applying a voltage to the nonlinear element, directly connected to one or both sides of the nonlinear element without passing through another element, from a frequency corresponding to DC, Specific frequency suppressing means for suppressing all or a part of the frequency up to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal, and / or the frequency of at least one harmonic of the carrier of the input signal; A predistortion compensating circuit including an output terminal for outputting a signal.

A second aspect of the present invention (corresponding to claim 2) is that all or some of the frequencies from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth and / or the carrier of the input signal In at least one of the harmonics, the impedance seen from the connection point where the specific frequency suppression means is connected to the specific frequency suppression means, the impedance value that is lower than the impedance seen from the connection point to the nonlinear element, The predistortion compensation circuit according to the first aspect of the present invention included in the specific frequency suppression means.

A third aspect of the present invention (corresponding to claim 3) is that the nonlinear element is provided between a connection point between the input terminal and the output terminal and a ground. 4 is a predistortion compensation circuit according to the present invention.

According to a fourth aspect of the present invention (corresponding to claim 4), the non-linear element is connected between the input terminal and the output terminal. This is a distortion compensation circuit.

According to a fifth aspect of the present invention (corresponding to claim 5), the non-linear element is a transistor, the input terminal is connected to one of a drain and a source of the transistor, and the output terminal is connected to a drain and a drain of the transistor. A first or a second source connected to the other of the sources, wherein the bias supply circuit is connected to the gate of the transistor;
Is a predistortion compensation circuit according to the present invention.

According to a sixth aspect of the present invention (corresponding to claim 6), any one of the first to fifth aspects, wherein the specific frequency suppressing means is composed of all or a part of a resistor, a coil, a capacitor, and a transmission line. Such a predistortion compensation circuit according to the present invention.

A seventh aspect of the present invention (corresponding to claim 7) is the predistortion compensation circuit according to any one of the first to fourth aspects of the present invention, wherein the non-linear element is constituted by a diode.

An eighth aspect of the present invention (corresponding to claim 8) is the predistortion compensation circuit according to any one of the first to fourth aspects of the present invention, wherein the non-linear element is constituted by a transistor.

As described above, the pre-distortion compensating circuit of the present invention operates in all or a part of the frequency range from the frequency corresponding to DC to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal. And / or connecting a specific frequency suppressing means for suppressing the frequency of at least one harmonic of the carrier of the input signal to at least one of the input and the output of the nonlinear element, so that the occupied band is reduced from the frequency corresponding to the direct current. Unnecessary distortion components due to distortion occurring at all or some frequencies up to the frequency corresponding to the width and / or at least one harmonic of the carrier of the input signal can be removed.

By doing so, the frequency becomes 2f1-f2
And the magnitude of the amplitude of the third-order intermodulation distortion component generated at 2f2-f1 is different, and the frequencies are 3f1-2f2 and 3f2.
The phenomenon that the magnitude of the amplitude of the fifth-order intermodulation distortion component generated at −2f1 differs is alleviated, and a sufficient distortion suppression amount can be obtained.

According to a ninth aspect of the present invention (corresponding to claim 9), the first aspect
To a power amplifying apparatus comprising: the predistortion compensation circuit according to any one of the first to eighth aspects of the present invention; and an amplifier for amplifying a signal from the predistortion compensation circuit.

A tenth aspect of the present invention (corresponding to claim 10) is:
The amplifier includes an input terminal for inputting a signal, a first matching circuit connected to the input terminal, a transistor having a gate connected to the first matching circuit, and a drain connected to the transistor. A second matching circuit, an output terminal connected to the second matching circuit for outputting a signal, and a first bias circuit connected between the first matching circuit and the transistor. And a second bias circuit connected between the second matching circuit and the transistor, and directly connected to one or both sides of the transistor without any other element, and from a frequency corresponding to DC,
All or some frequencies up to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal, and / or
Alternatively, the power amplifier according to the ninth aspect of the present invention includes a specific frequency suppressing unit configured to suppress a frequency of at least one harmonic of a carrier of the input signal.

According to an eleventh aspect of the present invention (corresponding to claim 11),
The amplifier has an input terminal for inputting a signal, a first matching circuit connected to the input terminal, a transistor connected to the base of the first matching circuit, and a collector connected to the transistor. A second matching circuit, an output terminal connected to the second matching circuit for outputting a signal, and a first bias circuit connected between the first matching circuit and the transistor. And a second bias circuit connected between the second matching circuit and the transistor, and directly connected to one or both sides of the transistor without any other element, and from a frequency corresponding to DC,
All or some frequencies up to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal, and / or
Alternatively, the power amplifier according to the ninth aspect of the present invention includes a specific frequency suppressing unit configured to suppress a frequency of at least one harmonic of a carrier of the input signal.

[0026]

Embodiments of the present invention will be described below.

(Embodiment 1) A predistortion compensation circuit according to Embodiment 1 of the present invention will be described below with reference to FIG. FIG. 1A is a configuration diagram of a predistortion compensation circuit according to Embodiment 1 of the present invention. As shown in FIG. 1A, a connection point 110 between the diode 106 and the output terminal 102 has a frequency ranging from a frequency corresponding to DC to a frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 101. At all or a part of the frequency, a specific frequency suppressing means 109 having an impedance lower than the input impedance of the diode 106 is added, and a connection point 111 between the diode 106 and the resistor 107 is shifted from the frequency corresponding to the DC to the occupied band. The specific frequency suppressing means 10 having an impedance lower than the output impedance of the diode 106 at all or a part of the frequency up to the frequency corresponding to the width.
8 is added.

Alternatively, the diode 106 and the output terminal 10
2, a specific frequency suppressing means 109 having an impedance lower than the input impedance of the diode 106 at a frequency twice as high as the carrier of the input signal.
May be added to a connection point 111 between the diode 106 and the resistor 107 at a frequency twice as high as the carrier of the input signal and a specific frequency suppressing means 108 having an impedance lower than the output impedance of the diode 106.

Alternatively, the diode 106 and the output terminal 10
2 at the connection point 110 between
Specific frequency suppressing means 109 having an impedance lower than the input impedance of diode 106 at all or a part of the frequency up to the frequency corresponding to the occupied bandwidth of the input signal input to input terminal 101, and at twice the frequency of the carrier wave. And a diode 106 and a resistor 1
07, at all or a part of the frequency of the input signal from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth, and at twice the frequency of the carrier, the output impedance of the diode 106 Specific frequency suppressing means 108 having low impedance may be added.

The specific frequency suppressing means 108, 109
May be connected to the diode 106 only.

In the first embodiment of the present invention, specific frequency suppressing means 108 and 109 are used as an example of the specific frequency suppressing means of the predistortion compensation circuit of the present invention.
Reference numerals 8 and 109 denote signal components (f2-f1) of the frequency of the difference between the input signals and signal components 2 (f
2-f1), and signal components 2f1, 2f2, (f1 + f2) of at least one harmonic of the carrier of the input signal.

FIG. 1B shows a specific frequency suppressing means 10.
FIG. 8 is a diagram illustrating an example in which lumped elements 8 and 109 are configured using lumped constant elements, and is an LC series resonance circuit in which a coil 113 and a capacitor 114 are connected in series. The connection terminal 112 is connected to the connection points 110 and 111, and the resonance frequency of the LC series resonance circuit is all or from the frequency corresponding to DC to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 101. Coil 1 corresponds to some frequencies
13 and the capacitor 114 are selected.
The element values of the coil 113 and the capacitor 114 may be selected so that the resonance frequency of the C series resonance circuit corresponds to twice the frequency of the carrier of the input signal.

FIG. 1C shows a specific frequency suppressing means 10.
FIG. 8 is a diagram showing an example in which 8, 109 are configured using transmission lines.
This is an open stub using the λ / 8 line 116. If the connection terminal 115 is connected to the connection points 110 and 111 and the line length of the λ / 8 line 116 is designed on the assumption that the wavelength λ is one wavelength of the carrier wave, the impedance becomes low with respect to 2f1, 2f2 and f1 + f2, and these signals become low. Can be suppressed.

FIG. 1D shows a specific frequency suppressing means 10.
8 and 109 are diagrams showing examples in which a transmission line and a capacitor are used, and a λ / 4 line 118 and a capacitor 1 are shown.
19 is a stub matching circuit in which 19 are connected in series. The connection terminal 117 is connected to the connection points 110 and 111, the line length of the λ / 4 line 118 is designed on the assumption that the wavelength λ is one wavelength of the carrier wave, and the input inputted to the input terminal 101 from the frequency corresponding to DC. A capacitor 119 whose impedance is sufficiently low at all or a part of the frequency up to the frequency corresponding to the occupied bandwidth of the signal may be connected, or the λ / 4 line 118 may have an impedance at twice the frequency of the carrier of the input signal. May be connected to a capacitor 119 having a sufficiently low impedance. Furthermore, λ /
The impedance of the four lines 118 is sufficiently low at all or some frequencies from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 101, and at twice the frequency of the carrier. It is also possible to connect a capacitor 119 serving as an impedance. In this way, in FIG.
From the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 101 at all or a part of the frequency and twice the frequency of the carrier. Make it lower than the input (output) impedance.

In this manner, all or a part of the frequency from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 101, or the frequency twice the carrier wave, etc. By preventing unnecessary distortion components due to the generated distortion from being generated in the predistortion compensation circuit, the amplitudes of the intermodulation distortion components of the same order are substantially matched in the predistortion compensation circuit. be able to.

The frequencies f1 and f2 taken up in FIGS. 5 and 6
More specifically, the specific frequency suppressing means 108 and 109 output signals having frequencies f2-f1, 2f1,.
At 2f2, since the impedance is lower than the input impedance or output impedance of the diode 106, all or some of the frequencies from the frequency corresponding to DC to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 101 Unnecessary distortion components due to distortion generated at twice the frequency of the carrier of the input signal are removed, and signals of frequencies f2-f1, 2f1, and 2f2 generated by the predistortion compensation circuit according to the present embodiment. Becomes smaller. Therefore, the amplitude of the signal input to the input terminal 101 and / or the voltage applied to the power supply terminal 103 are applied so that the distortion component having the same amplitude as the amplitude of the distortion component generated in the amplifier to be subjected to distortion compensation is output to the output terminal 102. By setting the voltage to be applied, the frequencies 2f2-f1, 2f1
The amplitude of the signal at -f2 becomes substantially equal.

In the first embodiment, in the predistortion compensating circuit of the present invention, the diode 106 is used as an example of the nonlinear element, and the resistor 10 is used as an example of the bias supply circuit.
4. The power supply terminal 103 and the capacitor 105 are provided as specific frequency suppressing means as specific frequency suppressing means 108,
109 was used for each.

Further, as the specific frequency suppressing means 108, 109 in the above-described first embodiment, a means composed of all or a part of a resistor, a coil, a capacitor, and a transmission line can be used.

In the first embodiment, means having a lower impedance than the output impedance or the input impedance of the diode 106 at twice the frequency of the carrier of the input signal is used as the specific frequency suppressing means 108 and 109. However, as the specific frequency suppressing means 108 and 109, means having a lower impedance than the output impedance or the input impedance of the diode 106 at a frequency that is an integral multiple of twice the carrier of the input signal can be used.

The specific frequency suppressing means 10 shown in FIG.
As means 8, means for suppressing the signal component (f2-f1) of the difference frequency of the input signal shown in FIG. 10 and its harmonic 2 (f2-f1) may be used, or at least one of the carrier waves of the input signal may be used. Signal components 2f1, 2f2, (f1
+ F2) may be used. Similarly, as the specific frequency suppressing means 109, the signal component (f2-f1) of the frequency of the difference between the input signals and its harmonic 2 (f2-f)
Means for suppressing 1) may be used, or signal components 2f1, 2f of at least one harmonic of the carrier of the input signal.
2, means for suppressing (f1 + f2) may be used.

Further, as shown in FIG.
Between the input terminal and the output terminal 102, the signal component (f2-f1) of the difference frequency of the input signal and its harmonic 2 (f2-f1)
Frequency suppression means 108a for suppressing signal components 2f1 and 2f2 of at least one harmonic of the carrier of the input signal.
Specific frequency suppressing means 1 for suppressing f2, (f1 + f2)
09a, and a signal component (f) having a frequency of the difference between the input signals between the diode 106 and the resistor 107.
2-f1) and its specific harmonic 2 (f2-f1), and a specific frequency suppressing means 108b, and signal components 2f1, 2f2, (f) of at least one harmonic of the carrier of the input signal.
1 + f2) may be provided.

The specific frequency suppressing means 108a and the specific frequency suppressing means 109a may be provided, and the specific frequency suppressing means 108b and the specific frequency suppressing means 109b may not be provided, or the specific frequency suppressing means 108b and the specific frequency suppressing means may be omitted. It is not necessary to provide the specific frequency suppressing means 108a and the specific frequency suppressing means 109a. In short, one or both sides of the nonlinear element are directly connected without any other element, and all or a part of the frequency from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 101 is input. It is only necessary to provide a specific frequency suppressing means for suppressing the frequency and / or the frequency of at least one harmonic of the carrier of the input signal.

Although the description has been made using two waves having different frequencies as the input signal, the same effect can be obtained with a modulated wave.

Further, in the above-described first embodiment, the resistor 104, the electrode terminal 103 and the capacitor 105 are used as an example of the bias supply circuit of the predistortion compensation circuit of the present invention. It may be replaced.
In this case, the bias supply circuit functions as a specific frequency suppressing unit.

(Embodiment 2) Hereinafter, Embodiment 2 of the present invention will be described with reference to FIG. FIG. 2A is a configuration diagram of a predistortion compensation circuit according to Embodiment 2 of the present invention.
As shown in FIG. 2A, a connection point 211 between the diode 206 and the output terminal 202 has a frequency ranging from a frequency corresponding to DC to a frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 201. At all or a part of the frequency, a specific frequency suppressing means 209 having an impedance lower than the output impedance of the diode 206 is added, and a connection point 210 between the diode 206 and the resistor 204 is added.
In particular, at all or some frequencies from a frequency corresponding to direct current to a frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 201, the specific frequency suppressing means has a lower impedance than the input impedance of the diode 206. 208 is added.

Alternatively, the diode 206 and the output terminal 20
2, a specific frequency suppressing means 209 having an impedance lower than the output impedance of the diode 206 at twice the frequency of the carrier of the input signal is added to the connection point 211 between the diode 206 and the resistor 204.
A specific frequency suppressing means 208 having an impedance lower than the input impedance of the diode 206 at twice the frequency of the carrier of the input signal may be added to 10.

Alternatively, the diode 206 and the output terminal 20
The connection point 211 between the two, from the frequency corresponding to DC,
Specific frequency suppressing means 209 having an impedance lower than the output impedance of diode 2067 at all or some frequencies up to the frequency corresponding to the occupied bandwidth of the input signal input to input terminal 201, and at twice the frequency of the carrier wave. At the connection point 210 between the diode 206 and the resistor 204, all or some of the frequencies from the frequency corresponding to DC to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 201, And at twice the frequency of the carrier, diode 206
The specific frequency suppressing means 208 having an impedance lower than the input impedance of the input signal may be added.

The specific frequency suppressing means 208, 209
May be connected to only one of them.

Also, in the second embodiment of the present invention, the specific frequency suppressing means 208 and 209 are used as an example of the specific frequency suppressing means of the predistortion compensating circuit of the present invention. 10, the signal component (f2-f1) of the difference frequency of the input signal and its harmonic 2 (f2-f1), the signal component 2f1, 2f2 of at least one harmonic of the carrier of the input signal, and the like are shown in FIG. (F1 + f
2) It is a means to suppress the above.

FIG. 2B shows the specific frequency suppressing means 20.
FIG. 8 is a diagram showing an example in which lumped elements 8 and 209 are configured using lumped constant elements, and is an LC series resonance circuit in which a coil 213 and a capacitor 214 are connected in series. The connection terminal 212 is connected to the connection points 210 and 211, and the resonance frequency of the LC series resonance circuit is all or from the frequency corresponding to DC to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 201. To correspond to some frequencies, coil 2
13 and the capacitor 214 are selected.
The element values of the coil 213 and the capacitor 214 may be selected so that the resonance frequency of the C series resonance circuit corresponds to twice the frequency of the carrier of the input signal.

FIG. 2C shows the specific frequency suppressing means 20.
FIG. 8 is a diagram showing an example in which the transmission lines 8 and 209 are configured using transmission lines.
This is an open stub using the λ / 8 line 216. If the connection terminal 215 is connected to the connection points 210 and 211 and the wavelength λ is one wavelength of the carrier wave and the line length of the λ / 8 line 216 is designed, the impedance becomes low with respect to 2f1, 2f2 and f1 + f2, and these signals become Can be suppressed.

FIG. 2D shows the specific frequency suppressing means 20.
8 and 209 show an example in which a transmission line and a capacitor are used.
19 is a stub matching circuit in which 19 are connected in series. The connection terminal 217 is connected to the connection points 210 and 211, the line length of the λ / 4 line 218 is designed on the assumption that the wavelength λ is one wavelength of the carrier wave, and the input that is input to the input terminal 201 from the frequency corresponding to DC. A capacitor 219 whose impedance is sufficiently low at all or a part of the frequency up to the frequency corresponding to the occupied bandwidth of the signal may be connected, or the impedance may be connected to the λ / 4 line 218 at twice the frequency of the carrier of the input signal. What is necessary is just to connect the capacitor 219 which becomes a sufficiently low impedance. Furthermore, λ / 4
The line 218 is connected to the input terminal 2 from the frequency corresponding to DC.
01 or all of the frequencies up to the frequency corresponding to the occupied bandwidth of the input signal input to the input signal 01 and the carrier 2
It is also possible to connect a capacitor 219 whose impedance is sufficiently low at twice the frequency. In this way, in FIG. 2D, the impedance viewed from the terminal 217 is changed from the frequency corresponding to DC to
At all or some frequencies up to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 201, and at twice the frequency of the carrier, the input (output) impedance of the diode 206 is made lower.

In this way, all or some of the frequencies from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 201, or the frequency twice the carrier wave are generated. By preventing unnecessary distortion components due to distortion from being generated in the pre-distortion compensation circuit, the pre-distortion compensation circuit has the same amplitude as the amplitude of the distortion component generated in the amplifier to be subjected to distortion compensation. If the amplitude of the signal input to the input terminal 201 and / or the voltage applied to the power supply terminal 203 is set so that the distortion component is output to the output terminal 202, the amplitude of the intermodulation distortion component of the same order is substantially reduced. Can be matched up.

In the above-described second embodiment, in the predistortion compensating circuit of the present invention, the diode 206 is used as an example of the nonlinear element, and the resistor 20 is used as an example of the bias supply circuit.
4. The power supply terminal 203 and the capacitor 205 are provided as specific frequency suppressing means as specific frequency suppressing means 208,
209 were used.

In the above-described second embodiment, a conversion circuit having a lower impedance than the output impedance or the input impedance of the diode 206 at twice the frequency of the carrier of the input signal is used as the specific frequency suppressing means 208 and 209. However, as the specific frequency suppressing means 208 and 209, the diode 20 is used at a frequency that is an integral multiple of twice the carrier of the input signal.
6, a conversion circuit having a lower impedance than the output impedance or the input impedance can be used.

Although the above description has been made using two waves having different frequencies as the input signal, the same effect can be obtained with a modulated wave.

(Embodiment 3) Hereinafter, Embodiment 3 of the present invention will be described with reference to FIG. FIG. 3A is a configuration diagram of a predistortion compensation circuit according to Embodiment 3 of the present invention.
As shown in FIG. 3A, a connection point 313 between the transistor 305 and the output terminal 302 has a frequency ranging from a frequency corresponding to DC to a frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 301. At all or a part of the frequency, a specific frequency suppressing means 311 having an impedance lower than the output impedance of the transistor 305 is added, and a connection point 314 between the transistor 305 and the input terminal 301 is shifted from the frequency corresponding to DC to the input terminal. 30
A specific frequency suppressing unit 310 having an impedance lower than the input impedance of the transistor 305 at all or a part of the frequency up to the frequency corresponding to the occupied bandwidth of the input signal input to 1 is added.

Alternatively, the transistor 305 and the output terminal 3
02 at the connection point 313 between the specific frequency suppressing means 31 having a lower impedance than the output impedance of the transistor 305 at twice the frequency of the carrier of the input signal.
1 may be added to the connection point 314 between the transistor 305 and the input terminal 301 at a frequency twice as high as the carrier of the input signal and a specific frequency suppressing means 310 having an impedance lower than the input impedance of the transistor 305. .

Alternatively, the transistor 305 and the output terminal 3
02, at all or some frequencies from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 301, and at twice the frequency of the carrier. , Transistor 30
5 is added with a specific frequency suppressing unit 311 having an impedance lower than the output impedance of the transistor 305.
At a connection point 314 between the input terminal 301 and all or part of the frequency from a frequency corresponding to DC to a frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 301, and twice the carrier. At this frequency, a specific frequency suppressing unit 310 having an impedance lower than the input impedance of the transistor 305 may be added.

The specific frequency suppressing means 310, 311
May be connected to only the transistor 305. The resistor 306 connected to the connection point 312 and the connection point 315 may be a coil or a capacitor, or a passive circuit including a resistor, a coil, and a capacitor.

In the third embodiment of the present invention, the specific frequency suppressing means 310 and 311 are used as an example of the specific frequency suppressing means of the predistortion compensation circuit of the present invention. 10, the signal component (f2-f1) of the difference frequency of the input signal and its harmonic 2 (f2-f1), the signal component 2f1, 2f2 of at least one harmonic of the carrier of the input signal, and the like are shown in FIG. (F1 + f
2) It is a means to suppress the above.

FIG. 3B shows the specific frequency suppressing means 31.
FIG. 2 is a diagram showing an example in which 0 and 311 are configured using lumped constant elements, and is an LC series resonance circuit in which a coil 316 and a capacitor 317 are connected in series. The connection terminal 315 is connected to the connection points 313 and 314, and the resonance frequency of the LC series resonance circuit is all or from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 301. To correspond to some frequencies, the coil 3
16 and the capacitor 317,
The element values of the coil 316 and the capacitor 317 may be selected so that the resonance frequency of the C series resonance circuit corresponds to twice the frequency of the carrier of the input signal.

FIG. 3C shows the specific frequency suppressing means 31.
FIG. 3 is a diagram illustrating an example in which 0 and 311 are configured using transmission lines.
This is an open stub using the λ / 8 line 319. The connection terminal 318 is connected to the connection points 313 and 314, and the λ / 8 line 3
If the line length is designed to correspond to λ / 8 at the fundamental frequency of the input signal, 2f1, 2f2, f1 + f2
And these signals can be suppressed.

FIG. 3D shows the specific frequency suppressing means 31.
FIG. 3 is a diagram showing an example in which 0, 311 are configured using a transmission line and a capacitor.
22 is a stub matching circuit in which 22 are connected in series. The connection terminal 320 is connected to the connection points 313 and 314, and the line length is designed to correspond to λ / 4 at the fundamental frequency of the input signal. A capacitor 322 that has low impedance at all or a part of the frequency up to the frequency corresponding to the occupied bandwidth of the input signal to be input may be connected, or the λ / 4 line 321 may be connected at twice the frequency of the carrier of the input signal. Low impedance capacitor 32
2 may be connected. Further, the λ / 4 line 321 has a low frequency at all or some frequencies from a frequency corresponding to DC to a frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 301 and at a frequency twice as high as the carrier. It is also possible to connect a capacitor 322 serving as an impedance. In short, the λ / 4 line 321 and the capacitor 3
It is sufficient that the overall impedance of the transistor 22 is smaller than the impedance of the transistor 305.

In this way, all or some of the frequencies from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal 301 or the frequency twice the carrier wave are generated. By preventing unnecessary distortion components due to distortion from being generated in the pre-distortion compensation circuit, the pre-distortion compensation circuit has the same amplitude as the amplitude of the distortion component generated in the amplifier to be subjected to distortion compensation. If the amplitude of the signal input to the input terminal 301 and / or the voltage applied to the power supply terminal 303 is set so that the distortion component is output to the output terminal 302, the magnitude of the amplitude of the intermodulation distortion component of the same order is substantially reduced. Can be matched up.

In the third embodiment described above, the transistor 305 as an example of a non-linear element and the resistor 30 as an example of a bias supply circuit in the predistortion compensation circuit of the present invention.
8. The power supply terminal 303 and the capacitor 309 are provided as specific frequency suppressing means as specific frequency suppressing means 310 and 31.
1 was used for each.

The connection points 313 and 314 in FIG.
Are connected to the connection point 330 between the gate of the transistor 305 and the resistor 308, the signal is input to the input terminal 301 from the frequency corresponding to DC. And / or at least one harmonic up to a frequency corresponding to the occupied bandwidth of the input signal and / or at least one harmonic of the carrier of the input signal.

Although the above description has been made using two waves having different frequencies as the input signal, the same effect can be obtained with a modulated wave.

Hereinafter, specific examples of the pre-distortion compensating circuit according to the embodiment of the present invention using a diode as a non-linear element other than the above-described first to third embodiments will be described with reference to FIGS. explain.

FIG. 4 shows an example in which lumped constant elements 410 and 412 such as resistors, coils and capacitors are connected to the anode and cathode of the diode 411. The lumped constant elements 410 and 412 such as a resistor, a coil, and a capacitor
It may be a passive circuit including lumped constant elements such as a resistor, a coil, and a capacitor.

FIG. 7 shows an example in which lumped constant elements 423 and 425 such as resistors, coils, and capacitors are connected to the anode and cathode of the diode 424. Note that lumped constant elements 423 and 425 such as a resistor, a coil, and a capacitor
It may be a passive circuit including lumped constant elements such as a resistor, a coil, and a capacitor.

FIG. 8 shows two diodes 437 and 440.
2 is an example of a circuit configuration combining. In addition, it is also possible to combine two or more diodes.

In each of the predistortion compensating circuits shown in FIGS. 4, 7 and 8, the specific frequency suppressing means composed of the λ / 4 line and the capacitor has a lower impedance than the input impedance or the output impedance of the diode. In each of the predistortion compensating circuits, the amplitudes of the same-order intermodulation distortion components can be made substantially equal.

A power amplifier including the predistortion compensating circuit described in each of the above embodiments and an amplifier for amplifying a signal from the predistortion compensating circuit also belongs to the present invention. As an example of the amplifier, the amplifier shown in FIG.

The amplifier shown in FIG. 12 has an input terminal 1301 for inputting a signal, a first matching circuit 1302 connected to the input terminal 1301, and a first matching circuit 13
02, a transistor 1303 whose gate is connected,
A second matching circuit 1304 connected to the drain of the transistor 1303;
And an output terminal 1305 for outputting a signal;
A first bias circuit 1306 connected between the first matching circuit 1302 and the transistor 1303;
And / or all frequencies from the frequency corresponding to DC to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal, and / or connected between the bias circuit 1306 and the transistor 1303. A first specific frequency suppressing unit 1307 for suppressing the frequency of at least one harmonic of the carrier of the input signal, a second bias circuit 1308 connected between the second matching circuit 1304 and the transistor 1303, Connected between the second bias circuit 1308 and the transistor 1303,
Suppressing all or some frequencies from a frequency corresponding to DC to a frequency corresponding to an occupied bandwidth of an input signal input to an input terminal, and / or a frequency of at least one harmonic of a carrier of the input signal. And a second specific frequency suppressing means 1309.

As shown in FIG.
3, on the input side and / or the output side, all or some of the frequencies from the frequency corresponding to the direct current to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal, and / or the carrier of the input signal Specific frequency suppressing means 1307, 1 for suppressing the frequency of at least one harmonic of
By providing 309, the unbalance of signal distortion generated in the amplifier can also be suppressed. Therefore, when an amplifier as shown in FIG. 12 is used, the effect of suppressing the unbalance of signal distortion in the entire power amplifying device is increased. Note that the circuit shown in FIG. 13 can be used as an example of the second bias circuit 1308. When the circuit shown in FIG. 13 is used as the second bias circuit 1308, the second bias circuit 1308 has a specific frequency. Exhibits the function of suppression means.

[0077]

As is apparent from the above description, the present invention provides a predistortion compensating circuit for generating an intermodulation distortion component capable of substantially canceling out an intermodulation distortion component generated in an amplifier. Can be.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a predistortion compensation circuit according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a predistortion compensation circuit according to a second embodiment of the present invention;

FIG. 3 is a configuration diagram of a predistortion compensation circuit according to a third embodiment of the present invention;

FIG. 4 is a configuration diagram of a predistortion compensation circuit according to another embodiment of the present invention.

FIG. 5 is a diagram for explaining the configuration and principle of the predistortion compensation system;

FIG. 6 is a diagram for explaining a problem.

FIG. 7 is a configuration diagram of a predistortion compensation circuit according to another embodiment of the present invention.

FIG. 8 is a configuration diagram of a predistortion compensation circuit according to another embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional predistortion compensation circuit.

FIG. 10 is a diagram for explaining a problem.

FIG. 11 is a configuration diagram of a predistortion compensation circuit according to the first embodiment of the present invention.

FIG. 12 is a configuration diagram of an amplifier according to an embodiment of the present invention.

FIG. 13 illustrates an example of a second bias circuit 1308.

[Explanation of symbols]

101, 201, 301 input terminal 102, 202, 302 output terminal 110, 111, 210, 211, 312, 313, 3
14 connection points 112, 115, 117, 212, 215, 217, 3
15, 318, 320 Connection terminals 106, 206 Diode 305 Transistor 108, 109, 208, 209, 310, 311 Specific frequency suppression means 104, 107, 204, 207, 306, 308 Resistance 105, 114, 119, 205, 214, 219, 3
09, 317, 322 Capacitor 113, 213, 304, 307, 316 Coil 116, 216, 319 λ / 8 line 118, 218, 321 λ / 4 line

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kaoru Ishida 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd.

Claims (11)

[Claims] An input terminal for inputting a predetermined signal; a non-linear element connected directly or indirectly to the input terminal; a bias supply circuit for applying a voltage to the non-linear element; Directly connected to one or both sides of the element without passing through other elements, from a frequency corresponding to DC, all or a part of a frequency corresponding to an occupied bandwidth of an input signal input to the input terminal, and And / or a predistortion compensating circuit comprising: a specific frequency suppressing means for suppressing a frequency of at least one harmonic of a carrier of the input signal; and an output terminal for outputting a signal. 2. The specific frequency suppression at all or some frequencies from a frequency corresponding to the direct current to a frequency corresponding to the occupied bandwidth and / or at least one harmonic of a carrier of the input signal. The said specific frequency suppression means has the impedance value which the impedance which looked at the said specific frequency suppression means from the connection point to which the means was connected is lower than the impedance which looked at the said nonlinear element from the said connection point. Predistortion compensation circuit. 3. The predistortion compensation circuit according to claim 1, wherein the non-linear element is provided between a connection point between the input terminal and the output terminal and ground. 4. The predistortion compensation circuit according to claim 1, wherein the nonlinear element is connected between the input terminal and the output terminal. 5. The non-linear element is a transistor,
The input terminal is connected to one of a drain and a source of the transistor, the output terminal is connected to the other of a drain and a source of the transistor, and the bias supply circuit is connected to a gate of the transistor. 3. The predistortion compensation circuit according to 2. 6. The predistortion compensating circuit according to claim 1, wherein said specific frequency suppressing means is constituted by all or a part of a resistor, a coil, a capacitor, and a transmission line. 7. The predistortion compensation circuit according to claim 1, wherein said non-linear element comprises a diode. 8. The predistortion compensation circuit according to claim 1, wherein said non-linear element comprises a transistor. 9. A power amplification device comprising: the predistortion compensation circuit according to claim 1; and an amplifier for amplifying a signal from the predistortion compensation circuit. 10. An amplifier comprising: an input terminal for inputting a signal; a first matching circuit connected to the input terminal; a transistor having a gate connected to the first matching circuit; A second matching circuit connected to the drain of the second matching circuit; an output terminal connected to the second matching circuit for outputting a signal; and a second matching circuit connected between the first matching circuit and the transistor. A first bias circuit; a second bias circuit connected between the second matching circuit and the transistor; directly connected to one or both sides of the transistor without passing any other element, and equivalent to DC. And / or at least one of the frequencies of the carrier wave of the input signal and / or a frequency corresponding to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal. Power amplifier of claim 9 which is composed of a specific frequency suppressing means for suppressing the frequency of the wave. 11. The amplifier, comprising: an input terminal for inputting a signal; a first matching circuit connected to the input terminal; a transistor connecting the first matching circuit to a base; A second matching circuit connected to the collector of the second matching circuit, an output terminal connected to the second matching circuit and outputting a signal, and connected between the first matching circuit and the transistor. A first bias circuit; a second bias circuit connected between the second matching circuit and the transistor; directly connected to one or both sides of the transistor without passing any other element, and equivalent to a direct current And / or at least one of the frequencies of the carrier of the input signal from the frequency of the input signal to the frequency corresponding to the occupied bandwidth of the input signal input to the input terminal. Power amplifier of claim 9 which is composed of a specific frequency suppressing means for suppressing the frequency of the wave.