GB2393866A

GB2393866A - A class F Doherty amplifier using PHEMTs

Info

Publication number: GB2393866A
Application number: GB0220732A
Authority: GB
Inventors: Rasib Khan; Nicholas D Archer; Stewart R Walker; Christopher I Mobbs
Original assignee: Filtronic PLC
Current assignee: Filtronic PLC
Priority date: 2002-09-06
Filing date: 2002-09-06
Publication date: 2004-04-07
Also published as: AU2003263320A1; GB0220732D0; WO2004023646A1

Abstract

A Doherty amplifier uses a GaAs pseudomorphic HEMT as output transistor of the peaking amplifier 120. The PHEMT absorbs substantially no power from the common node 135 when the peaking amplifier is inactive. A silicon LDMOS transistor would absorb much more power, reducing amplifier efficiency. The output networks 118 and 128 cause the amplifiers 110 and 120 to operate in class F or in modified class F by providing short circuits at the lower even harmonics and open circuits at the lower odd harmonics. Each network (figure 4B) comprises a low-pass ladder filter and a shunt resonator with resonant frequency close to the fundamental frequency. GaN or SiC devices may be used instead of a PHEMT. The amplifiers may have multiple stages (figure 2). The operating frequency is around 2.14 GHz.

Description

1 2393866

Power Amplifier The present invention relates to high efficiency power amplifiers, and in particular to semiconductor transistor 5 based power amplifiers for use in wireless telecommunication applications in the radio and microwave frequency bands.

In the 1930s a high efficiency, linear, valve based power 10 amplifier was devised by W.H. Doherty. This 'Doherty' amplifier configuration consisted of two valve amplifiers (the main amplifier and the auxiliary amplifier), which delivered power into a common load in an efficient manner. More recently, attempts have been made to 15 reproduce the Doherty technique, but with valve amplifiers replaced by semiconductor transistor based amplifiers. However, transistor based Doherty amplifiers have not been realised effectively at high frequencies due to the limitations imposed by semiconductor device 20 parasitics.

There are significant problems with the realization of a Doherty amplifier using most common silicon based RF power transistor devices, including LDMOS.

It would be advantageous to be able to provide a power amplifier realised using transistors while still providing the high efficiency of the Doherty configuration. According to a first aspect of the invention, there is provided a power amplifier for amplifying an electrical signal to be supplied to a load, comprising a transistor based main amplifier, a transistor based auxiliary

amplifier, parallel to the main amplifier, an impedance inverted between the main amplifier and a common output of the amplifier, the main amplifier signal path and auxiliary amplifier signal path providing signals in 5 phase at the common output, and the auxiliary amplifier absorbing substantially no power when inactive.

The auxiliary amplifier is configured so that it absorbs sufficiently little power when inactive, that the 10 efficiencies of the Doherty configuration can be realised while using transistor based amplifying devices.

The main amplifier can be configured to operate in a number of classes, such as class A, A/B, D, E, F. 15 modified F class, inverse class F (also known as class F bar). The auxiliary amplifier final stage can also be configured to operate in a number of classes such as class A, A/B, C, D, E, F. modified class F. inverse class F. Preferably the auxiliary amplifier includes at least 20 one stage which is class c.

The main amplifier and/or the auxiliary amplifier can be class F amplifiers. The main amplifier and/or auxiliary amplifier can have a terminating network causing them to 25 operate in a preferred class. A terminating network can be connected to the main amplifier and/or the auxiliary amplifier causing the amplifier to operate in class F or modified class F. 30 The terminating network can present a real impedance at the fundamental frequency of the signal being amplified,

a short circuit at the first (2m-2) even harmonics, an open circuit at the first (2m-1) odd harmonics and reactive terminations at all harmonics 2m and above, where m = 1,2,3,,. The terminating network can 5 include a ladder of impedance inverters. The terminating network can include a resonator which resonates at substantially the fundamental frequency. The terminating network can be configured to compensate for amplifier device parasitics. Preferably, the terminating network 10 compensates for the output capacitance of an amplifying transistor. The main amplifier and/or auxiliary amplifier can be multistage. The main amplifier can include a class F 15 amplifying stage. The auxiliary amplifier can include a class F amplifying stage. Preferably, the auxiliary amplifier includes a class C driver stage.

The auxiliary amplifier can include a GaAs based device.

20 Preferably the auxiliary amplifier includes a pseudomorphic high electron mobility transistor (pHEMT).

According to a further aspect of the invention, there is provided a method of amplifying an electrical signal to 25 be supplied to a load, comprising the steps of providing a signal path through a main transistor based amplifier, said signal path including an impedance inverter between the main amplifier and a common point, providing a signal path through an auxiliary transistor based amplifier, 30 parallel with the main amplifier signal path, and to the common point, wherein the signal paths provide signals at the common point which are substantially in phase, and substantially preventing absorption of electrical power by the auxiliary amplifier while inactive.

The main amplifier and/or auxiliary amplifier can be operated in class F. The auxiliary amplifier can be driven by a device operating in class C. The auxiliary 5 amplifier and/or main amplifier can include a GaAs based transistor. An embodiment of the invention will now be described, by way of example only, and with the reference to the 10 accompanying drawings, in which: Figure 1 shows a schematic block diagram of a power amplifier illustrating the Doherty configuration) Figure 2A shows a schematic block diagram of an 15 embodiment of a power amplifier according to the present invention; Figure 2B shows a schematic block diagram of a further embodiment of a power amplifier according to the present invention; 20 Figure 3A shows a plot illustrating the efficiency versus the output power of a Doherty amplifier for an 8 dB efficiency range; Figure 3B shows a plot illustrating the contributions to the power output from each device 25 versus the power input power for a Doherty amplifier; Figure 4A shows a schematic block diagram of output network of the main and auxiliary amplifier parts of an amplifier according to the invention; 30 Figure 4B shows a schematic circuit diagram of the output network parts; Figures 4C, 4D and 4E respectively show prototype mat, 2 & 3 terminating networks;

Figure 5 shows a plot of the measured efficiency as a function output power for a number of implementations of the power amplifier according to the present invention; 5 Figure 6A shows a further implementation of a power amplifier according to the present invention.

Similar items in different figures share common reference numerals unless indicated otherwise.

Some of the details of otherwise conventional features, the presence and realization of which will be apparent to a person of ordinary skill in the art in light of the following description, have been omitted from the

15 following description in order not to obscure the present

invention. Figure 1 shows a schematic block diagram of an amplifier 100 illustrating the background to and operation of the

20 present invention. The amplifier 100 includes a main amplifier 110 and an auxiliary amplifier 120 connected in parallel with the main amplifier. A common input 102 is connected to a power dividing device 105. A main amplifier signal path passes through the main amplifier 25 and an auxiliary amplifier signal path passes through the auxiliary amplifier. The main and auxiliary signal paths join at a common connection or junction 135. An impedance inverter 125 is connected between the output of the main amplifier and a further impedance inverter 140 30 is connected between the common connection and an output 142 of the amplifier 100. A load 130 is connected to the output 142 of the amplifier.

The input power dividing device 105 splits the input signal between the main amplifier 110 signal path and the auxiliary amplifier 120 signal path. The ratio of the power division between the two paths may or may not be 5 equal. The ratio of power division between the two paths is dependent upon the gain of the main and the auxiliary amplifier, which in turn depends on the class of operation of the amplifiers. For example, class C amplifiers have a lower gain than, for example, class 10 A/B. The power division ratio is also dependent on the first break point.

The ratio of the power division between the two paths is dependent upon the relative gain of the main and 15 auxiliary amplifiers and on the first break point. The gain of the two sides is likely to be different since they are biased differently. For example some of the auxiliary stages will be in class C which has less gain than most other types of bias. The first break point is 20 determined by the ratio of the load impedance seen from the common junction and impedance inverter 125. This fixes break point 150 and the power level at breakpoint 155. The power division ration is chosen using the following equations.

Normalising the maximum output power to 1W, the load impedance to lohm and the maximum voltage at either end of impedance inverter 125 to lVrms. The first break point is given by 1/k^2 where k is the value of impedance 30 inverter 125. The main amplifier maximum power will be Ilk, and the auxiliary amplifier maximum output power will be 1-1/k. If Ga is the auxiliary amplifier gain and

Gm is the main amplifier gain then the power splitter ratio will be (Ga/k) /(Gm*(1-1/k)). Some deviation from this may be necessary to allow for nonideal behaviour.

5 The input power dividing device can be a hybrid, power divider or a coupler. If the power dividing device is an in-phase divider (i.e. it does not introduce a phase change in the signal in either path) then an additional +90 phase length is needed in the auxiliary amplifier 10 path to compensate for the +90 phase change introduced by the impedance inverted 125 in the main amplifier 110 path up to the common junction 135. If a quadrature power dividing device 105 is used, then the split with a +90 phase change is used to feed the auxiliary amplifier 120.

The signals in the two paths combine at the common junction 135. The impedance inverted 125 connects the output of the main amplifier 110 to the common junction, and the output of the auxiliary amplifier 120 connects 20 directly to the common junction. The combined output of the amplifier is fed via impedance inverter 140, which is provided to scale the impedance of the power amplifier to more closely match that of the load 130. The load can be a variety of devices depending on the application of the 25 amplifier, including, for example, an antenna, a filter or an isolator.

The idealized basic mode of operation of amplifier 100 will be discussed below, before more detailed 30 descriptions of embodiments of the amplifier will be

presented with reference to Figures 2A, 2B and 6.

Amplifier efficiency is the proportion of the DC power PDC supplied to the amplifier that is available as RF

power PRO at the output of the amplifier, to be delivered to the load, i. e. = PRE/PDC. The amplifier is most efficient, for a given output power level, when an optimum load is presented at its output. The resulting RF 5 voltage waveform across the optimum load has a peak-to-

peak magnitude equivalent to twice the DC supply voltage, for a given output power level. As the voltage swing at the output is dependent on the load resistance, the efficiency of the amplifier changes with the load 10 resistance. Also, the efficiency of the amplifier decreases as the RF drive decreases.

The amplifier configuration of Figure 1 is essentially an active loadpull technique in which the resistance of the 15 RF load is dynamically modified by applying current from a second, phase-coherent current source: i.e. the current supplied by the auxiliary amplifier is in phase with the current supplied by the main amplifier at junction 135.

In the amplifier 100 the auxiliary amplifier 120 is the 20 phase coherent current source, which modifies the load seen by the main amplifier 110. The final output power of the amplifier 100 is the combination from both the main amplifier 110 and the auxiliary amplifier 120. At high output power levels, both the amplifiers contribute, but 25 as the input drive is reduced, there comes a point when the auxiliary amplifier 120 shuts down and generates no more RF power. In order for the amplifier 100 to operate correctly, the auxiliary amplifier needs to either cease drawing any DC power or under some bias conditions (e.g., 30 deep A/B) draw a very small amount of DC Power.

Referring to Figure 3A in region 140 of graph 302, the auxiliary amplifier 120 is effectively turned off and is not contributing to the output power. The output power

from the main amplifier 110 increases with the increasing input drive level and the efficiency improves. At breakpoint 150 the main amplifier is operating at its maximum efficiency, and the RF voltage amplitude at its 5 output is twice the DC supply. The maximum output power from the main amplifier at breakpoint 150 is a fraction - of its actual saturated output power capability. As the drive level is increased beyond breakpoint 150 (region 145) the auxiliary amplifier starts to turn on, supplying 10 current to the load and hence dynamically decreases the load resistance seen by the main amplifier, due to an auxiliary amplifier load- pulling effect. The impedance inverter 125 causes the resistive impedance seen by the main amplifier to decrease as the auxiliary amplifier 15 current increases.

The amount of output power from the main amplifier increases with the dynamically decreasing load resistance up to its maximum output power capability at point 155, 20 as illustrated by graph 304 of figure 3B. The main amplifier operates at its maximum efficiency in region 145 at all the output power levels, since the RF voltage amplitude at its output remains twice the DC supply voltage. In region 145 the auxiliary amplifier turns on and sees an upward load-pull effect. Initially, the auxiliary amplifier will not have the maximum RF voltage swing at its output, hence the composite efficiency drops slightly 30 before reaching the maximum at point 155, where the input drive is sufficient to swing the RF voltage at the output of auxiliary amplifier at twice the DC supply. Hence the amplifier 100 exhibits a high efficiency over a wide range of output power levels. The range depends on the

impedance of impedance inverted 125, which determines the fraction of output power available from the main device at the break point 150, and the power capability ratio of the main and auxiliary amplifier.

Figures 2A and 2B illustrate two embodiments of amplifier 100. Figure 2A shows an amplifier 200 in which the main 10 amplifier 110 and auxiliary amplifier 120 are implemented as two stage devices. Main amplifier 110 includes a main driver stage 114 and a main amplifier stage 116. An amplifier output network 118 is connected to the output of the amplifier stage, as will be described in greater 15 detail below. Auxiliary amplifier 120 includes an auxiliary driver stage 124 and an auxiliary amplifier stage 126. An amplifier output network 128 is connected to the output of the amplifier stage 126, as will be described in greater detail below.

In the main amplifier 110, the driver 114 is a class A/B stage and the final stage 116 is a class F amplifier with the output matching network 118 presenting the appropriate impedances to the final stage amplifier to 25 cause it to operate in class F (i.e. the correct impedance at the fundamental frequency, open circuits at the odd harmonics and short circuits at the even harmonics). The matching network 118 also ensures that only a signal at the fundamental frequency is present, by 30 filtering out the harmonics before the signal flows into the impedance inverter 125. Driver stage 114 could also be of any other class e.g. class A, B. D, E, modified class F etc.

The auxiliary driver 124 is biased in class C. The auxiliary amplifier is class F with an output network 128 similar to output network 118.

5 The impedance inverter 140 in Figure 2A and 2B scales the impedance at the common junction 135 to the load 130.

For example, in an embodiment of the invention, impedance inverter 125 was implemented as a \/4 microstrip transmission lines of 38Q impedance, and impedance 10 inverter 140 was implemented as a \/4 microstrip transmission lines of 30.86Q impedance. Impedance inverters 125 and 140 can be implemented in a number of ways, for example as including lumped components, and the impedance values will vary depending on the actual 15 implementation of the amplifier.

The two stage auxiliary amplifier improves the controllability of the auxiliary amplifier turn on. For a single stage auxiliary amplifier, the auxiliary amplifier 20 would be biased in class C to control its turn on. Class C amplifiers do not conduct at low input power levels and so the auxiliary amplifier is inactive in the low input power level region 140. AS the input power level increases, the class C amplifier gradually turns on and 25 becomes active. The biasing of auxiliary driver 124 in class C allows the auxiliary amplifier stage 126 to be class F or modified class F. A two stage auxiliary amplifier provides a number of advantages. Stability can be improved due to the use of a physically small device 30 biased in class C. A more uniform impedance match over the dynamic range of the amplifier can be achieved. The final stage can have an increased gain and output power than could be achieved if the final stage were class C, and without an increase in the power delivered to the

final stage by the driver stage. The control of the auxiliary amplifier turn on is improved. Biasing the final stage in class C can have a number of drawbacks. A class C device can have a substantially larger gate 5 capacitance which is more difficult to match into over a wide range of dynamic input power levels and does not give a smooth turn on characteristic. If the final stage is biased in class C then owing to a larger negative bias on the gate, the device can breakdown before the full 10 output power is available from it. The final stage is important in terms of efficiency and if it is class C then it has a lower gain and hence worse power added efficiency compared to other bias classes.

15 The harmonic content of the signal is filtered out by the matching networks 118 128, before it reaches the common junction 135, which is important to yield the high efficiencies promised by the Doherty configuration. The load-pulling effect only occurs at the fundamental 20 frequency and the open and short circuits presented by the matching networks at the harmonics for class F operation are not effected by the load-pulling. This class F technique is one example of such a circuit that provides high efficiency and at the same time provides 25 the harmonic filtering at the output of the amplifier, which maximises the Doherty load-pulling effect over a wide range of input powers.

Figure 2B shows an amplifier 202 similar to amplifier 200 30 shown in figure 2A. However, both the main 110 and auxiliary 120 amplifiers include a pre-driver stage 112 and 122 respectively. The pre-driver stages 112, 122 effectively move control of the main and auxiliary amplifiers down the chain by a stage. Pre-driver 122 is

biased in class C, and pre-driver 112 is biased in class A/B which offers even further improvements to the advantages described above for amplifier 200. Biasing the pre-driver 122 in class C allows the driver stages 5 114 & 116 and the final stages 124 & 126 to be biased in any class, such as A/B, A, D, E, class F. modified class F. inverse class F. etc. which is suitable to provide the required performance of the amplifier.

10 In both figure 2A and 2B all the amplifiers use GaAs transistors. Other transistor technologies, such as silicon LDMOS, GaN, SiC, etc. may be used for the amplifiers stages, except for the auxiliary amplifier final stage 126. This is because for power levels where 15 the auxiliary amplifier 120 is off, the amplifier 126 should not absorb RF power from the main amplifier, i.e. it should appear to be approximately an open circuit looking into its output from the common junction 135.

For silicon LDMOS power devices typically half of the 20 power incident on the output can be absorbed. This has a significant effect on efficiency which can wipe out the gains in efficiency due to the Doherty technique. For GaAs pHEMTs the absorbed power can be as low as one twentieth that of LDMOS transistors. Therefore, a GaAs 25 transistor can yield the high efficiencies promised by the Doherty configuration. However, any transistor device technology, such as GaN, SiC or others, that absorbs little power from the main amplifier and presents a substantially open circuit in their 'off' state will be 30 suitable as the auxiliary final stage 126 as well.

Figure 4A shows the main amplifier output matching network 118 and the auxiliary amplifier output matching network 128. Each of the output networks 118, 128

provides a termination to the preceding amplifier causing it to act as a class F or modified class F amplifier.

The terminating networks 118, 128 are designed to present a complex impedance at the fundamental frequency of the 5 signal being amplified, a short circuit at the first (2m-

2) even harmonics, an open circuit at the first (2m-1) odd harmonics and reactive terminations at all harmonics 2m and above (m = 1,2,3,..,=). Such-a terminating network has the effect of removing or reducing the 10 presence of even harmonic components of the voltage present in the amplifier so that the voltage has a squarer waveform thereby reducing the power dissipated in the amplifier itself resulting from the co-existence of current and voltage in the amplifier. The terminating 15 circuit also includes a shorting circuit which presents a short circuit to all harmonics above the fundamental frequency so that only the amplified signal at the fundamental frequency is output from the terminating network. Figure 4A shows the main amplifier output matching network 118 and the auxiliary amplifier output matching network 128, which have to be phase changes of multiples of 90 such that at the common junction 135 From the main path: 2n+1 inverters where n = 0,1,2,3,...= From the aux. path: 2m inverters, where m = 0,1,2,3,...m In figure 4A Kl to Kn and K1 to Km are impedance inverters, 30 which are used to transform the device impedance to the impedance the amplifier requires at the common junction 135. The first impedance inverted K1 for both the output matching networks 118 and 128 at the output of the main and auxiliary amplifier simultaneously, has to absorb the

device parasitics as part of the impedance inversion network. A suitable m=3 matching circuit 208 for an amplifier 5 device to operate as modified Class F will now be described in general terms with particular reference to figure 4B. The output capacitance 210 of the transistor device is considered to be part of the external matching circuit. Capacitance 210 is not a separate capacitor 10 component but rather represents the inherent capacitance of the transistor output. This circuit 208 then has to provide the correct impedance at the fundamental frequency, provide a short circuit at the first 2m-2 even harmonics, provide an open circuit at the first 2m-1 odd 15 harmonics and reactive terminations at all harmonics 2m and above.

The main part of the terminating circuit 118, 128 attached to the output of the amplifier devices 110, 120 20 is a lowpass ladder network 230 commencing with a shunt capacitor 212 and terminated with a narrow bandwidth shunt resonator 232, comprising capacitance 224 and inductance 226, connected in parallel with the resistive load 130. This shunt resonator is configured to resonate 25 close to the fundamental frequency and provide the correct impedance at the fundamental frequency which when transformed through the matching circuit, provides the correct impedance to the amplifier device 110, 120 for optimum efficiency. The presence of this shunt resonator 30 232 also ensures that the matching circuit itself 118, 128 is short circuited at its output for all frequencies upwards from and including the 2m harmonic.

Nodal admittance scaling can also be implemented to transform the low impedance level at the amplifier device 110, 120 to higher terminating impedances. This can be achieved by normal techniques and hence is omitted in the 5 discussion.

Normal d.c. biasing can be treated separately in the form of an r.f. choke in the drain bias feed and a decoupling capacitor prior to the resistive load and short 10 resonator, then in prototype form the matching network is required to have a short circuited input admittance of the form: y() _ (p2 + 1)(p2 + g)()(p2 + (2m -1) 2) ( 1) P. p(p2 +4)(p2 +16)()(p2 +(2m-2)2) and should act as an impedance inverted at p=+j corresponding to the normalized fundamental frequency.

The resultant prototype networks 180, 182, 184 from the 20 synthesis of low ordered (m=1, 2 and 3) networks are shown in Figures 4C, 4D and 4E respectively. The general formula for explicit values for the elements in the arbitrary degree network are as follows: 25 Let gr=Cr r odd =Lr r even then g=1, gigs m(2m 1) 4 r = 2 2m -] r r+] (2m-1+r)(2m-r)

and g2mgm+= (2) where at p=j, the characteristic impedance of the network 5 acting as an impedance inverter is: z 1 (3) (2m -1) In Figures 4C-E, the values for the impedances of the components in each network are normalized relative to the 10 impedance of the amplifier device capacitance Cds 210, which provides the first capacitive element in each network. The above describes the optimum complex impedance termination for a Class F and modified Class F power amplifier so as to operate with the maximum efficiency of: q= cots l 2(m+1) l2(m +1)] when the first 2m-1 odd harmonics are open circuited. To provide the correct termination, lowpass prototype circuits have been synthesized 180, 182, 184 and explicit formulas given for element values in the general network 25 of degree 2m+1 (equations 2,3). This network 230 is terminated in a narrowband shunt resonant circuit 232 with the correct resistive termination 130 enabling the entire circuit to be scaled at its internal nodes to provide the practical impedance levels for any transistor 30 amplifier 110, 120.

! Each impedance inverter is provided by a capacitor 212, 216, 220 and associated inductor 214, 218, 222 respectively. The first impedance inverter Kl for both the output matching networks 118 and 128 at the output of 5 the main and auxiliary amplifier, absorbs the device parasitics 234 (represented by transistor drain-source capacitance 210) as part of the impedance inversion network. This can be achieved by selecting the capacitance of capacitor 212 to take into account the 10 'extra' capacitance 210 already provided by the transistor output.

In the lumped element impedance inverting class F matching network shown in figure 4B, capacitor 210 15 represents the device parasitics and the capacitive and inductive elements 212, 214, 216, 218, 220, 222, 224, 226 and 228 form the class F matching network such that the amplifier device 110, 120 sees an open circuit at odd harmonics and a short circuit at the even harmonics. The 20 capacitive component 224 and inductive component 226 form a resonator at the fundamental frequency, which effectively filters out the harmonics, and hence only the fundamental component is present at the output of the matching networks 118 and 128. This makes an important 25 contribution to the effective realization of the Doherty amplifier, as the impedance inverters 125, 140 are frequency dependent.

The elements making up the terminating networks 118, 128 30 may be realised as lumped components or distributed components, or a mixture.

Figure 5 shows a graph 160 illustrating the measured efficiency 162, 164, 166 versus the output power for an

i implementation of amplifier 202 at three different frequencies 2.11, 2. 14 and 2.17GHz, respectively. As can be seen the amplifier maintains a very high efficiency over a substantial power range in region 168.

Figure 6 shows a further embodiment of an amplifier 204 according to the present invention. The output matching networks 118 and 128 are formed from impedance inverters as described above, such that they absorb the device 10 parasitics and also incorporate the class F harmonic terminations. The impedance inverters in conjunction with the phase equaliser 121 ensure that, at the common junction 135, the phases of thesignals from the two paths are in phase and hence correct for Doherty action.

15 Phase equaliser 121 can be implemented using parallel microstrip lines.

The main amplifier stages 112 and 114, and the auxiliary amplifier stages 122 and 124 are implemented as balanced 20 amplifiers. Auxiliary predriver 122 controls the turn on and the two devices in this amplifier are both biased in class C, but may be at a different bias potential than each other for controlling the turn on characteristics.

The power divider 105 is a hybrid. The phase equaliser 25 121 is used to balance the phase between the two paths up to the common junction 135 and gain equaliser 111 is used to compensate for lower gain in the auxiliary path compared to main path. The gain in auxiliary amplifier is lower than main amplifier, since one stage is biased in 30 class C. The impedance inverter 125 is a 38Q \/4 microstrip line and impedance inverter 140 is a 30.86Q \/4 microstrip line.

Claims

CLAIMS:

1. A power amplifier for amplifying an electrical signal to be supplied to a load, comprising: 5 a transistor based main amplifier; a transistor based auxiliary amplifier connected in parallel with the main amplifier; an impedance inverter connected between an output of the main amplifier and a common output of the amplifier, 10 wherein a main amplifier signal path and an auxiliary amplifier signal path are such that signals at the common output are in phase and the auxiliary amplifier will absorb substantially no power when off.

2. The amplifier as claimed in claim 1, and including respective terminating networks connected to the main amplifier the auxiliary amplifier which filter harmonic signals so that signals at the common output comprise signals at a fundamental frequency only.

3. The amplifier as claimed in claim 1, wherein the main amplifier and/or auxiliary amplifier are class F amplifiers. 25

4. The amplifier as claimed in claim 3, and including a terminating network connected to the main amplifier and/or the auxiliary amplifier causing the amplifier to operate in class F or modified class F. 30

5. The amplifier as claimed in claim 4, wherein the or each terminating network presents a complex impedance at the fundamental frequency of the signal being amplified, a short circuit at the first (2m-2) even harmonics, an open circuit at the first (2m-1) odd harmonics and

reactive terminations at all harmonics 2m and above, where m = 1,2,3,.,=.

6. The amplifier as claimed in claim 3, wherein the or 5 each terminating network is configured to compensate for amplifier device parasitics.

7. The amplifier as claimed in claim 1, wherein the main amplifier is multistage and includes a class F 10 amplifying stage.

8. The amplifier as claimed in claim 1, wherein the auxiliary amplifier is multistage and includes a class F amplifying stage.

9. The amplifier as claimed in claim 8, wherein the auxiliary amplifier includes a class C driver stage.

10. The amplifier as claimed in claim 1, wherein the 20 auxiliary amplifier includes a GaAs based device.

11. A power amplifier substantially as hereinbefore described. 25

12. A method of amplifying an electrical signal to be supplied to a load, comprising: providing a signal path through a main transistor based amplifier, said signal path including an impedance inverter between the main amplifier and a common point; 30 providing a signal path through an auxiliary transistor based amplifier, parallel with the main amplifier signal path, and to the common point, wherein the signal paths ensure that signals at the common point are substantially in phase; and

i substantially preventing absorption of electrical power by the auxiliary amplifier when inactive.

13. The method of claim 12, further comprising filtering 5 harmonics from the first signal path and the second signal path so that the signals atthe common point comprise signals at a fundamental frequency only.

14. The method of claim 12, wherein the main amplifier and/or auxiliary amplifier are operated in class F. 15. The method of claim 13, wherein the auxiliary amplifier is driven by a class C operating device.

15. A method of amplifying an electrical signal substantially as hereinbefore described.

15

16. The method of claim 13, wherein the auxiliary amplifier and/or main amplifier includes a GaAs based transistor.

17. A method of amplifying an electrical signal 20 substantially as hereinbefore described.

Amendments to the claims have been filed as follows CLAIMS:

1. A power amplifier for amplifying an electrical signal to be supplied to a load, comprising: a transistor based main amplifier; 5 a transistor based auxiliary amplifier connected in parallel with the main amplifier; an impedance inverter connected between an output of the main amplifier and a common output of the amplifier; and respective terminating networks connected to the main amplifier and the auxiliary o amplifier before the common output which filter harmonic signals so that signals at the common output comprise signals at a fundamental frequency only; wherein a main amplifier signal path and an auxiliary amplifier signal path are such that signals at the common output are in phase and the auxiliary amplifier will absorb substantially no power when off.

5 2. The amplifier as claimed in claim 1, wherein the main amplifier and/or auxiliary amplifier are class F amplifiers.

3. The amplifier as claimed in claim 2, wherein at least one of the terminating networks connected to the main amplifier and the auxiliary amplifier cause the amplifier to operate in class F or modified class F. 20 4. The amplifier as claimed in claim 3, wherein the or each terminating network presents a complex impedance at the fundamental frequency of the signal being amplified, a short circuit at the first (2m- 2) even harmonics, an open circuit at the first (2m-1) odd harmonics and reactive terminations at all harmonics 2m and above, where m = 1,2,3,..,8.

5. The amplifier as claimed in claim 2, wherein the or each terminating network is 25 configured to compensate for amplifier device parasitics.

-21, 6. The amplifier as claimed in claim 1, wherein the main amplifier is multistage and includes a class F amplifying stage.

7. The amplifier as claimed in claim 1, wherein the auxiliary amplifier is multistage and includes a class amplifying stage.

5 8. The amplifier as claimed in claim 7, wherein the auxiliary amplifier includes a class C driver stage.

9. The amplifier as claimed in claim I, wherein the auxiliary amplifier includes a GaAs based device.

10. A power amplifier substantially as hereinbefore described.

lo 11. A method of amplifying an electrical signal to be supplied to a load, comprising: providing a signal path through a main transistor based amplifier, said signal path including an impedance inverter between the main amplifier and a common point; providing a signal path through an auxiliary transistor based amplifier, parallel with the main amplifier signal path, and to the common point, wherein the signal paths 5 ensure that signals at the common point are substantially in phase; filtering harmonics from the first signal path and the second signal path before the common point so that the signals at the common point comprise signals at a fundamental frequency only; and substantially preventing absorption of electrical power by the auxiliary amplifier 20 when inactive.

12. The method of claim 11, wherein the main amplifier and/or auxiliary amplifier are operated in class F. 13. The method of claim 11, wherein the auxiliary amplifier is driven by a class C operating device.

14. The method of claim 11, wherein the auxiliary amplifier and/or main amplifier includes a GaAs based transistor.