JPH0319507A - High efficiency amplifier - Google Patents

Abstract

PURPOSE:To improve the power efficiency by providing a limiter to a gate input and clipping positive and negative peaks of a gate voltage to a value nearly equal to maximum allowable forward and reverse voltages of the gate or below respectively. CONSTITUTION:A limiter LM is provided to a gate input of a TR Q, a gate voltage V9 is formed to be a trapezoidal wave and the positive and negative peaks are set equal to the maximum allowable forward and reverse voltages of the gate or below respectively. The gate connects to a power terminal PW3 receiving a voltage VL1 corresponding to the positive peak voltage of a limiter output via a diode D1 and connects to a power terminal PW4 receiving a voltage VL2 corresponding to the negative peak voltage of the limiter output via a diode D2. Thus, it is possible to make the drain voltage VD close to a rectangular wave, and the drain loss is reduced and a class F amplifier with excellent power efficiency is obtained.

Description

[Detailed Description of the Invention] "Industrial field of f-li applications"
Related to improving the efficiency of ET ('ji field effect 1 transistor) amplifiers.

``Prior Art'' Conventionally, a class F amplifier as shown in the fourth country has been used as this divine amplifier. A sine wave input signal (generally FM wave, PM wave, etc.) applied to the human power terminal IN is applied to the gate of a quasi-field effect transistor (hereinafter referred to as FET or simply transistor) Q via a direct lk blocking capacitor C. l1 will be done. The gate of the transistor Q is connected to the power supply terminal P W . through the choke coil I,1. Connected to. The source of the transistor Q is connected to the voltage terminal PW. of the power supply voltage ■..=lO■, for example, through the choke coil L2. The signal amplified by the transistor Q is DC switching capacitor C,
, the λ/4 distributed constant line Nl, and the output terminal OUT in order to be supplied to the load resistor R1. The output end of the λ/4 distributed constant line is grounded via a parallel resonant circuit N2 that resonates at the frequency f of the fundamental wave of the input signal. The load impedance ZL of the transistor Q is a harmonic reflection circuit Fc dominated by the λ/4 distributed constant line N1 and the parallel resonant circuit N2.
According to the characteristics of (a), for the main wave ZL(f.)
R'l Here, R'L = R20 /Rt, and R0 is the characteristic impedance of the S/4 distributed constant line N.

(1)) For even harmonics, Zc (2nf+
) −=0 (c) For strange harmonics Z1 (f=
−． −rr 1) Constructed so that z(1).

Here, n≧1 is an integer.

From the characteristics of (a) to (c) above, (2) Drain voltage■. contains only the direct component, the fundamental wave, and the odd-numbered harmonics (because the negative GiZL is short-circuited to the even-numbered harmonics and the voltage becomes zero), and (v) the drain current I. contains only the DC component, the fundamental wave, and even harmonics (because the load ZL is open for odd harmonics and no current flows). Power terminal PW. The voltage of , that is, the gate high-ass voltage V, is selected to be equal to the pinch-off voltage vpD (−3 V in this example), which is the limit gate voltage at which the transistor Q cant-off.

When the gate voltage of Masahiro wave ■9 shown in FIG. 5A is applied to the gate of the transistor Q, V as shown in IJB of FIG.
, > V, the drain current I flows toward the source, and in other half waves where ■, ≦ V, the transistor/transistor Q is turned off and I n -' −
It is 0. Therefore, Train Indensho 1. becomes a half-wave rectified wave of a sine waveform. l"r<'lid of the drain electric power Mi lo changes depending on the magnitude of the drain electric current Mi lo.However, from the above characteristic (ne), the 1' rain electric lacquer ID has a fundamental wave and even-order harmonics. We have a half-sine rectified waveform containing only one drain voltage corresponding to one drain current.

As shown in Figure C, the waveform is vertically swung around the electric voltage von = 10 V. In this example, the peak value of the valley is a value slightly larger than Ov (the transistor has an on-resistance, so it is not Ov), and the peak value of the peak is a value slightly smaller than 2VDn-20V, and each waveform has a slightly chipped tip. becomes. If the amplitude of the gate poison IJV becomes somewhat smaller than in Figure 8, the drain voltage Y■l■.

The peak value of will never reach a plateau. On the contrary, game 1 electricity 1
As jE V , becomes larger, the 1' rain poison pressure v0 becomes increasingly different, approaching a trapezoidal wave or even a rectangular wave. However, the above characteristic (2) is always maintained.

]・Rain current 1. As mentioned in 0) above, consists of a DC component, a fundamental wave, and an even-order l'''j jl4 wave, but the DC component flows through the chic coil L2, and the fundamental wave and even-order harmonics are λ /4 line N, is connected to /A.The even-order harmonics are parallel resonance I'i with small I/beadance compared to R.
The human part flows to 1st road N, and almost no flow flows to RL.

The impedance of the parallel resonant circuit N2 to the convex main wave is R
, the main wave current flows through R1. Therefore, the output voltage Vout supplied to the negative (; I R t becomes a sine wave with only the fundamental wave as shown in Figure 5D). .

6A to 8A show the transistors Q and ■. In the static characteristic diagram 12, 11 ra/register Q takes (to.
Vo) is the operating point P of the amplifier. This is a diagram showing trajectories P, ~P2 moving around , and n and C in each of the above diagrams are drain currents 1 opposite to the locus of A, respectively.
, and the drain voltage . FIG. 6 shows a case where the amplitude of the input gate voltage vg is small and the drain voltage v0 does not reach a ceiling, and the above-mentioned locus P1 to P is the cropping point P. It becomes a straight line with a breaking point at . P' to P'2 are cases where the amplitude of the gate voltage vg is small.

Figure 7 shows drain voltage■. This is a case where the amplitude of the gate voltage v9 is increased until it reaches a peak and becomes a trapezoidal wave.

1 of (lo, Va)! It traces P. - Half of P2 P. -P
．． is the straight line P. P. It becomes a convex dl+ line below. FIG. 8 shows the case where the amplitude of the gate voltage (1)9 is further increased to bring the drain voltage v0 closer to a rectangular wave, and the traces P, -P.
The degree of gulf +Ib becomes even larger.

The drain loss of transistor Q is IDXVO at Lucara, point (L.Vo) (7) Locus P, -P. bay [1
)J(7) degree is large, and the closer to the VD axis and I axis of the coordinates, the smaller the drain n1 loss becomes. In other words, the closer the drain voltage waveform is to the rectangular wave C, the smaller the drain loss becomes. Also, although a detailed explanation is omitted, the load RL
The output power Po supplied to the drain voltage increases as the drain voltage waveform approaches a rectangular wave. Therefore, the same can be said about the power supply efficiency (drain efficiency) η - (P./P,.)XIOO%. In addition, ■),, is the direct 7A power supplied from the power supply to the drain, and P. is the power of the signal wave supplied to the negative (AjR,).

Figures 7 and 8 show power supply efficiency and {'rain voltage■.

The waveforms are shown to explain the relationship,
In reality, due to restrictions on gate voltage V, as described in the next section, drain voltage V. cannot be made into a 6-square wave or a square wave like this.

``Problem to be solved by the invention'' 1. In electronic equipment for use on 1Wastar, 1fA4iF type radio equipment, etc., power supplies need to be small, lightweight, and have a long life.
Output amplifiers are required to have good power efficiency. However, due to the performance of the FET that should not be used (GA.FET is used because it is in the GH2 band), the output is 1 {!
The I-container does not have satisfactory efficiency. That is, when the maximum value of the gate voltage is V, maκ〉O, a forward current (current flowing from the gate to the source) flows through the Schottky junction of the gate, and its permissible value is about @mA as an average DC value. Therefore, the positive gate voltage is limited to the maximum allowable forward voltage.

On the other hand, if the minimum value V,min of the gate voltage exceeds the reverse breakdown voltage of the Schottky junction (for example, -7V), will there be a leak? il
Since t'/A is di and its permissible value is several mA in normal DC value, the negative gate voltage 9 is limited to the maximum permissible reverse voltage.

In this way, since the positive and negative peaks of the gate voltage ■, are limited, the drain voltage ■. The gate voltage V. becomes a trapezoidal wave or a rectangular wave. Therefore, it was not possible to obtain high power supply efficiency.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a class F power amplifier with high power efficiency.

``Means for solving the problem'' As an output load circuit for the drain of a source grounded FET amplifier circuit biased to the gate or Vincioff voltage,
Connect a harmonic reflection circuit such that the human power impedance seen from the drain side shows resistance at the fundamental frequency of the input signal, and becomes a short circuit and an open circuit at even and odd harmonic frequencies, respectively. FET increases'K! In the device, in this invention, a limiter is provided on the gate input side to clip the stop and negative peak voltage of the gate quasi-voltage to values approximately equal to or less than the maximum allowable forward voltage and maximum allowable reverse voltage of the gate, respectively. It is something.

-E It is desirable to provide a hand stomp filter on the gate input side of the amplifier for suppressing even-order high 3l1 waves of {3゛4.

``Example'' An example of the present invention is shown in the first row of the first page, and parts corresponding to those in FIG. do. In this invention, a terminal L is connected to the gate input side of the transistor Q.
M is provided, so that the gate voltage ■, is a trapezoidal wave whose positive and negative peaks are the maximum allowable forward voltage (e.g. 0.7V) and the maximum allowable reverse voltage (e.g. -7V) of the gate I, respectively. Set to less than or equal to .

The gate is connected via the diode D1 to a voltage corresponding to the positive peak voltage of the limiter output. Power terminal P to which is supplied
A power supply terminal PW is connected to WU and is supplied with a voltage VL2 corresponding to the negative peak voltage of the liminter output via a diode {)7 (opposite to the diode D1).
Connected to 4. Power terminal PW. ．． PW4 is a bypass capacitor C. to short-circuit harmonic signals. ,C
, is grounded through. These diotes'D,,D
．． , capacitor C■C, etc. ξ冫ゆLMfJ
INy will be destroyed. In this example, the gate is connected to the coil L.
and a resistor, Rc, are connected to the power supply terminal PWI via I+li, and the coil L. The connection point between and resistor R is grounded via a bypass capacitor C to prevent the gate input signal from being branched to the gate bias circuit and resulting in loss.

FIG. 2 shows the waveforms of the main parts of the circuit shown in FIG. In order to make the output voltage of the Riminota LM close to a square wave, the amplitude of the human voltage V in is chosen to be sufficiently larger than that of the Riminota output voltage. Since the Riminok output voltage becomes a trapezoidal wave and the peak value of the voltage is set close to the maximum allowable voltage of the gate, the drain voltage vl, is ■. . -1
．． It is a trapezoidal wave that oscillates in the range of 0 to 20V with OV as the center, and has a waveform that is closer to a rectangular wave than the conventional one.

Amplifier input power P. Output power P when changing
0, electric efficiency η. FIG. 3 shows changes in the gate current 16. The gate current characteristics shown by the dotted line in the same figure are those of the conventional example shown in FIG. When approaches Pil, the gate current IG becomes a negative current (flows from the source to the gate)
to a forward current (flowing from the gate to the source), and reaches the permissible forward current value of 1 cmaX at the input power P1. Therefore, human power P. cannot be increased any further, and the maximum output and maximum efficiency are P0, . is limited to η1. (In this example, the peak value of negative current is the tolerance value 1, si
This is a case where the input power is limited by one power line without exceeding n. ) However, in the same circuit shown in FIG. 1, the positive and negative peak values of the gate current are suppressed to be sufficiently smaller than in the conventional example due to the action of the beam ξ-interval LM, and the allowable {fit. , may ,
It never exceeds lc +*in. Therefore, the same applies to gate voltage (2)9. Human Power P. For example, Pi. (>Pi.
), at which time the maximum output P. z
(>po1) is obtained. To give a numerical example, ηl-7
0%, η2=80%Po+=28. 5dB, ,
Poz=30dB. It's like this.

As shown by the dotted line in FIG. 1, it is desirable to provide a Trump circuit (generally a bandstop filter) N1 at the gate of the transistor Q for bypassing even harmonics. In this example, the trap circuit TC is constructed from a series circuit of a distributed constant line N having a fundamental wave of λ/4 and a DC blocking capacitor C7. In addition, capacitor C
, also serves as a bypass for the harmonic signal.

Now, let us consider the case where the Trumble circuit TC is piggybacked.

When the input signal contains two sine waves (r, .ft) with similar frequencies, the nonlinearity of the LM causes even-order harmonics 01 (2f..4f.・;2
h. 4r2,...) will also occur. These even-order harmonics are combined with the fundamental wave by the nonlinear operation of the FET, and the frequencies 2r, -r, which are close to the fundamental wave frequency r,,r2. 2f,
-f. An intermodulation wave with . This is: next tt
l Ti. This is also known as the A-key distortion component.

These circumference gj. #! i. Since the fundamental wave frequency is close to 2, it is difficult to separate it.
The loop 'rC is for this purpose.

"Effect of Start 1" According to the present invention, a limiter is provided on the gate input side of the F FET, and the input gate voltage is either its positive and negative peak values or the positive and negative allowable values of the gate voltage are \\. It is possible to make the drain voltage V much closer to a rectangular wave than in the past by converting it into a trapezoidal wave of equal or smaller magnitude. As a result, drain loss is reduced, and a class F amplifier with higher power efficiency than before can be realized.

If a van 1' stop filter for suppressing even-order harmonics is provided at the gate input (Q+1), the intermodulation distortion of the intensifier output can be greatly improved.

[Brief explanation of the drawing]

Figure 1 is from this! A circuit diagram showing the embodiment of II, Fig. 2 is a waveform diagram of the main part of Fig. 1, and Fig. 3 shows the output power, power supply efficiency, and gate current when changing the human power in the embodiment of Fig. 1. Figure 4 is a circuit diagram of a conventional high-efficiency amplifier, Figure 5 is a waveform diagram of the main part of Figure 4, and Figures 6 to 8 are diagrams showing changes in the drain voltage of the FET in Figure 4. . Against drain current! . The locus of the pair (V..!) drawn on the static characteristic diagram of
12 shows corresponding drain current waveforms and drain iKJ waveforms.

Claims (2)

[Claims] (1) As an output load circuit for the drain of a source-grounded type FET amplifier circuit whose gate is biased approximately at the pinch-off voltage, the input impedance seen from the drain side represents a resistive load at the frequency of the fundamental wave of the input signal, and the even-order In an FET amplifier, a harmonic reflection circuit is connected which is almost short-circuited and opened at odd-order harmonic frequencies, respectively, and a limiter is provided on the gate input side to adjust the positive and negative peak values of the gate voltage. A high-efficiency amplifier characterized in that the voltages are clipped to values approximately equal to or less than the maximum allowable forward voltage and maximum allowable reverse voltage of the gate, respectively. (2) The high-efficiency amplifier according to claim (1), further comprising a bandstop filter provided on the gate input side for suppressing even harmonics of the input signal.