JP2001275342A - Dc-voltage converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC-voltage converting circuit, capable of reducing response delays in a feedback loop and stabilizing output voltage. SOLUTION: This converting circuit includes a differential voltage generating means (22) for generating differential voltage between detected voltage of the output voltage, in which DC-voltage supplied by a DC power source is stepped vertically and a reference voltage, a comparing means (28) for comparing the differential voltage with a ramp waveform signal and generating a switching pulse of a duty ratio which corresponds to the differential voltage, and a slow start means (30) for generating a slow start signal of fall waveform voltage which falls gradually from prescribed voltage when power source is turned on, supplying the signal to the comparison means 28 instead of the differential voltage, and increasing the duty ratio of the switching pulse gradually. Thus the response delay in the feedback loop can be reduced and stabilize the output voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC voltage conversion circuit, and more particularly, to a DC voltage conversion circuit that steps up or down a DC voltage and outputs the resulting DC voltage.

[0002]

2. Description of the Related Art Conventionally, a so-called DC / DC, which boosts (or steps down) a DC voltage output from a battery or the like, and outputs the same.
There is a DC voltage conversion circuit called a converter.

FIG. 4 is a circuit diagram showing an example of a conventional DC voltage conversion circuit. In the figure, a negative electrode of a DC power supply E1 such as a battery is grounded, and a positive electrode is connected to one end of a coil L1. The other end of the coil L1 is a Schottky diode SD
1 and a switching P
It is connected to the drain of the channel MOS transistor M1. The source of the MOS transistor M1 is grounded. The cathode of the Schottky diode SD1 is connected to the output terminal 10, and the output terminal 10 is grounded via the capacitor C1 and connected in series with the resistor R
1, R2.

The resistors R1 and R2 divide the voltage at the output terminal 10, and the detection voltage at the output terminal 10 taken out from the connection point between the resistors R1 and R2 is supplied to the non-inverting input terminal of the differential amplifier 12. . The reference voltage Vref is applied to the inverting input terminal of the differential amplifier 12 from the positive electrode of the reference power supply E2 whose negative electrode is grounded, and the differential amplifier 12 outputs the difference voltage between the detection voltage and the reference voltage Vref. . The difference voltage output from the differential amplifier 12 is inverted by the inverting amplifier 14 and supplied to the first non-inverting input terminal of the comparator 18.

A constant frequency sawtooth wave generated by an oscillator (OSC) 16 is supplied to an inverting input terminal of a comparator 18. Generates a switching pulse that is high when the voltage is higher than the sawtooth voltage of the inverting input terminal and low when the difference voltage is lower than the sawtooth voltage, and supplies the switching pulse to the gate of the MOS transistor M1.

For this reason, when the voltage at the output terminal decreases and the inverted difference voltage indicated by the dashed line in FIG. 5A becomes higher than the sawtooth voltage indicated by the solid line, the comparator 18
5B, the duty ratio of the switching pulse shown in FIG. 5B is increased, and the voltage of the output terminal is increased.

On the other hand, a resistor R3 is connected to the positive electrode of the reference power source E2.
Is connected to the other end of the resistor R3, the other end of the resistor R3 is grounded via the capacitor C2, and is connected to the second non-inverting input terminal of the comparator 18. The above resistor R3 and capacitor C2 constitute a soft start circuit. Without this soft start circuit, when the power is turned on, the voltage at the output terminal is close to 0 and the duty ratio of the switching pulse is maximized. Therefore, the voltage at the output terminal 10 overshoots as shown by the solid line in FIG. Occurs. This is particularly noticeable at light loads. If a soft start circuit is used, the voltage of the second non-inverting input terminal of the comparator 18 gradually rises by charging the capacitor C2 when the power is turned on, so that the duty ratio of the switching pulse gradually increases from the minimum, and the voltage of the output terminal 10 Gradually rises without overshoot as shown by the broken line in FIG.

[0008]

Since the above-described conventional DC voltage conversion circuit uses the inverting amplifier 14, the response delay in the feedback loop constituted by the differential amplifier 12, the inverting amplifier 14, the comparator 18, and the like. Is large and the output terminal 10
Cannot follow the voltage fluctuation at high speed and output terminal 1
This may cause unstable operation such as oscillation of a voltage of 0.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a DC voltage conversion circuit capable of reducing a response delay in a feedback loop and stabilizing an output voltage.

[0010]

According to a first aspect of the present invention, there is provided a differential voltage generating means for generating a differential voltage between a detection voltage of an output voltage obtained by increasing or decreasing a DC voltage supplied from a DC power supply and a reference voltage. (22) comparing means (28) for comparing the difference voltage with the ramp waveform signal to generate a switching pulse having a duty ratio according to the difference voltage; and a driving means driven by the switching pulse and supplied from the DC power supply. Switching means for switching DC voltage (M1
1) and generating a slow start signal of a falling waveform voltage gradually decreasing from a predetermined voltage when the power is turned on, and supplying the same to the comparing means (28) instead of the differential voltage, thereby gradually increasing the duty ratio of the switching pulse. Slow start means (30) for increasing.

As described above, when the power supply is turned on, the slow start signal of the falling waveform voltage which gradually decreases from the predetermined voltage is generated and supplied to the comparing means (28) instead of the differential voltage. 22) and comparison means (28)
The signal inverting circuit (14) required between the two can be eliminated, and the delay due to the inverting circuit (14) can be eliminated, so that the response delay in the feedback loop can be reduced and the output voltage can be stabilized. Can be

The reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0013]

FIG. 1 is a circuit diagram showing a first embodiment of a DC voltage conversion circuit according to the present invention. In the figure, a negative electrode of a DC power source E11 such as a battery is grounded, and a positive electrode is a coil L1.
1 is connected to one end. The other end of the coil L11 is connected to the anode of the Schottky diode SD11 and to the drain of the switching P-channel MOS transistor M11. The source of the MOS transistor M11 is grounded. The cathode of the Schottky diode SD11 is connected to the output terminal 20, and the output terminal 20 is grounded via the capacitor C11 and also grounded via the resistors R11 and R12 connected in series.

The resistors R11 and R12 divide the voltage at the output terminal 20, and the detection voltage at the output terminal 20 extracted from the connection point between the resistors R11 and R12 is supplied to the non-inverting input terminal of the differential amplifier 22. The reference voltage Vref is applied to the inverting input terminal of the differential amplifier 22 from the positive electrode of the reference power supply E12 whose negative electrode is grounded.
2 outputs a difference voltage between the detection voltage and the reference voltage Vref. The difference voltage output from the differential amplifier 22 is supplied to a first inverting input terminal of the comparator 28.

A non-inverting input terminal of a comparator 28 is supplied with a sawtooth wave having a constant frequency generated by an oscillator (OSC) 26. Generates a switching pulse which is high when the voltage is higher than the sawtooth voltage of the non-inverting input terminal and becomes low when the difference voltage is lower than the sawtooth voltage, and supplies the switching pulse to the gate of the MOS transistor M11.

On the other hand, the positive electrode of the reference power supply E12 is grounded via resistors R13 and R14 connected in series, and is also grounded via a resistor R15 and a capacitor C12 connected in series. The connection point between the resistors R13 and R14 is connected to the non-inverting input terminal of the differential amplifier 24 via the resistor R16, and the connection point between the resistor R15 and the capacitor C12 is connected to the inverting input terminal of the differential amplifier 24. The resistor R17 is connected between the output terminal and the inverting input terminal of the differential amplifier 24, and the output terminal of the differential amplifier 24 is connected to the second non-inverting input terminal of the differential amplifier 28. The above resistor R1
3-R17, capacitor C12 and differential amplifier 24 constitute a soft start circuit.

FIG. 2 is a circuit diagram of one embodiment of the comparator 28. In the figure, a first inverted input terminal 31 is connected to an output terminal of the differential amplifier 22, a second inverted input terminal 32 is connected to an output terminal of the differential amplifier 24, and a non-inverted input terminal 3 is connected.
3 is connected to the output terminal of the oscillator 26, and these are connected to the respective bases of the pnp transistors Q1, Q2, Q3. The emitters of the transistors Q1, Q2, Q3 are commonly connected and connected to a power supply Vcc via a constant current source.

The collectors of the transistors Q1 and Q2 are commonly connected and connected to the collector of an npn transistor Q4, and the collector of the transistor Q3 is connected to the collector of an npn transistor Q5. Transistor Q4
The base of Q5 is commonly connected and the transistor Q4
And the emitters of the transistors Q4 and Q5 are grounded. An output terminal 35 is provided at the collector of the transistor Q5, and is connected to the gate of the MOS transistor M11.

Here, the voltage of the output terminal 20 decreases,
When the differential voltage output from the differential amplifier 22 becomes lower than the sawtooth voltage, the duty ratio of the switching pulse output from the comparator 18 increases, and the voltage at the output terminal 20 is controlled to increase. When the voltage of the output terminal 20 becomes high, the voltage of the output terminal 20 is controlled to be low by the reverse operation.

In the soft start circuit, when the power is turned on, the capacitor C12 is charged and gradually rises, and the voltage (soft start signal) output from the differential amplifier 24 rises from a predetermined voltage [= E12 · R14 / (R13 + R14)]. Since the voltage gradually falls with a constant τ (= C12 · R15 · R17 / R16), the duty ratio of the switching pulse output from the comparator 28 gradually increases from the minimum, and the voltage of the output terminal 20 does not cause overshoot. Get up slowly.

In the present embodiment, the conventional inverting amplifier 14 can be eliminated by gradually lowering the soft start signal from a predetermined voltage, whereby the differential inverting amplifier 22 and the comparator 28 are constituted. The response delay in the feedback loop can be reduced, and the output voltage can be stabilized.

FIG. 3 is a circuit diagram showing a second embodiment of the DC voltage conversion circuit according to the present invention. In the figure, a DC power source E such as a battery is shown.
The negative electrode 11 is grounded, and the positive electrode is connected to one end of the coil L11. The other end of the coil L11 is connected to the anode of the Schottky diode SD11 and to the drain of the switching P-channel MOS transistor M11. MOS transistor M11
Is grounded at the source. Schottky diode S
The cathode of D11 is connected to the output terminal 20, and the output terminal 20 is grounded via a capacitor C11 and also grounded via resistors R11 and R12 connected in series.

The resistors R11 and R12 divide the voltage at the output terminal 20, and the detection voltage at the output terminal 20 extracted from the connection point between the resistors R11 and R12 is supplied to the non-inverting input terminal of the differential amplifier 22. The reference voltage Vref is applied to the inverting input terminal of the differential amplifier 22 from the positive electrode of the reference power supply E12 whose negative electrode is grounded.
2 outputs a difference voltage between the detection voltage and the reference voltage Vref. The difference voltage output from the differential amplifier 22 is supplied to the base of the npn transistor Q10. The transistor Q10 has a collector connected to the output terminal 20 and an emitter grounded via the resistor R18 to form an emitter follower circuit. The emitter voltage of the transistor Q10 is supplied to the first inverting input terminal of the comparator 28. . The first inverting input terminal of the comparator 28 and the second
The inverting input terminal is short-circuited.

A non-inverting input terminal of a comparator 28 is supplied with a sawtooth wave having a constant frequency generated by an oscillator (OSC) 26. Generates a switching pulse which is high when the voltage is higher than the sawtooth voltage of the non-inverting input terminal and becomes low when the difference voltage is lower than the sawtooth voltage, and supplies the switching pulse to the gate of the MOS transistor M11.

On the other hand, the positive electrode of the reference power source E12 is grounded via resistors R13 and R14 connected in series, and grounded via a resistor R15 and capacitor C12 connected in series. The connection point between the resistors R13 and R14 is connected to the non-inverting input terminal of the differential amplifier 24 via the resistor R16, and the connection point between the resistor R15 and the capacitor C12 is connected to the inverting input terminal of the differential amplifier 24. The resistor R17 is connected between the output terminal and the inverting input terminal of the differential amplifier 24, and the output terminal of the differential amplifier 24 is connected to the second non-inverting input terminal of the differential amplifier 28. The above resistor R1
3-R17, capacitor C12 and differential amplifier 24 constitute a soft start circuit.

In the circuit configuration shown in FIG. 1, when the soft start signal gradually falls from a predetermined voltage, the transistor Q2 shown in FIG.
Is a value obtained by adding Vbe (the voltage drop between the base and the emitter of the transistor) to the soft start signal voltage, and the collector voltage of the transistor Q2 is about 0.2 V (on-resistance of the transistor) lower than the emitter voltage. Then, the transistor Q4 cannot operate.

However, in the circuit configuration of FIG.
12 is grounded via resistors R15, R16, R17, R18, the base voltage of the transistor Q2 forming the comparator 28 is set to a predetermined voltage [= E12 · R
18 / (R15 + R16 + R17 + R18)] or less. Therefore, it is possible to prevent the transistor Q4 from becoming inoperable, and it is possible to always perform a normal operation.

[0028]

As described above, the first aspect of the present invention provides
When a power supply is turned on, a slow start signal of a falling waveform voltage that gradually decreases from a predetermined voltage is generated and supplied to the comparing means instead of the differential voltage. Since the signal inverting circuit, which has been used, can be eliminated, and the delay caused by the inverting circuit can be eliminated, the response delay in the feedback loop can be reduced, and the output voltage can be stabilized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of a DC voltage conversion circuit of the present invention.

FIG. 2 is a circuit diagram of one embodiment of a comparator 28.

FIG. 3 is a circuit configuration diagram of a second embodiment of the DC voltage conversion circuit of the present invention.

FIG. 4 is a circuit configuration diagram of an example of a conventional DC voltage conversion circuit.

FIG. 5 is a diagram for explaining a switching operation of the DC voltage conversion circuit.

FIG. 6 is a diagram showing a voltage waveform of an output terminal 10;

[Explanation of symbols]

 E11 DC power supply L11 Coil SD11 Schottky diode M11 MOS transistor C11 Capacitors R11 to R18 Resistance E12 Reference power supply 22, 24 Differential amplifier 26 Oscillator 28 Comparator

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (1)

[Claims] 1. A difference voltage generating means for generating a difference voltage between a reference voltage and a detection voltage of an output voltage obtained by stepping up or stepping down a DC voltage supplied from a DC power supply, and comparing the difference voltage with a ramp waveform signal. A comparison unit that generates a switching pulse having a duty ratio according to the difference voltage; a switching unit that is driven by the switching pulse and switches a DC voltage supplied from the DC power supply; A slow start means for generating a slow start signal of a falling waveform voltage and supplying the slow start signal to the comparing means instead of the differential voltage, and gradually increasing a duty ratio of the switching pulse. circuit.