JP2001274392A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an LDMOS transistor with improved breakdown voltage. SOLUTION: A drift region forming process in the manufacturing step for the semiconductor device includes a step for implanting phosphorous ion and arsenic ion with different diffusion constant in a surface layer of the substrate, a step for forming a selective oxide film (first gate insulating film) 9A and an element isolation film 9B by selective oxidation, a step for diffusing the phosphorous ion and arsenic ion, and a step for implanting boron ion and diffusing the boron ion. In a step for forming the selective oxide film 9A and the element film 9B, the selective oxidation process is carried out in a laminated state of the oxide film and the polysilicon film. In this case, only the drift-region formation region is selectively oxidized in a state that the polysilicon has been removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to an LD (Lateral Double) as a high-voltage element used in, for example, a liquid crystal driving IC.
Diffused) MOS transistor technology.

[0002]

2. Description of the Related Art Here, the LDMOS transistor structure means that a diffusion region formed on the surface side of a semiconductor substrate is diffused with an impurity having a different conductivity type to form a new diffusion region. The difference in the lateral diffusion is used as the effective channel length. By forming a short channel, the element is suitable for low on-resistance.

FIG. 20 is a cross-sectional view for explaining a conventional LDMOS transistor, and shows an N-channel type LDMOS transistor structure as an example. Although the description of the structure of the P-channel LDMOS transistor is omitted, it is well known that the structure is the same except for the conductivity type.

In FIG. 20, reference numeral 1 denotes one conductivity type, for example, P
A semiconductor substrate (P-Sub) 2 is an N-type well region (N-well). A P-type body (PB) region 3 is formed in the N-type well region 2 and a P-type body region 2 is formed. An N + type diffusion region 4 is formed in 3, and an N + type diffusion region 5 is formed in the N type well region 2.
A gate electrode 7 is formed on the surface of the substrate with a gate insulating film 6 interposed therebetween. A channel region 8 is formed in a surface region of the P-type body region 3 immediately below the gate electrode 7.

The N + type diffusion region 4 is a source region, the N + type diffusion region 5 is a drain region, and the N type well region 2 formed so as to surround the drain region from the gate electrode 7 is a drift region. . Also,
S, G, and D are a source electrode, a gate electrode, and a drain electrode, respectively, 12 is a P + type diffusion region for taking the potential of the P type body region 3, and 11 is an interlayer insulating film.

In the above LDMOS transistor,
By forming the N-type well region 2 by diffusion, the concentration on the surface of the N-type well region 2 is increased, so that the current easily flows on the surface of the N-type well region 2 and the breakdown voltage can be increased. The LDMOS transistor having such a configuration is called a surface relaxation type (RESURF) LDMOS, and the dopant concentration of the drift region of the N-type well region 2 is set so as to satisfy the RESURF condition. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 9-139438.

[0007]

However, FIG.
As shown in (1), the N-type well region 2 is uniformly formed to the same depth position, which hinders further increase in breakdown voltage and reduction in on-resistance.

Accordingly, the present invention provides a semiconductor device which can meet the demand for higher withstand voltage and lower on-resistance, and furthermore, by optimizing a manufacturing method thereof, enables a higher withstand voltage. With the goal.

[0009]

In order to achieve the above object, according to the present invention, there is provided a semiconductor device having a gate electrode formed on a semiconductor substrate via first and second gate insulating films having different thicknesses. In the device, the step of forming a drift region includes at least two types of impurities of the same conductivity type having different diffusion coefficients, and a diffusion coefficient substantially equal to or greater than a diffusion coefficient of one of the two types of impurities. A step of utilizing a difference in diffusion coefficient with an impurity of the opposite conductivity type having an impurity to implant ions so as to be shallow below the gate electrode and deep near the drain region.

Further, the method of manufacturing a semiconductor device according to the present invention comprises:
The step of forming a drift region includes a step of ion-implanting at least two types of second conductivity type impurities having different diffusion coefficients into a substrate surface layer, and forming a first gate insulating film and an element isolation film by selective oxidation. Two kinds of second
Diffusing conductive type impurities, and ion-implanting at least one or more first conductive type impurities having a diffusion coefficient substantially equal to or higher than at least one or more of the second conductive type impurities. Diffusing, wherein the step of forming the first gate insulating film and the element isolation film selectively oxidizes in a state where an oxide film and a polysilicon film or an oxide film and an amorphous silicon film are stacked on a substrate. Selectively oxidizing the drift region forming region only after removing the polysilicon film or the amorphous silicon film, wherein impurities implanted in the drift region forming region are subjected to the first gate insulating film formation when forming the first gate insulating film. By properly incorporating it into the gate insulating film, the impurity concentration in the drift region on the substrate surface can be reduced. That.

Further, in the semiconductor device according to the present invention, the drift region is formed to be shallow below the gate electrode and deep near the drain region, and the drift region has an impurity concentration of the second region. It is characterized in that it is lower under the first gate insulating film thicker than the gate insulating film and lower than under the second gate insulating film. According to this configuration, the arsenic ion concentration under the first gate insulating film (selective oxide film 9A) does not decrease sufficiently, and the selective oxide film 9
The concentration of the first N- layer 22A under A is increased, and it is possible to prevent the operating withstand voltage from being reduced due to electric field concentration.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view for explaining an LDMOS transistor of the present invention, and shows an N-channel type LDMOS transistor structure as an example.
Although the description of the structure of the P-channel LDMOS transistor is omitted, it is well known that the structure is the same except for the conductivity type. The same components as those in the conventional configuration are denoted by the same reference numerals, and the description will be simplified.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate (P-Sub) of one conductivity type, for example, a P-type, and 21 denotes a P-type well region (P-well). 2
2 are formed, and a P-type body (PB) region 3 is formed. Further, N +
A diffusion region 4 is formed, and an N + diffusion region 5 is formed in the N− layer 22.

Further, the selective oxidation film 9A (first
A gate electrode 7 is formed so as to extend over the gate insulating film 6) and the gate oxide film 6 (the second gate insulating film), and a channel region 8 is formed in the surface region of the P-type body region 3 immediately below the gate electrode 7. Are formed.

The N + type diffusion region 4 is a source region, the N + type diffusion region 5 is a drain region, and the N− layer 22 formed so as to surround the gate electrode 7 and below the drain region is a drift region. Although not shown, the source electrode S and the drain electrode D are formed so as to be in contact with the N + type diffusion regions 4 and 5 in the same manner as in the conventional configuration. P-type diffusion region 12 for taking the potential of mold body region 3
Is formed and covered with an interlayer insulating film 11.

The feature of the above structure is that, as described above, the N- layer 22 is formed in the P-type well region 21 and the N- layer 22 is formed.
Is formed shallow (first N− layer 22A) below the gate electrode 7 and deep (second N− layer 22A) near the drain region 5.
B) It is formed (see FIG. 1).

As a result, the concentration of the first N− layer 22A formed shallowly below the gate electrode 7 is formed to be high, so that the on-resistance becomes small and the current easily flows, and the vicinity of the drain region 5 ( Drift area position)
Since the concentration of the N− layer 22B is low, the depletion layer easily expands, and a high breakdown voltage can be achieved (see the concentration distribution diagram shown in FIG. 9). Note that the N-channel type LDM of the present embodiment is
The OS transistor has a withstand voltage of about 30 V.

Hereinafter, a method of manufacturing the above-described semiconductor device will be described with reference to the drawings.

In FIG. 2, after a pad oxide film 29 is formed on a P-type semiconductor substrate 1, an N- layer 22 which will become a drift region in a later step is formed in a P-type well region 21 using a photoresist film (PR) as a mask. The first and second ion-implanted layers 32 and 33 are formed by ion-implanting two types of N-type impurities (for example, arsenic ions and phosphorus ions) for forming GaAs.

In this step, for example, arsenic ions are implanted at an acceleration voltage of about 160 KeV and at an injection amount of 3 × 10 ¹² / cm ² , and phosphorus ions are implanted at an acceleration voltage of about 50 KeV and 4 × 10 ¹² / cm 2. Perform under the injection condition of ² .

Next, referring to FIG. 3, a polysilicon film 30 is formed on a pad oxide film 29 on the substrate 1 and a silicon nitride (SiN) film 31 formed on the polysilicon film 30 is used as a mask. Selectively oxidize the region to about 730
A selective oxide film 9A and an element isolation film 9B having a thickness of about nm are formed, and arsenic ions and phosphorus ions implanted into the surface layer of the substrate are diffused into the substrate as described above. At this time, the arsenic ions are diffused into the substrate 1 due to the difference in diffusion coefficient between arsenic ions and phosphorus ions, forming a first N− layer 22A relatively on the surface of the substrate. The second N− layer 22B is diffused to a relatively deep position in the P-type well region 21.
Is formed.

Subsequently, in FIG. 4, after a photoresist film (PR) is formed on the substrate 1 on the drain formation region, a P-type impurity (for example, , Boron ions) are implanted and diffused, so that the phosphorus ions forming the second N − layer 22B of the source forming region are offset by the boron ions, so that the second
Of the N− layer 22B.

In this step, for example, boron ions are implanted at an acceleration voltage of about 80 KeV at a dose of 8 × 10 ¹² / cm ² and then thermally diffused at about 1100 ° C. for 2 hours. Here, FIG. 9 is a diagram showing the impurity concentration distributions of the arsenic ion (shown by a solid line), the phosphorus ion (shown by a dashed line), and the boron ion (shown by a dotted line). Is superimposed with the concentration distribution having boron ions as a parent and is offset.

As described above, in the present invention, when forming the drift region, the difference between the diffusion coefficients of arsenic ions and phosphorus ions having different diffusion coefficients is utilized to form the second N formed deep in the substrate near the source formation region. The layer 22B is offset by ion-implanting and diffusing boron ions implanted in a later step, so that only the first N-layer 22A formed on the surface of the substrate remains on the source forming region side. In addition, a semiconductor device with reduced on-resistance can be provided by a relatively simple manufacturing process.

Next, in FIG. 5, after a gate oxide film 6 having a thickness of about 80 nm is formed on the substrate 1, the gate oxide film 6 has a thickness of about 250 nm so as to extend over the selective oxide film 9 A. The gate electrode 7 having a thickness of 5 nm is formed.

Subsequently, referring to FIG.
And a P-type impurity (for example, using a photoresist film (PR) formed so as to cover the drain formation region as a mask.
By implanting and diffusing boron ions, a P-type body region 3 is formed adjacent to one end of the gate electrode 7.

In this step, for example, boron ions are implanted at an acceleration voltage of about 40 KeV at a dose of 5 × 10 ¹³ / cm ² and then thermally diffused at about 1050 ° C. for 2 hours.

Further, in FIG. 7, using a photoresist film (PR) having openings on the source forming region and the drain forming region formed in the P-type body region 3 as a mask, N-type impurities (for example, phosphorus ions or Arsenic ions are implanted to form N + type diffusion regions 4 and 5 which will be source / drain regions.

The N + type diffusion regions 4 and 5 may have a so-called LDD structure. In this case, first, the gate electrode 7, the selective oxide film 9A, and a photoresist film (not shown) are used as a mask. For example, about 4
After implanting at an acceleration voltage of 0 KeV at an implantation rate of 3.5 × 10 ¹³ / cm ^2, a sidewall spacer film is formed at the side end of the gate electrode 7, and the sidewall spacer film, the gate electrode 7, Using the selective oxide film 9A and a photoresist film (not shown) as a mask, for example, arsenic ions are implanted at an acceleration voltage of about 80 KeV and at a dose of 5 × 10 ¹⁵ / cm ² .

In FIG. 8, in order to form a P-type diffusion region 12 formed at a position adjacent to the N-type diffusion region 4 in order to take the potential of the P-type body region 3,
Using the photoresist film (PR) as a mask, a P-type impurity (for example, boron difluoride ion) is implanted to form the P-type diffusion region 12. In this step, for example, boron difluoride ions are treated at an acceleration voltage of about 60 KeV for 4 times.
The injection is performed at an injection amount of × 10 ¹⁵ / cm ² .

After forming the interlayer insulating film 11 in the same manner as in the conventional structure, the source electrode S and the drain electrode D are formed to complete the semiconductor device shown in FIG.

As described above, in the semiconductor device having the above structure, when forming the drift region, two kinds of second conductivity type impurities (phosphorus ions and arsenic ions) having different diffusion coefficients are used.
By making use of the difference between the diffusion coefficient of boron ions and the diffusion coefficient of phosphorus ions which are substantially the same as the diffusion coefficient of phosphorus ions, the gate electrode 7 is formed shallow under the gate electrode 7 and deep near the drain region 5 to increase the breakdown voltage and The on-resistance can be reduced.

Next, another embodiment of the present invention will be described with reference to the drawings.

A feature of the present invention is to achieve a higher breakdown voltage than the semiconductor device having the above configuration by further optimizing the manufacturing process when the drift region has a double structure of phosphorus ions and arsenic ions. It was done.

First, the inventor has noticed that the concentration of the first N-layer 22A made of arsenic ions is higher than the predicted value in the above structure.

The present inventor has proposed that the selective oxidized film 9A formed by the polybuffer drocos method, which improves the above phenomenon and the so-called locos method applied to the process and suppresses bird's beak growth and alleviates stress, can be used. It has been found that this is related to the forming process.

In the polybuffer drocos method, an oxide film and a polysilicon film (or an oxide film and amorphous silicon may be stacked) on a substrate, and an oxidation resistant film having a predetermined opening formed thereon. (SiN film or the like) is used as a mask to thermally oxidize the polysilicon film or the substrate under the opening to grow an oxide film.

When this method is used, arsenic ions implanted near the substrate interface in the step of forming the selective oxide film 9A are not sufficiently taken into the selective oxide film 9A, and as a result, the arsenic ions are not as expected. It was considered that the low concentration did not occur. That is, due to the presence of the polysilicon film laminated on the oxide film on the substrate by the polybuffer drocos method, the polysilicon film is oxidized earlier than the substrate during the LOCOS oxidation.

As a result, the arsenic ions diffuse into the substrate during this time, and the concentration of the arsenic ions under the selective oxide film 9A does not decrease sufficiently. In fact, as shown by the dotted line in FIG. As a result, the concentration of the first N- layer 22A under the oxide film 9A is increased, and the operation withstand voltage is reduced due to electric field concentration.

Therefore, in the manufacturing method of the present invention, the selective oxidation step is performed with the polysilicon film used in the polybuffer drocos method removed only in the drift region forming region.

That is, in FIG. 10, the P-type semiconductor substrate 1
A pad oxide film 29 and a polysilicon film 30 are formed thereon, and the polysilicon film 3 is formed using a photoresist film PR.
After forming an opening in the predetermined region of the P-type well region 2,
1, the polysilicon film 30 and the photoresist film 31
Layer 22 serving as a drift region in a later step using
The first and second ion-implanted layers 32 and 33 are formed by ion-implanting two types of N-type impurities (for example, arsenic ions and phosphorus ions) for forming GaAs.

In this step, for example, arsenic ions are implanted at an acceleration voltage of about 160 KeV and at a dose of 3 × 10 ¹² / cm ² , and phosphorus ions are implanted at an acceleration voltage of about 50 KeV and 4 × 10 ¹² / cm 2. Perform under the injection condition of ² .

Next, in FIG. 11, an oxidation resistant (SiN) film 3 formed on the substrate 1 including the polysilicon film 30 is formed.
By using 1 as a mask, a predetermined region on the substrate surface is selectively oxidized by a polybuffer drocos method to form a selective oxide film 9A having a thickness of about 600 nm and an element isolation film 9B having a thickness of about 730 nm. During this selective oxidation,
As described above, the arsenic ions are diffused into the substrate 1 from the difference between the diffusion coefficients of arsenic ions and phosphorus ions implanted into the substrate surface layer, and the first N-
A layer 23A is formed, and the phosphorus ions are
The second N− layer 23B is formed at a relatively deep position in the P-type well region 21 by being diffused inside.

Here, the present step is a step which is a feature of the present invention, and includes the drift region 23 (the first N− layer 23 A, the second
When the N− layer 23B) is formed, the selective oxidation is performed in a state where the polysilicon film 30 on the drift region formation region is removed, so that when the selective oxide film is formed as in the related art, the selective oxidation is performed. Arsenic ions that should be taken into the oxide film and reduced in concentration are not diffused into the substrate more than necessary, and a desired concentration distribution can be obtained.

FIG. 18 is a diagram showing an impurity concentration distribution of phosphorus ions and arsenic ions in the drift region formed by the first manufacturing method. Similarly, FIG. 19 is a diagram showing phosphorus ions in the drift region formed by the second manufacturing method. FIG. 4 is a diagram showing impurity concentration distributions of arsenic ions and arsenic ions. As can be seen from this figure, the impurity concentration of arsenic ions near the substrate surface is lower in the drift region formed by the second manufacturing method than in the drift region formed by the first manufacturing method.

More specifically, the thickness of the selective oxide film 9A is slightly smaller than the thickness of the element isolation film 9B, but the thickness of the selective oxide film 9A is required to be as large as that of the element isolation film 9B. There is no such thing, and there is no problem in applying this process.

Thereafter, through the same steps as in the first manufacturing method (FIGS. 4 to 8), a semiconductor device according to the second manufacturing method is completed. That is, in FIG. 12, after a photoresist film (PR) is formed on the substrate 1 on the drain formation region, a P-type impurity (for example, boron ion) is formed on the surface of the substrate in the source formation region using the photoresist film as a mask.
Is implanted and diffused to offset the phosphorus ions forming the second N− layer 23B of the source forming region with the boron ions, thereby forming the second N− layer 23B of the source forming region.
The layer 23B is extinguished;

In this step, for example, boron ions are implanted at an acceleration voltage of about 80 KeV at a dose of 8 × 10 ¹² / cm ² , and then thermally diffused at about 1100 ° C. for 2 hours.

Next, in FIG. 13, after a gate oxide film 6 having a thickness of about 80 nm is formed on the substrate 1, the gate oxide film 6 has a thickness of about 250 nm over the selective oxide film 9 A. The gate electrode 7 having a thickness of 5 nm is formed.

Subsequently, in FIG. 14, a P-type impurity (for example, boron ion) is implanted and diffused by using a photoresist film (PR) formed so as to cover the gate electrode 7 and the drain formation region as a mask. A P-type body region 3 is formed adjacent to one end of the gate electrode 7.

In this step, for example, boron ions are implanted at an acceleration voltage of about 40 KeV at an implantation amount of 5 × 10 ¹³ / cm ² , and then thermally diffused at about 1050 ° C. for 2 hours.

Further, in FIG. 15, using a photoresist film (PR) having openings on the source formation region and the drain formation region formed in the P-type body region 3 as a mask, N-type impurities (for example, phosphorus ions or Arsenic ions are implanted to form N + type diffusion regions 4 and 5 which will be source / drain regions.

The N + type diffusion regions 4 and 5 may have a so-called LDD structure. In this case, first, the gate electrode 7, the selective oxide film 9A, and a photoresist film (not shown) are used as a mask. For example, about 4
After implanting at an acceleration voltage of 0 KeV at an implantation rate of 3.5 × 10 ¹³ / cm ^2, a sidewall spacer film is formed at the side end of the gate electrode 7, and the sidewall spacer film, the gate electrode 7, Using the selective oxide film 9A and a photoresist film (not shown) as a mask, for example, arsenic ions are implanted at an acceleration voltage of about 80 KeV and at a dose of 5 × 10 ¹⁵ / cm ² .

In FIG. 16, a photoresist film (PR) is formed to form a P-type diffusion region 12 formed at a position adjacent to the N-type diffusion region 4 in order to take the potential of the P-type body region 3. ) Is used as a mask to implant a P-type impurity (for example, boron difluoride ion).
A mold diffusion region 12 is formed. In this step, for example,
Boron difluoride ions are implanted at an acceleration voltage of about 60 KeV and at a dose of 4 × 10 ¹⁵ / cm ² .

Thereafter, as shown in FIG. 17, an interlayer insulating film 11 is formed in the same manner as in the conventional structure, a source electrode S and a drain electrode D are formed, and a semiconductor device is completed.

The operating withstand voltage of the semiconductor device formed as described above could be improved to about 40 V.

[0058]

According to the present invention, at least two types of impurities of the second conductivity type having different diffusion coefficients,
Forming a drift region using a difference in diffusion coefficient with at least one type of first conductivity type impurity having a diffusion coefficient substantially equal to or higher than that of at least one type of second conductivity type impurity; By properly adjusting the pressure, it is possible to further increase the breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a concentration distribution diagram of various ions for explaining the principle of forming a drift region according to the present invention.

FIG. 10 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 11 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 12 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 13 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 14 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 15 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 16 is a sectional view illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

FIG. 17 is a cross-sectional view illustrating the method for manufacturing the semiconductor device of the second embodiment of the present invention.

FIG. 18 is a concentration distribution diagram of various ions in a drift region.

FIG. 19 is a concentration distribution diagram of various ions in a drift region.

FIG. 20 is a sectional view showing a conventional semiconductor device.

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/94 A 29/78 301D (72) Inventor Yumiko 2-5-5 Keihanhondori, Moriguchi-shi, Osaka 3 F-term in Yo-Eki Corporation (reference) 4M108 AA02 AA09 AB04 AB10 AB13 AB16 AC01 AD07 AD13 5F032 AA13 AA18 CA03 CA17 DA43 DA47 DA53 5F040 DA00 DA22 EB01 EC19 ED09 EF01 EF02 EF13 EF18 EK01 EM01 FC17

Claims (11)

[Claims] A first and a second film having different thicknesses on a semiconductor substrate;
A gate electrode formed through the gate insulating film, and a source region formed to be adjacent to the gate electrode;
In a semiconductor device in which a drain region formed at a position separated from the source region and a drift region formed from the gate electrode to the drain region, the drift region is shallow below the gate electrode, And the impurity concentration of the drift region is lower under the first gate insulating film than under a second gate insulating film thinner than the first gate insulating film. A semiconductor device. 2. The semiconductor device according to claim 1, wherein the gate electrode is formed over a first gate insulating film and over a second gate insulating film thinner than the first gate insulating film. 2. The semiconductor device according to 1. 3. The semiconductor device according to claim 1, wherein said first gate insulating film is a selective oxide film formed by selective oxidation. 4. The semiconductor device according to claim 3, wherein a region excluding the surface of the selective oxide film and the surface of the drift region is formed by a selective oxidation method using a buffer droco method. 5. A method according to claim 1, wherein the first and second layers have different thicknesses on the semiconductor substrate.
A gate electrode formed through the gate insulating film, and a source region formed to be adjacent to the gate electrode;
In a method for manufacturing a semiconductor device in which a drain region is formed at a position separated from the source region and a drift region is formed from the gate electrode to the drain region, the step of forming the drift region differs at least in a diffusion coefficient. Utilizing a difference in diffusion coefficient between two types of impurities of the same conductivity type and an impurity of the opposite conductivity type having a diffusion coefficient substantially equal to or higher than the diffusion coefficient of one type of the two types of impurities, A method of implanting ions so as to be shallow below the gate electrode and deeper near the drain region. 6. The step of forming the drift region includes a first implantation step of implanting at least two types of second conductivity type impurity ions having different diffusion coefficients into a surface layer of the semiconductor substrate; and a step of selectively oxidizing the first gate. Forming an insulating film and an element isolation film; and at least one or more first conductivity type impurity ions having a diffusion coefficient substantially equal to or greater than that of at least one or more of the second conductivity type impurities. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising: a second implantation step of implanting a semiconductor. 7. The method according to claim 6, wherein the first implantation step includes an ion implantation step and a diffusion step, and the diffusion step is performed simultaneously with the step of forming the element isolation film. Of manufacturing a semiconductor device. 8. The first implantation step is a step of implanting arsenic ions and phosphorus ions, and the second implantation step is to cancel the phosphorus ions.
7. The method according to claim 6, further comprising the step of selectively implanting boron ions into a part of the arsenic and phosphorus implanted region. 9. The step of forming the first gate insulating film and the element isolation film by the selective oxidation includes the step of selectively oxidizing the oxide film and a polysilicon film or an oxide film and an amorphous silicon film on a substrate. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the method is a buffer drocos process. 10. An oxide film and an oxide film on a substrate such that the step of forming the first gate insulating film and the element isolation film removes the polysilicon film or the amorphous silicon film only in the drift region formation region. 10. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of selectively oxidizing the polysilicon film or the oxide film and the amorphous silicon film in a stacked state. 11. A step of forming an oxide film on the first conductivity type semiconductor layer, a step of forming a polysilicon film or an amorphous silicon film on the oxide film, and a step of forming the polysilicon film or the amorphous film in a drift region forming region. A step of removing the silicon film; a step of ion-implanting two types of second conductivity type impurities into the drift region forming region; and a mask of the oxidation-resistant film formed on the semiconductor layer including the polysilicon film or the amorphous silicon film. A desired region on the semiconductor layer is selectively oxidized to form a first gate insulating film and an element isolation film, and the two types of second
Forming a low-concentration second conductivity type layer at a relatively deep position in the semiconductor layer and at a relatively relatively high surface layer, respectively, based on a difference in diffusion coefficient between the conductivity type impurities; A first conductivity type impurity is ion-implanted and diffused into the surface of the semiconductor layer in the source formation region using the photoresist film formed in the above as a mask, thereby forming the source formation region at a relatively deep position in the semiconductor layer. A step of diffusing the second conductive type layer by diffusing the first conductive type impurity and a step of forming a second gate insulating film on the semiconductor layer except for a region where the first gate insulating film is formed Forming a gate electrode over the first insulating film and the second gate insulating film; and forming a first electrode through a mask formed so as to cover the gate electrode and the drain formation region. Forming a first conductivity type body region adjacent to one end of the gate electrode by injecting and diffusing a conductivity type impurity; and a source formation region and a drain formed in the first conductivity type body region. Forming a source / drain region by injecting a second conductivity type impurity through a mask having an opening on the formation region.