JP2001274363A - Non-volatile semiconductor memory device and producing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory device and a producing method therefor, with which write time can be shortened by setting a plurality of thresholds of a memory cell transistor with the same number of times of write. SOLUTION: A floating gate FG is selectively provided over two adjacent active regions AA and an element isolation region STI between them and while covering this floating gate FG, control gates CG1-CG16 are extended orthogonally with the active regions AA. In each of active regions AA, serially connected memory cell transistors M1-M16 are formed by providing impurity diffusion layers to become source and drain regions so as to sandwich the floating gate FG and the control gates CG1-CG16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly to a technique used for a nonvolatile semiconductor memory device that performs multi-level control.

[0002]

2. Description of the Related Art Conventionally, as a kind of semiconductor memory device, a flash EEPROM capable of electrically rewriting has been used.
(Electrically Erasable and Programmable Read Only
Memory) is known. Above all, a NAND flash EEPROM, in which a plurality of memory cells are connected in series to form a NAND cell, has attracted attention as being capable of high integration.

Conventional NAND Flash EEPROM
Will be described. FIG. 28 is a plan view of the NAND flash EEPROM. As shown in the figure, a plurality of device isolation regions STI
(Shallow Trench Isolation) is formed, and an active area AA (Active Area) for forming a semiconductor element is formed between adjacent element isolation areas STI. In the active region AA, a floating gate FG (Floating Gate) is selectively provided, and a control gate CG (Cont CG) is formed so as to cover the floating gate FG and to be orthogonal to the active region AA.
rol Gate) 1 to CG 16 are extended. Active area A
A includes the floating gate FG and the control gates CG1 to CG.
By providing impurity diffusion layers (not shown) serving as source and drain regions so as to sandwich G16, memory cell transistors M1 to M16 connected in series are formed. At both ends of the memory cell transistors M1 and M16, select gates SGD and SGS are formed so as to be orthogonal to the active region AA, similarly to the control gates CG1 to CG16. Similarly to the memory cell transistors M1 to M16, the active region AA is provided with impurity diffusion layers (not shown) serving as source and drain regions so as to sandwich the select gates SGD and SGS. S2 is formed.
Thus, one NAND cell is configured by connecting the memory cell transistors M1 to M16 in series between the select transistors S1 and S2. The drain region of the select transistor S1 having the select gate SGD is connected to a not-shown bit line BL (Bit Line) via a contact hole 210, and the select gate S
The source region of the select transistor S2 having GS is connected to a source line SL (Source) formed of an impurity diffusion layer (not shown).
Line) is connected to the source region of the adjacent select transistor.

FIGS. 29 (a) and 29 (b) are cross-sectional views taken along lines AA 'and BB' in FIG. 28, respectively.

As shown in the figure, a silicon oxide film 120 is buried in a trench 110 formed on a main surface of a silicon substrate 100 to form an element isolation region STI. On the active region AA between the element isolation regions STI, a gate insulating film 130 is formed.
A floating gate FG including amorphous silicon films 140 and 150 is formed on 30. On the floating gate FG, an insulating film 160 between the floating gate and the control gate is formed. On the insulating film 160 between the floating gate and the control gate,
Control gates CG1 to CG16, select gate SGD,
An amorphous silicon film 170 to be SGS is formed. Then, in the silicon substrate 100, the memory cell transistors M1 to M16 and the select transistors S1 and S2 are formed by selectively forming the impurity diffusion layers 180 serving as source and drain regions. Also,
A silicon nitride film 190 is formed on the entire surface, and an interlayer insulating film 200 is formed so as to cover the memory cell transistors M1 to M16 and the select transistors S1 and S2. Then, by forming the wiring layer 220 of the bit line BL that makes contact with the drain region of the selection transistor S1 via the contact hole 210,
A NAND flash EEPROM is formed.

FIG. 30 is an equivalent circuit of a NAND cell. As shown, 16 memory cell transistors M1 to M16 are connected in series between the select transistors S1 and S2. The control gates CG1 to CG16 are connected to word lines WL (Word Line) 1 to WL16, respectively.
GD and SGS are connected to a row decoder (not shown), and the row decoder selectively drives one of the word lines WL1 to WL16 and the select gate lines SGD and SGS. The bit line BL is connected to a column selector (not shown), and is selected by the column selector. Source line SL is connected to a source decoder via a global source line (not shown).

Next, the NAND flash EEPROM is used.
The method of manufacturing the OM will be described with reference to FIGS. 31 (a) and (b) to FIGS. 36 (a) and (b). FIG. 31 (a),
(B) to FIGS. 36 (a) and 36 (b) show FIGS.
FIGS. 4A and 4B correspond to FIGS. 4A and 4B and sequentially show cross-sectional views of a manufacturing process of a NAND flash EEPROM.

First, as shown in FIGS. 31A and 31B, a gate insulating film 130 made of a silicon oxide film, an amorphous silicon film 140, a silicon nitride film 230, and a silicon oxide film 240 are formed on a silicon substrate 100. Are sequentially formed.

Next, a silicon oxide film 240, a silicon nitride film 230, an amorphous silicon film 140, and a gate insulating film 13 are formed by lithography and anisotropic etching.
0, and selectively etching the silicon substrate 100,
A trench 110 for element isolation as shown in FIGS. 32A and 32B is formed.

Next, as shown in FIGS. 33 (a) and 33 (b), a silicon oxide film 120 is deposited and formed on the entire surface and the trench 11 is formed.
The silicon oxide films 120 and 240 are polished and flattened by CMP (Chemical Mechanical Polishing) using the silicon nitride film 230 as a stopper to complete the element isolation region STI.

Thereafter, the silicon nitride film 230 is selectively removed by wet etching. And FIG.
As shown in (a) and (b), a floating gate FG including the amorphous silicon films 150 and 140 is formed by forming and patterning the amorphous silicon film 150.

Next, as shown in FIGS. 35A and 35B,
An insulating film 160 between the floating gate and the control gate, an amorphous silicon film 170 to be a control gate and a select gate on the entire surface
Are sequentially formed, and control gates CG1 to CG16 and select gates SGD and SGD are formed by lithography and etching.
GS is formed. Through the above steps, a two-layer gate structure as shown in the figure is obtained.

Next, as shown in FIGS. 36A and 36B, an impurity is introduced into a region serving as a source and a drain by an ion implantation method, and an impurity diffusion layer 180 is selectively formed. The transistors M1 to M16 and the selection transistors S1 and S2 are completed. Subsequently, after the silicon nitride film 190 and the interlayer insulating film 200 are formed on the entire surface, the interlayer insulating film 200 is reflowed by heat treatment and flattened.

Thereafter, the interlayer insulating film 200 is polished and flattened by the CMP method, and a contact hole for making contact with the drain region of the select transistor is formed by lithography and etching. Then, the contact hole is buried with a metal wiring layer to form a bit line, and the structure shown in FIGS. 29A and 29B is obtained.

Next, the NAND type flash EEPROM is described.
The operation of the OM will be described using an equivalent circuit in FIG. Data writing is performed in order from the memory cell transistor M16 farthest from the bit line BL. The high voltage Vpp is applied to the control gate CG16 of the selected memory cell transistor M16, and the intermediate potential Vppm is applied to the control gates CG1 to CG15 of the memory cell transistors M1 to M15 on the bit line BL side. 0 V or intermediate potential V is applied to the bit line BL according to data.
give m.

When 0 V is applied to the bit line BL, this potential is transferred to the drain of the selected memory cell transistor, and electrons are injected into the floating gate FG. As a result, the threshold voltage of the selected memory cell transistor shifts in the positive direction. This state is set to “0”. On the other hand, when the intermediate potential Vm is applied to the bit line BL, the injection of electrons does not effectively occur, so that the threshold voltage does not change.
Stay negative. It should be noted that data is written to the control gate C
This is performed simultaneously for all the memory cell transistors sharing G.

Erasure of data is collective erasure of all bits. That is, all the control gates CG1 to CG16 are set to 0
V, and a p-type well (not shown) in the silicon substrate on which the NAND cell is formed is set to 20V. Thereby, in all the memory cell transistors M1 to M16, the electrons of the floating gate FG are emitted to the p-type well, and the threshold voltage shifts in the negative direction.

In reading data, the control gate CG of the selected memory cell transistor is set to 0 V, and the control gates CG of the other memory cell transistors are set to the power supply potential Vcc to determine whether a current flows through the selected memory cell transistor. This is performed by detecting

As described above, conventionally, one memory cell transistor stores two data, “0” and “1”, and the data level n is “n = 2”. However, in recent years, as a technique for increasing the storage capacity, a multi-valued memory that sets the data level n to “n ≧ 3” has attracted attention.

For example, if the data level n is "n = 4", one memory cell transistor has "00",
Two-bit data "01", "10", and "11" can be stored. This multi-level control of “n ≧ 3” can be realized by setting the threshold voltages of the memory cell transistors to three or more. That is, when the four-level control is performed as described above, the threshold voltage Vth of the memory cell transistor is set to “Vth00”, “Vth01”,
Four types of “Vth10” and “Vth11” may be used. Then, in order to set the threshold voltage to four types, the amount of electrons to be injected into the floating gate FG may be divided into four types (in the above example, the data of “11” indicates that the charge is effectively stored in the floating gate FG). Not injected).

However, the conventional NAND flash EE
In the PROM, data is written by applying a pulse of a constant write voltage to the control gate CG of the selected memory cell transistor a plurality of times, for example, about 10 times.
This has been done by divided writing. In addition, when performing multi-value control, the amount of charge injected into the memory cell transistor is controlled by changing the number of times of writing. Therefore, for example, when performing four-level control, the number of times of writing is "30" when writing data "00" to the memory cell transistor, 20 times when writing data "01", and when writing data "10". It was necessary to perform divided writing ten times. Therefore, when performing multi-level control, if the number of bits of data to be stored in one memory cell transistor is increased, the number of times of writing increases accordingly, and there is a problem that the writing operation takes time.

[0022]

In the above-mentioned conventional nonvolatile semiconductor memory device, data is written by divisional writing. When multi-value control is performed, the amount of charge injected into the memory cell transistor is controlled by changing the number of times of writing. Therefore, for example, when performing 4-level control, when writing data “00” to the memory cell transistor, the number of times of writing is 3
It was necessary to perform the divisional writing 0 times, 20 times to write the data “01”, and 10 times to write the data “10”. Therefore, when performing multi-level control, if the number of bits of data to be stored in one memory cell transistor is increased, the number of times of writing increases accordingly, and there is a problem that the writing operation takes time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to set a plurality of thresholds of a memory cell transistor with the same number of times of writing, so that a nonvolatile semiconductor memory device capable of shortening a writing time can be provided. It is to provide a manufacturing method thereof.

[0024]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device provided on an element isolation region provided on a semiconductor substrate and on an active region between adjacent element isolation regions. A first gate insulating film extending from the first gate insulating film of the active region to the first gate insulating film of the adjacent active region via the element isolation region. Gate electrode, a second gate insulating film provided on the first gate electrode, and a second gate insulating film provided on the second gate insulating film, and at least partially overlaps the first gate electrode. A second gate electrode, the first gate insulating film, the first gate electrode, the second gate insulating film, and the stacked gate structure formed by the second gate electrode, the Sharing the first gate electrode Source formed respectively in the sexual area, is characterized in that it comprises a drain region.

According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the first gate insulating films provided on the active regions sharing the first gate electrode, respectively, It is characterized in that the film thicknesses are different from each other.

According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, the first gates respectively provided on active regions sharing the first gate electrode. The insulating films are characterized by different types of films.

According to a fourth aspect, in the nonvolatile semiconductor memory device according to any one of the first to third aspects, the first semiconductor device is provided on an active region sharing the first gate electrode. At least one of the gate insulating films is an oxynitride film.

Further, as described in claim 5, in the nonvolatile semiconductor memory device according to any one of claims 1 to 4, the active region sharing the first gate electrode with the stacked gate structure. When one memory cell transistor is constituted by the source and drain regions respectively formed and the n (n> 3) value is stored in the memory cell transistor, the voltage applied to the second gate electrode is fixed. Changing the amount of electrons injected from each of the active regions to the first gate electrode by changing the combination of voltages applied to the drain regions formed in the active regions sharing the first gate electrode. By adjusting the threshold value, a threshold level of the n value of the memory cell transistor is set.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a nonvolatile semiconductor memory device, comprising: forming a first gate insulating film on an active region of a semiconductor substrate; Forming a first conductive film for forming a first gate electrode, the first conductive film and the first conductive film;
Forming a trench by etching the gate insulating film and the semiconductor substrate, and forming an element isolation region by filling the trench with an insulating film; and forming a trench on the first conductive film and the element isolation region. Forming a second conductive film for forming the first gate electrode; and forming the second conductive film on the first conductive film of the active region adjacent to the first conductive film of the active region. Forming a first gate electrode composed of the first conductive film and the second conductive film on the film so as to be present over the element isolation region, Forming a second gate insulating film on the gate electrode, and forming a second gate electrode on the second gate insulating film so as to at least partially overlap the first gate electrode. Performing the first game. Insulating film, the first gate electrode,
Impurities are introduced using the stacked gate structure formed by the second gate insulating film and the second gate electrode as a mask, and source and drain regions are respectively formed in the active regions sharing the first gate electrode. And a step of forming

According to a seventh aspect of the present invention, there is provided a method for manufacturing a nonvolatile semiconductor memory device, comprising the steps of:
Forming a first insulating film; removing a portion of the first insulating film to expose the semiconductor substrate;
Forming a second insulating film on the insulating film and the semiconductor substrate, and forming a first conductive film for forming a first gate electrode on the second insulating film. , The first conductive film, the second insulating film, the first insulating film,
And etching the semiconductor substrate to form a trench, and filling the trench with a third insulating film to form an element isolation region, and the second insulating film remaining on one of the adjacent active regions Forming a first gate insulating film from the first and second insulating films remaining on the other active region; and forming the first gate insulating film on the first conductive film and the element isolation region. Forming a second conductive film for forming one gate electrode; and forming the second conductive film on the first conductive film of the active region adjacent to the first conductive film of the active region. Forming a first gate electrode composed of the first conductive film and the second conductive film by patterning so as to be present over the element isolation region; Forming a second gate insulating film on the electrode; , On the second gate insulating film,
Forming a second gate electrode so as to at least partially overlap the first gate electrode; and forming the first gate insulating film, the first gate electrode, and the second gate electrode.
Impurity is introduced using the stacked gate structure formed by the gate insulating film and the second gate electrode as a mask,
Forming source and drain regions in the active regions sharing the first gate electrode, respectively.

According to a eighth aspect of the present invention, in the method for manufacturing a nonvolatile semiconductor memory device according to the sixth or seventh aspect, the first and second gate electrodes are provided on active regions sharing the first gate electrode. One gate insulating film is characterized by different types of films.

Further, as set forth in claim 9, in the method for manufacturing a nonvolatile semiconductor memory device according to any one of claims 6 to 8, the first gate electrode is provided on an active region sharing the same. At least one of the obtained first gate insulating films is an oxynitride film.

According to the structure and method of the present invention, the plurality of active regions share the first gate electrode, and each active region is provided with a source and a drain region. I have. That is, one memory cell transistor has a structure having a plurality of electrically isolated source and drain regions. Therefore, the potential difference between each active region and the first gate electrode can be set independently by changing the combination of voltages applied to the electrically separated drain regions. Therefore, when writing data by injecting electrons into the first gate electrode of the memory cell transistor and changing the threshold voltage, the amount of electrons injected from each active region into the first gate electrode is reduced. Since the setting can be made finely, there is no need to change the number of times of writing for each set threshold voltage unlike the conventional multi-value control. That is, all the threshold voltages can be set with the same number of times of writing, so that the writing time can be shortened.

The first gate insulating films on the respective active regions sharing the first gate electrode may have different thicknesses or different materials. May be.

It is desirable to use an oxynitride film for at least one first gate insulating film on each of the active regions sharing the first gate electrode.

[0036]

Embodiments of the present invention will be described below with reference to the drawings. For this explanation,
Common parts are denoted by common reference symbols.

A nonvolatile semiconductor memory device and a method of manufacturing the same according to the first embodiment of the present invention will be described using a NAND flash EEPROM as an example.

FIG. 1 shows a NAND flash EEPROM.
FIG. As shown in the figure, a plurality of device isolation regions STI are formed in a strip shape on a silicon substrate 10, and an active region AA is formed between adjacent device isolation regions STI.
It has become. Then, two adjacent active areas AA
And the element isolation region STI therebetween.
A floating gate FG is selectively provided.
Control gates CG1 to CG16 extend so as to cover G and to be orthogonal to the active region AA. Active area A
A includes the floating gate FG and the control gates CG1 to CG.
By selectively providing impurity diffusion layers (not shown) serving as source and drain regions so as to sandwich G16, memory cell transistors M1 to M16 connected in series are formed. That is, the memory cell transistor M1
To M16 are the floating gate FG and the control gates CG1 to CG
It has a structure having one stacked gate of 16 and two sets of source and drain regions electrically separated. At both ends of the memory cell transistors M1 and M16, select gates SGD and SGS are formed so as to be orthogonal to the active region AA, similarly to the control gates CG1 to CG16. Similarly to the memory cell transistors M1 to M16, the active region AA is provided with impurity diffusion layers (not shown) serving as source and drain regions so as to sandwich the select gates SGD and SGS, so that the select transistors S1 and S2 are provided. Are formed. That is, the selection transistors S1 and S2 have a structure similar to the memory cell transistors M1 to M16, having one gate and two sets of source and drain regions that are electrically separated. Thus, the selection transistor S1,
One NAND cell is configured by connecting the memory cell transistors M1 to M16 in series during S2.
The two drain regions of the select transistor S1 having the select gate SGD are connected to a bit line BL (not shown) via the contact hole 21, and the two source regions of the select transistor S2 having the select gate SGS are shown in FIG. A source line SL formed of an impurity diffusion layer (not shown) is connected to a source region of an adjacent select transistor.

FIGS. 2A and 2B are cross-sectional views taken along lines AA 'and BB' in FIG. 1, respectively.

As shown, a silicon oxide film 12 is formed in a trench 11 formed on the main surface of a silicon substrate 10.
Is embedded to form an element isolation region STI. A gate insulating film 13 (first gate insulating film) is formed on the active region AA between the element isolation regions STI,
On the gate insulating film 13, an amorphous silicon film 14 (first conductive film) which forms a part of the floating gate FG is formed. Then, the amorphous silicon film 14 formed in the two adjacent active regions AA and the amorphous silicon film 15 (the second A conductive film is formed, and the amorphous silicon films 14 and 15 form the floating gate FG.
(First gate electrode) is formed. Floating gate F
G, a floating gate / control gate insulating film 16 (second
Is formed on the floating gate / control gate insulating film 16, and the control gates CG1 to CG16,
An amorphous silicon film 17 (second gate electrode) serving as select gates SGD and SGS is formed. And
The memory cell transistors M1 to M16 and the select transistors S1 and S2 are formed in the silicon substrate 10 by selectively forming the impurity diffusion layers 18 serving as source and drain regions. In the select transistors S1 and S2, the insulating film 16 between the floating gate and the control gate is removed in a region (not shown), and the amorphous silicon film 1 is removed.
5 and 17 are electrically connected. Further, a silicon nitride film 19 is formed on the entire surface, and the memory cell transistors M1 to M16 and the select transistors S1, S1
2, an interlayer insulating film 20 is formed. Then, a wiring layer 22 of the bit line BL that makes contact with the drain region of the selection transistor S1 via the contact hole 21 is formed, thereby forming a NAND flash EEPROM.

FIG. 3 is an equivalent circuit of a NAND cell.
As shown in the figure, two conventional NAND cells are arranged in parallel, and memory cell transistors that share control gates CG1 to CG16 are connected with a common floating gate FG. In other words, 2
Memory cell transistors M1 to M16 each including one memory cell transistor are connected in series. Then, select transistors S1 and S2, which are two transistors, are provided at both ends of the memory cell transistors M1 and M16. The control gates CG1 to CG16 of the memory cell transistors M1 to M16 are respectively connected to word lines WL (Wo
rd Line) 1 to WL16 and the word lines WL1 to WL1.
The WL16 and the select gate lines SGD, SGS are connected to a row decoder (not shown), and the row decoder selectively drives any one of the word lines WL1 to WL16 and the select gate lines SGD, SGS. Also,
The bit line BL is connected to a column selector (not shown),
Selected by this column selector. Source line SL
Are connected to a source decoder via a global source line (not shown).

Next, the NAND type flash EEPROM is used.
4 (a), (b) to FIG.
This will be described with reference to FIGS. FIG. 4 (a),
(B) to FIGS. 15 (a) and 15 (b) show FIGS.
FIGS. 4A and 4B correspond to FIGS. 4A and 4B and sequentially show cross-sectional views of a manufacturing process of a NAND flash EEPROM.

First, as shown in FIGS. 4A and 4B,
A silicon oxide film serving as a gate insulating film 13 is formed on the silicon substrate 10 to a thickness of 10 nm by a thermal oxidation method or the like.
An amorphous silicon film 14 is formed on the gate insulating film 13 by a low pressure CVD (Chemical Vapor Deposition) method or the like.
It is formed to a thickness of nm. The gate insulating film 13 may be a silicon oxide film, but may be an oxynitride film by performing nitridation and oxidation using NH ₃ gas or the like. Subsequently, a silicon nitride film 23 and a silicon oxide film 24 are formed on the amorphous silicon film 14 to a thickness of 70 nm and 230 nm, respectively, by a low pressure CVD method or the like.
Then, a hydrogen combustion oxidation treatment is performed at a temperature of 850 ° C. for 30 minutes.

Next, a photoresist is applied to the entire surface, and is patterned by lithography for forming element isolation regions. Next, RIE using photoresist as a mask
The silicon oxide film 24 and the silicon nitride film 23 are processed by performing anisotropic etching such as a (Reactive Ion Etching) method. Then, the photoresist is removed by performing treatment with a mixed solution of O ₂ -plasma, sulfuric acid, and hydrogen peroxide solution.
Further, the silicon oxide film 24 and the silicon nitride film 23
The polycrystalline silicon film 14, the silicon oxide film 13, and the silicon substrate 10 are sequentially etched by RIE using the mask as a mask to form a trench 11 for forming an element isolation region, as shown in FIG. The structure shown in (b) is obtained.

Next, a 6-nm-thick silicon oxide film is formed on the surface of the silicon substrate 10 exposed on the surface of the trench 11 by performing a heat treatment in an oxidizing atmosphere at a temperature of 1000 ° C. Zu). This silicon oxide film
By making the shape of the corner of the trench 11 gentle, concentration of stress or the like on this corner is prevented.

Then, as shown in FIGS. 6A and 6B, a silicon oxide film 12 is formed on the entire surface by HDP (High Density).
The trench 11 is buried by forming the film to a thickness of 430 nm by a plasma (plasma) method or the like. Then, the silicon oxide films 12 and 24 are polished and flattened by the CMP method using the silicon nitride film 23 as a stopper, thereby completing the element isolation region STI.

Then, as shown in FIGS. 7A and 7B, a phosphoric acid treatment at a temperature of 150 ° C. is performed for 40 minutes.
The silicon nitride film 23 is selectively removed.

Thereafter, as shown in FIGS. 8A and 8B, an amorphous silicon film 15 and a silicon oxide film 25 are sequentially formed to a thickness of 100 nm and 230 nm, respectively, by a low pressure CVD method.

Next, as shown in FIGS. 9A and 9B, a photoresist 26 is applied to the entire surface and patterned by lithography as shown in the figure. Then, the silicon oxide film 25 is processed by RIE or the like using the photoresist 26 as a mask.

After that, the resist 26 is removed by performing a process using a mixed solution of O ₂ -plasma, sulfuric acid, and hydrogen peroxide solution. Next, as shown in FIGS. 10A and 10B, a silicon oxide film 27 is formed to a thickness of 70 nm on the entire surface by a low pressure CVD method or the like.

Thereafter, FIG.
Etching is performed so that the silicon oxide film 27 remains only on the side wall of the silicon oxide film 25 as shown in FIGS.

Then, the amorphous silicon film 15 is formed by RIE using the silicon oxide films 25 and 27 as a mask.
Then, the mask material for the silicon oxide films 25 and 27 is removed with a mixed solution of O ₂ -plasma, sulfuric acid, and hydrogen peroxide. By the above steps, FIGS. 12 (a) and 12 (b)
As shown in FIG. 3, the amorphous silicon films 14 and 1 extend over two active regions AA and the element isolation region STI sandwiched between the active regions AA.
5 to complete the floating gate FG.

Next, as shown in FIGS. 13A and 13B, an insulating film 16 between the floating gate and the control gate is formed to a thickness of 17 nm over the entire surface by low pressure CVD. The insulating film 16 between the floating gate and the control gate is, for example, a silicon oxide film (SiO ₂ : 5 nm), a silicon nitride film (SiN: 7
nm) and silicon oxide film (SiO ₂ : 5 nm).
This is an ONO film having a layer structure. The insulating film 16 between the floating gate and the control gate may be simply a silicon oxide film, or may be an ON film or a NO film having a two-layer structure of a silicon oxide film and a silicon nitride film. Note that the insulating film 16 between the floating gate and the control gate is removed in a part (not shown) of the region where the select transistor and the transistor in the peripheral region are to be formed. Of course, all the insulating film 16 between the floating gate and the control gate in the region to be formed may be removed. Subsequently, the insulating film 16 between the floating gate and the control gate is
The control gates CG1 to CG16 and the select gate S
The amorphous silicon film 17 to be GD and SGS is reduced in pressure CV.
Formed to a thickness of 80 nm by Method D. Note that a silicide film such as a tungsten silicide film may be formed on the amorphous silicon film 17, or an insulating film may be formed on the silicide film.

Next, as shown in FIGS. 14A and 14B, the amorphous silicon film 17, the floating gate-control gate insulating film 16, and the amorphous silicon film 17 are formed by lithography and anisotropic etching. The high quality silicon films 15 and 14 are etched to form a two-layer gate structure. Then, an impurity is introduced into a region serving as a source and a drain by an ion implantation method to selectively form the impurity diffusion layer 18. Then, a heat treatment at a temperature of 1050 ° C. is performed for 30 seconds to activate the introduced impurity. Do. Subsequently, a silicon nitride film 1
9 is formed to a thickness of 40 nm by a low pressure CVD method.

Through the above steps, the memory cell transistors M1 to M16 and the select transistors S1 and S2 are completed. Note that, as described above, the selection transistors S1, S1
2, the floating gate FG and the select gate SGD,
It is electrically connected to the SGS in a region not shown.

Next, as shown in FIGS. 15A and 15B, BPSG (Boron Phosphor) having high step coverage over the entire surface is provided.
The interlayer insulating film 20 is formed by a ous silicate glass) film. After the memory cell transistors M1 to M16 and the select transistors S1 and S2 are embedded with the interlayer insulating film 20, a BPSG film is reflowed and flattened by performing a heat treatment.

Thereafter, the interlayer insulating film 20 is formed by the CMP method.
After the polishing, the surface of the interlayer insulating film 20 is flattened by performing a heat treatment, and subsequently, the density of the interlayer insulating film 20 is increased by a heat treatment in a nitrogen atmosphere. Then, a contact hole 21 for making contact with the impurity diffusion layer 18 of the select transistor S1 is formed by lithography and anisotropic etching. Then, an impurity is introduced into the silicon substrate 10 at the bottom of the contact hole 21 by an ion implantation method, and RTA (Rapid Thermal
The introduced impurities are activated by heating in a nitrogen atmosphere at a temperature of 950 ° C. by an Annealing method. Then, by PVD (Physical Vapor Deposition) method,
For example, forming a titanium film and a tungsten film on the entire surface,
The contact hole 21 is buried. Further, the titanium film and the tungsten film are patterned to form a bit line B
The L wiring layer 22 is formed to complete the structure shown in FIGS.

Next, in the NAND flash EEPROM having the above-described structure, a method of writing data in the case of performing multi-value control will be described by taking as an example the case of performing four-value control. FIG. 16 shows the relationship between the number of memory cells and the threshold voltage Vth.
And data “00”, “01”,
The threshold voltages corresponding to “10” and “11” are set to “Vth00”, “Vth01”, “Vth10”,
“Vth11”. Note that data “11” is an erased state in which electrons are not effectively injected into the floating gate FG of the memory cell transistor and the threshold voltage is negative.

Referring to FIGS. 17A to 17D, the relationship between the voltages when writing four data as described above will be described. FIGS. 17A to 17D are plan views of the NAND flash EEPROM, and show the voltage relationships when writing data “00”, “01”, “10”, and “11”, respectively. Here, it is assumed that the memory cell transistor M3 is selected. Therefore, the control gates CG1 to CG of the memory cell transistors M1 to M16
16, the high voltage Vpp = 20 V is applied only to the control gate CG3 of the memory cell transistor M3, and the other control gates CG1, CG2, CG4 to CG16 have the intermediate potential Vppm so that electrons are not injected into the floating gate.
= 7V is applied. Also, the selection transistors S1, S2
20V is applied to both select gates SGD and SGS to bring them into a selected state. The source line SL is set to the ground potential, and the source region of the selection transistor S2 is set to the ground potential by the source line SL.

First, a case where data "00" is written to the memory cell transistor M3 will be described with reference to FIG. To write data “00”, it is necessary to set the threshold voltage Vth of the memory cell transistor M3 to the highest “Vth00”. That is, the state is such that the amount of electrons injected into the floating gate FG is the largest. Therefore, the two drain regions of the selection transistor S1 are set in a floating state. Then, in the selected memory cell transistor M3, a high potential difference of about 20 V is generated between the silicon substrate 10 and the floating gate FG, and a large amount of electrons are injected into the floating gate FG.

Next, when writing data "01",
As shown in FIG. 17B, 2 of the selection transistor S1
One of the drain regions is set to a floating state, and the other is set to an intermediate potential Vm ′ = 3.5 V. Then, in the selected memory cell transistor M3, the potential of one of the two active regions AA of the silicon substrate 10 rises due to the effect of setting the other drain region of the two drain regions to 3.5 V, and the silicon substrate in this region The potential difference between 10 and floating gate FG decreases. Therefore, the amount of electrons injected into the floating gate FG is smaller than when data “00” is written.

When writing data "10", the data shown in FIG.
As shown in (c), the two drain regions of the selection transistor S1 are both set to the intermediate potential Vm '= 3.5V. Then, in the selected memory cell transistor M3, due to the effect that the two drain regions are set to 3.5 V, the silicon substrate 10 is less than when data “00” is written.
Of the two active regions AA increases, and the potential difference between the two active regions AA and the floating gate FG decreases. Therefore, the amount of electrons injected into the floating gate FG is further reduced as compared with the case where the data “01” is written.

Since the writing of data "11" is in an erased state and the threshold voltage Vth must not be changed from a negative state, electrons are not effectively injected into the floating gate. Therefore, while maintaining one of the two drain regions of the selection transistor S1 at the intermediate potential Vm '= 3.5V, the other is set to the intermediate potential Vm = 7.0V. Then, in the selected memory cell transistor M3, the potential of one of the two active regions AA of the silicon substrate 10 further rises due to the effect of setting the other drain region of the two drain regions to 7.0 V, and the silicon in this region is increased. The potential difference between the substrate 10 and the floating gate FG further decreases. Therefore, the injection amount of electrons into the floating gate FG is further reduced as compared with the case where data “10” is written, and the floating gate FG
Injection of electrons into is not performed effectively.

In the above four voltage relations, in each case, when, for example, ten pulses are applied to perform divided writing, the potential difference between the silicon substrate and the floating gate FG is different even if the number of writings is the same, so that The amount of electrons injected into the floating gate FG is different, and four threshold voltages “Vth00”, “Vth01”, “Vth10”,
“Vth11” can be set.

The voltage applied to the two drain regions of the select transistor S1 is not limited to the above value. If the amount of electrons injected into the floating gate FG can be changed step by step, Any combination of voltage values applied to the drain region may be used.

Conventionally, when performing quaternary control, four threshold values of the memory cell transistor are set by fixing the voltage of the drain region of the selection transistor S1 and changing the number of times of writing. Therefore, data “00”, “0”
When writing "1" and "10", it was necessary to apply a write pulse 30 times, 20 times, and 10 times, respectively.
However, according to the above embodiment, the floating gate FG of one memory cell transistor is connected to the element isolation region STI and the two active regions AA adjacent to the element isolation region STI.
The active region AA is provided with two sets of electrically isolated source and drain regions. Therefore, by changing the combination of voltages applied to the two drain regions, the amount of electrons injected from each active region AA to the floating gate FG can be finely controlled. Therefore, when data is written to the memory cell transistor, it is not necessary to change the number of times of writing for each set threshold voltage unlike the conventional multi-value control. That is, by changing the voltage of the drain region of the selection transistor S1, any data can be written by applying a write pulse ten times, so that the writing time can be reduced.

In the above embodiment, the same material is used for the two gate insulating films 13 on the two active regions AA where one memory cell transistor is formed. Alternatively, different materials may be used, such as using an oxynitride film for the other. In the case of the above example, after forming the gate oxide film 13 with the silicon oxide film on the silicon substrate 10 in the step shown in FIG. 4, a mask material having an opening in a region where the silicon oxide film is to be an oxynitride film is used. Once formed, nitridation and oxidation are performed. Thereafter, the mask material is removed, and according to the manufacturing method described in the first embodiment, one of the two gate insulating films 13 of one memory cell transistor is a silicon oxide film and the other is an oxynitride film. I can do it.

Next, a nonvolatile semiconductor memory device and a method of manufacturing the same according to the second embodiment of the present invention will be described.
An ND type flash EEPROM will be described as an example.

The NAND flash E according to the present embodiment
The planar structure of the EPROM is the same as that described in the first embodiment, and a description thereof will not be repeated.

FIG. 18 is a sectional view taken along the line AA 'in FIG. The cross-sectional structure along the line BB 'in FIG. 1 is also substantially the same as that of the first embodiment, and a description thereof will be omitted.

As shown, a silicon oxide film 12 is formed in a trench 11 formed in the main surface of a silicon substrate 10.
(Third insulating film) is buried to form an element isolation region STI.
Are formed. A gate insulating film 13 (first region) is provided on one active region AA adjacent to the isolation region STI.
Are formed on the other active region AA, and two gate insulating films 13 'and 13 (gate insulating film 13': second insulating film, gate insulating film 13) are formed on the other active region AA. :
A first insulating film and gate insulating films 13 and 13 ′ (first gate insulating film) are formed. On the gate insulating film 13, an amorphous silicon film 14 forming a part of the floating gate FG is formed. Then, an amorphous silicon film 15 is formed so as to straddle the amorphous silicon film 14 formed in the two adjacent active regions AA and the element isolation region STI between the two active regions AA. The amorphous silicon films 14 and 15 form a floating gate FG. On the floating gate FG, an insulating film 16 between the floating gate and the control gate is formed. On the insulating film 16 between the floating gate and the control gate, the control gates CG1 to CG1 are formed.
6. An amorphous silicon film 17 serving as select gates SGD and SGS is formed. And the silicon substrate 10
Is selectively formed with an impurity diffusion layer 18 (not shown) serving as source and drain regions, so that the memory cell transistors M1 to M16 and the selection transistor S
1, S2 are formed. The selection transistor S
1 and S2, the insulating film 16 between the floating gate and the control gate is removed in a region (not shown), and the amorphous silicon film 15 is removed.
And 17 are electrically connected. Further, a silicon nitride film 19 is formed on the entire surface, and the memory cell transistors M1 to M16 and the select transistors S1, S2
, An interlayer insulating film 20 is formed.
Then, the bit line BL that makes contact with the drain region of the selection transistor S1 through the contact hole 21
By forming the wiring layer 22, a NAND flash EEPROM is formed.

That is, the NAND flash EEPROM according to the present embodiment is the same as the NAND flash EEPROM according to the first embodiment.
The two gate insulating films on the two active regions AA of the memory cell transistors M1 to M16 of the D-type flash EEPROM have different thicknesses.

Next, the NAND flash EEPR
The method of manufacturing the OM will be described with reference to FIGS. 19 to 26 correspond to FIG. 18 and sequentially show cross-sectional views of a manufacturing process of the NAND flash EEPROM.

First, as shown in FIG. 19, a silicon oxide film to be a gate insulating film 13 'is formed on a silicon substrate 10 to a thickness of 10 nm by a thermal oxidation method or the like. Then, the gate insulating film 13 'is patterned as shown by lithography and anisotropic etching.

Next, as shown in FIG. 20, the gate insulating film 13 is formed on the silicon substrate 10 and the gate insulating film 13 '.
The amorphous silicon film 14 is formed to a thickness of 10
m and 60 nm respectively. The gate insulating films 13 and 13 ′ may be silicon oxide films, but may be oxynitride films by performing nitridation and oxidation using NH ₃ gas or the like. Subsequently, a silicon nitride film 23 and a silicon oxide film 24 are formed on the amorphous silicon
It is formed to a thickness of 0 nm. Then, a hydrogen combustion oxidation treatment is performed at a temperature of 850 ° C. for 30 minutes.

Next, a photoresist is applied to the entire surface and patterned by lithography for forming element isolation regions. Next, RIE using photoresist as a mask
The silicon oxide film 24 and the silicon nitride film 23 are processed by performing anisotropic etching such as a (Reactive Ion Etching) method. Then, the photoresist is removed by performing treatment with a mixed solution of O ₂ -plasma, sulfuric acid, and hydrogen peroxide solution.
Further, the silicon oxide film 24 and the silicon nitride film 23
Polycrystalline silicon film 14, gate insulating films 13, 13 'and silicon substrate 10 by RIE or the like using
Are sequentially etched to form a trench 11 for forming an element isolation region to obtain a structure shown in FIG.

Next, a 6-nm thick silicon oxide film is formed on the surface of the silicon substrate 10 exposed on the surface of the trench 11 by performing a heat treatment in an oxidizing atmosphere at a temperature of 1000 ° C. Zu). This silicon oxide film
By making the shape of the corner of the trench 11 gentle, concentration of stress or the like on this corner is prevented.

Then, as shown in FIG. 22, a silicon oxide film 12 is formed on the entire surface to a thickness of 430 nm by the HDP (High Density Plasma) method or the like, so that the trench 1 is formed.
Embed 1 Then, the silicon oxide film 12 is formed by a CMP method using the silicon nitride film 23 as a stopper.
24 is polished and flattened to complete an element isolation region STI.

Then, as shown in FIG.
The silicon nitride film 23 is selectively removed by performing phosphoric acid treatment at 40 ° C. for 40 minutes.

Thereafter, the amorphous silicon film 15 and the silicon oxide film 25 are each formed to a thickness of 100 n by a low pressure CVD method.
Next, as shown in FIG. 24, a photoresist 26 is applied to the entire surface and patterned by lithography as shown in FIG. Then, the silicon oxide film 25 is processed by RIE or the like using the photoresist 26 as a mask.

After that, the resist 26 is removed by performing a process using a mixed solution of O ₂ -plasma, sulfuric acid, and hydrogen peroxide solution. Next, a silicon oxide film 27 is formed to a thickness of 70 nm on the entire surface by a low pressure CVD method or the like, and the silicon oxide film 27 is left only on the side walls of the silicon oxide film 25 as shown in FIG. Etching as follows.

Then, the amorphous silicon film 15 is formed by RIE using the silicon oxide films 25 and 27 as a mask.
Then, the mask material of the silicon oxide films 25 and 27 is removed with a mixed solution of O ₂ -plasma, sulfuric acid, and hydrogen peroxide, and as shown in FIG.
A floating gate FG composed of amorphous silicon films 14 and 15 is completed over the element isolation region STI sandwiched between A and the element isolation region STI.

Thereafter, as in the first embodiment, FIG.
3 to FIG. 15, the NAND flash EE
Complete the PROM.

Next, the NAND flash E having the above structure
With reference to FIGS. 27A to 27D, a description will be given of the relationship between the voltages when the quaternary control shown in FIG. 16 is performed in the EPROM. FIGS. 27A to 27D show N
FIG. 3 is a plan view of an AND-type flash EEPROM, showing a voltage relationship when data “00”, “01”, “10”, and “11” are written, respectively. It is assumed that the memory cell transistor M3 is selected as in the first embodiment. The active region in which only one layer of the gate oxide film 13 is formed is AA, and the active region in which the two layers of the gate insulating films 13 and 13 'are formed is AA'.

First, when writing data "00" to the memory cell transistor M3, as in the first embodiment, as shown in FIG.
Are set in a floating state, a large amount of electrons are injected into the floating gate FG, and the threshold voltage of the memory cell transistor is the highest “Vth00”.
Can be set to

Next, when writing data "01",
As shown in FIG. 27B, 2 of the selection transistor S1
Of the drain regions, the drain region of the active region AA is set to be floating, and the drain region of the active region AA ′ is set to 3.5V. This reduces the amount of electrons injected into the floating gate FG as compared with the case where data “00” is written.

When writing data “10”, the data shown in FIG.
As shown in (c), the two drain regions of the selection transistor S1 are both set to 3.5V. As a result, compared to the case where data “01” is written, floating gate FG
The amount of electrons injected into the substrate is further reduced.

When writing data "11", of the two drain regions of the select transistor S1, the drain region of the active region AA is set to 3.5V and the drain region of the active region AA 'is set to 7.0V. . As a result, the amount of electrons injected into the floating gate FG is further reduced, and the floating gate F
Injection of electrons into G is not performed effectively.

In the above four voltage relationships, four threshold voltages "Vth00" and "Vth00"
th01 ”,“ Vth10 ”, and“ Vth11 ”can be set, so that the writing time can be shortened, and as described in the first embodiment, 2
When the thickness of the two gate insulating films is the same, when a voltage is applied to only one of the two drains, the number of electrons injected into the floating gate FG is the same regardless of the voltage applied to either drain region. is there. However, as in the present embodiment, 2
By changing the thickness of one gate insulating film, the number of electrons that can be injected into the floating gate FG differs depending on which drain region is to be applied with a voltage. Therefore, the amount of data stored in the memory cell transistor can be easily increased as compared with the first embodiment.

As in the first embodiment, the voltages applied to the two drain regions of the select transistor S1 are not limited to the above values.

Although the same material is used for the two gate insulating films on the two active regions AA and AA ', they are different from each other, such as using a silicon oxide film for one and an oxynitride film for the other. Materials may be used. In the case of the above example, in the step shown in FIG.
After forming 3 ', a mask material having an opening in a region where the silicon oxide film is to be turned into an oxynitride film is formed,
Nitriding. Thereafter, the mask material is removed, and one of the two gate insulating films of one memory cell transistor is made of a silicon oxide film and the other is made of an oxynitride film by following the manufacturing method described in the second embodiment. Can be done. In addition, the present invention can be implemented with appropriate modifications without departing from the gist of the present invention.

[0092]

As described above, according to the present invention, a nonvolatile semiconductor memory device and a method of manufacturing the same which can shorten the write time by setting a plurality of threshold values of the memory cell transistor with the same number of write operations are provided. Can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view of a NAND flash EEPROM according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a NAND flash EEPROM according to the first embodiment of the present invention, and FIG.
5A is a cross-sectional view along the line AA ′, and FIG.

FIG. 3 is an equivalent circuit of one NAND cell of the NAND flash EEPROM according to the first embodiment of the present invention;

FIGS. 4A and 4B are cross-sectional views showing a first manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention; FIG. 4A is a sectional view taken along line AA ′ in FIG. 1; Sectional drawing along the BB 'line direction.

FIGS. 5A and 5B are cross-sectional views illustrating a second manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention; FIG. 5A is a sectional view taken along line AA ′ in FIG. 1; Sectional drawing along the BB 'line direction.

FIGS. 6A and 6B are cross-sectional views illustrating a third manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention. FIG. 6A is a sectional view taken along line AA ′ of FIG. Sectional drawing along the BB 'line direction.

FIGS. 7A and 7B are cross-sectional views showing a fourth manufacturing process of the NAND-type flash EEPROM according to the first embodiment of the present invention; FIG. 7A is a sectional view taken along the line AA ′ in FIG. 1; Sectional drawing along the BB 'line direction.

FIGS. 8A and 8B are cross-sectional views of a fifth manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention, wherein FIG. 8A is a sectional view taken along line AA ′ in FIG. 1, and FIG. Sectional drawing along the BB 'line direction.

FIGS. 9A and 9B are cross-sectional views illustrating a sixth manufacturing process of the NAND-type flash EEPROM according to the first embodiment of the present invention; FIG. 9A is a sectional view taken along line AA ′ in FIG. 1; Sectional drawing along the BB 'line direction.

FIGS. 10A and 10B are cross-sectional views of a seventh manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention, in which FIG. 10A is a sectional view taken along line AA ′ of FIG. 1, and FIG. Sectional drawing along the BB 'line direction.

11 is a sectional view of an eighth manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention. FIG. 11A is a sectional view taken along line AA ′ in FIG. 1, and FIG. Sectional drawing along the BB 'line direction.

12A and 12B are cross-sectional views illustrating a ninth manufacturing process of the NAND flash EEPROM according to the first embodiment; FIG. 12A is a sectional view taken along line AA ′ of FIG. 1; Sectional drawing along the BB 'line direction.

FIGS. 13A and 13B are cross-sectional views illustrating a tenth manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention; FIG.
The figure is a sectional view along the line BB '.

14A and 14B are cross-sectional views illustrating an eleventh manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention. FIG. 14A is a sectional view taken along line AA ′ in FIG. 1, and FIG.
The figure is a sectional view along the line BB '.

15A and 15B are cross-sectional views illustrating a twelfth manufacturing process of the NAND flash EEPROM according to the first embodiment of the present invention. FIG. 15A is a sectional view taken along the line AA ′ in FIG.
The figure is a sectional view along the line BB '.

FIG. 16 is a diagram showing a relationship between the number of memory cells and a threshold voltage when performing multi-value control in a NAND flash EEPROM.

FIGS. 17A and 17B are plan views of the NAND flash EEPROM according to the first embodiment of the present invention, in which FIG. 17A is data “00”, FIG. 17B is data “01”, and FIG. FIGS. 10D and 10D are diagrams showing the relationship between voltages when data “11” is written.

FIG. 18 is a cross-sectional view of a NAND flash EEPROM according to a second embodiment of the present invention, which is a cross-sectional view along the line AA ′ in FIG. 1;

FIG. 19 is a sectional view of a first manufacturing step of a NAND flash EEPROM according to the second embodiment;

FIG. 20 is a sectional view of a second manufacturing step of the NAND flash EEPROM according to the second embodiment;

FIG. 21 is a sectional view of a third manufacturing step of the NAND flash EEPROM according to the second embodiment;

FIG. 22 is a sectional view of a fourth manufacturing step of the NAND flash EEPROM according to the second embodiment;

FIG. 23 is a sectional view of a fifth manufacturing step of the NAND flash EEPROM according to the second embodiment;

FIG. 24 is a sectional view of a sixth manufacturing step of the NAND flash EEPROM according to the second embodiment;

FIG. 25 is a sectional view of a seventh manufacturing step of the NAND flash EEPROM according to the second embodiment;

FIG. 26 is a sectional view of an eighth manufacturing step of the NAND flash EEPROM according to the second embodiment;

FIGS. 27A and 27B are plan views of a NAND flash EEPROM according to a second embodiment of the present invention, wherein FIG. 27A is data “00”, FIG. FIGS. 10D and 10D are diagrams showing the relationship between voltages when data “11” is written.

FIG. 28 is a plan view of a conventional NAND flash EEPROM.

29A and 29B are cross-sectional views of a conventional NAND-type flash EEPROM. FIG. 29A is a cross-sectional view taken along the line AA ′ in FIG. 28, and FIG.

FIG. 30 is an equivalent circuit diagram of one NAND cell of a conventional NAND flash EEPROM.

31A to 31C are cross-sectional views of a first manufacturing process of a conventional NAND flash EEPROM, in which FIG. 31A is along the line AA ′ in FIG. 28, and FIG. 31B is along the line BB ′ in FIG. FIG.

32A and 32B are cross-sectional views of a second manufacturing process of the conventional NAND flash EEPROM, in which FIG. 32A is along the line AA ′ in FIG. 28, and FIG. FIG.

33A to 33C are cross-sectional views of a third manufacturing process of the conventional NAND flash EEPROM, in which FIG. 33A is along the line AA ′ in FIG. 28, and FIG. FIG.

34A and 34B are cross-sectional views illustrating a fourth manufacturing process of the conventional NAND flash EEPROM, in which FIG. 34A is along the line AA ′ in FIG. 28, and FIG. FIG.

FIGS. 35A and 35B are cross-sectional views of a fifth manufacturing process of a conventional NAND flash EEPROM, in which FIG. 35A is along the line AA ′ in FIG. 28, and FIG. FIG.

36A and 36B are cross-sectional views of a sixth manufacturing process of a conventional NAND flash EEPROM, in which FIG. 36A is along the line AA ′ in FIG. 28, and FIG. FIG.

[Explanation of symbols]

10, 100: silicon substrate 11, 110: trench 12, 24, 25, 27, 120, 240: silicon oxide film 13, 13'130: gate insulating film 14, 15, 140, 150, 170: amorphous silicon film 16, 160: insulating film between floating gate and control gate 18, 180: impurity diffusion layer 19, 23, 190, 230: silicon nitride film 20, 200: interlayer insulating film 21, 210: contact hole 22, 220: wiring layer 26 … Photoresist

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F001 AA09 AA43 AB02 AF20 AG29 AG30 5F083 EP27 EP32 EP43 EP44 EP76 ER22 JA04 JA39 NA01 PR05 PR34 PR40 ZA21 5F101 BA24 BB02 BF05 BH15 BH16

Claims (9)

[Claims] An element isolation region provided on a semiconductor substrate; a first gate insulating film provided on an active region between adjacent element isolation regions; and a first gate insulating film on the active region. A first gate electrode extending on the first gate insulating film of the active region adjacent to the first gate electrode via the element isolation region; and a second gate provided on the first gate electrode. An insulating film, a second gate electrode provided on the second gate insulating film, at least partially overlapping the first gate electrode, the first gate insulating film, the first gate Source and drain regions respectively formed in active regions sharing the first gate electrode so as to sandwich an electrode, the second gate insulating film, and a stacked gate structure formed by the second gate electrode Having The nonvolatile semiconductor memory device according to claim. 2. The first gate insulating film provided on each of the active regions sharing the first gate electrode,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the film thicknesses are different from each other. 3. The first gate insulating film provided on an active region sharing the first gate electrode,
3. A film according to claim 1, wherein the film types are different from each other.
14. The nonvolatile semiconductor memory device according to claim 1. 4. The semiconductor device according to claim 1, wherein at least one of the first gate insulating films provided on the active regions sharing the first gate electrode is an oxynitride film. 4. The nonvolatile semiconductor memory device according to claim 1. 5. A memory cell transistor comprising the stacked gate structure and source and drain regions respectively formed in an active region sharing the first gate electrode, wherein the memory cell transistor has n ( n> 3) When storing a value, a voltage applied to the second gate electrode is fixed, and a combination of voltages applied to the drain regions formed in the active regions sharing the first gate electrode, respectively. 2. The threshold level of the n-value of the memory cell transistor is set by adjusting the amount of electrons injected from each of the active regions into the first gate electrode by changing the threshold voltage. 5. The nonvolatile semiconductor memory device according to claim 1. 6. A step of forming a first gate insulating film on an active region of a semiconductor substrate, and forming a first conductive film for forming a first gate electrode on the first gate insulating film. Forming a trench by etching the first conductive film, the first gate insulating film, and the semiconductor substrate, and forming an element isolation region by filling the trench with an insulating film; Forming a first conductive film on the first conductive film and the element isolation region;
Forming a second conductive film for forming a gate electrode of the above; and forming the second conductive film on the first conductive film of the adjacent active region from the first conductive film of the active region. Forming a first gate electrode composed of the first conductive film and the second conductive film by patterning so as to be present over the element isolation region; and Forming a second gate insulating film thereon; and forming a second gate electrode on the second gate insulating film so as to at least partially overlap the first gate electrode. An impurity is introduced by using a stacked gate structure formed by the first gate insulating film, the first gate electrode, the second gate insulating film, and the second gate electrode as a mask; In the active region sharing the same gate electrode. Forming a source region and a drain region, respectively. 7. A step of forming a first insulating film on an active region of a semiconductor substrate, a step of exposing the semiconductor substrate by removing a part of the first insulating film, and a step of exposing the first insulating film. Forming a second insulating film on the film and the semiconductor substrate; forming a first conductive film for forming a first gate electrode on the second insulating film; Etching the first conductive film, the second insulating film, the first insulating film, and the semiconductor substrate to form a trench, and filling the trench with a third insulating film to form an element isolation region A first insulating film remaining on one of the adjacent active regions and a first insulating film remaining on the other active region;
Forming a gate insulating film, and forming the first insulating film on the first conductive film and the element isolation region.
Forming a second conductive film for forming the gate electrode, and forming the second conductive film on the first conductive film of the adjacent active region from the first conductive film of the active region. Forming a first gate electrode composed of the first conductive film and the second conductive film by patterning so as to be present over the element isolation region; Forming a second gate insulating film thereon; and forming a second gate electrode on the second gate insulating film so as to at least partially overlap the first gate electrode. Implanting impurities using a stacked gate structure formed by the first gate insulating film, the first gate electrode, the second gate insulating film, and the second gate electrode as a mask, In the active region sharing the same gate electrode. Forming a source region and a drain region, respectively. 8. The first gate insulating film provided on each of the active regions sharing the first gate electrode,
The film type is different from each other.
The manufacturing method of the nonvolatile semiconductor memory device according to the above. 9. The semiconductor device according to claim 6, wherein at least one of said first gate insulating films provided on an active region sharing said first gate electrode is an oxynitride film. 9. The method for manufacturing a nonvolatile semiconductor memory device according to claim 1.