JP2006190820A - Charge injection method of nonvolatile memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a so-called NAND-type MONOS memory device in which data can be optionally written in or erased from one of memory transistors by the bit. <P>SOLUTION: In a writing operation, electrons are separately injected into the first and second part of a charge storage film (ONO film) 30 of a selected memory transistor through a so-called CHE injection method (first and second charge injection step). On the other hand, in an erasing operation, holes induced by a tunnel current between band-band are generated in a source/drain region 22 which functions as a drain when electrons are injected into the first part (A part), and injected into the A part to electrically compensate a part of electrons injected into the A part (third charge injection step). In the third charge injection step, when holes are injected into the second part (a part located opposite to the A part), the function of the source is replaced with that of the drain. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to charge injection in a nonvolatile memory device having a so-called NAND string (transistor string) and capable of electrically writing and erasing data to a selected memory transistor.

  Currently, many types of memory cell systems have been proposed for a batch erase type nonvolatile memory device (flash memory) having a floating gate (FG). Among them, the cell size is small and the capacity can be increased. A NAND type is known as a cell system. The NAND flash memory has a transistor string called a NAND string in which a plurality of memory transistors are connected in cascade between two select transistors.

In a NAND flash memory, both data writing and erasing are performed by FN (Fowler Nordheim) tunnel current, and data that can be stored in one memory transistor is usually one binary data, that is, one bit data. In order to further increase the capacity, in addition to miniaturization of elements, a multilevel technology capable of storing a plurality of bits in one memory transistor is important.
However, in the multi-value processing which is normally performed in the memory transistor having the FG structure, the charge injection region is a conductor (polysilicon FG), so that local charge injection cannot be performed. Therefore, multi-level storage is performed for memory transistors having an FG structure in which a plurality of bits are stored by finely dividing a threshold voltage of a storage state. However, with this multi-value technology, control of peripheral circuits is complicated, and errors due to fluctuations in threshold voltage are likely to occur.

A nonvolatile memory device having a structure capable of storing 2 bits by changing the FG type gate structure to a MONOS type and performing local charge injection to one memory transistor is known (for example, Patent Document 1).
In this nonvolatile memory device, writing is achieved by hot hole injection caused by band-to-band tunnel current, and erasure is performed in block units by FN tunnel current.
JP 2003-163292 A

By the way, for example, an EEPROM built in a security card may require a byte rewriting function. In byte rewriting applications, it is necessary to perform erasing and writing independently every 8 bits.
However, the byte rewriting is not possible with the technique described in Patent Document 1. This is because erasing is performed in units of blocks by the FN tunnel current.

  The problem to be solved by the present invention is that in a so-called NAND-type non-volatile memory device capable of storing 1 bit in each of two different parts of the same charge storage film in the memory transistor for a total of 2 bits, one memory It is possible to arbitrarily perform writing and erasing of data with respect to a transistor in bit units.

  A method for injecting charge into a nonvolatile memory device according to the present invention includes a first and a second select transistor whose on and off are independently controlled, and a plurality of memories cascaded between the first and the second select transistors. A non-volatile memory device having a transistor array including the transistor, and a charge injection of the non-volatile memory device that changes a data storage state by injecting a charge into the memory transistor selected from the plurality of memory transistors A method is provided in which a channel is formed between a source and a drain of the selected memory transistor, and a first polarity charge traveling through the channel is changed to a charge existing between a gate and a channel of the selected memory transistor. A first current injected into the first local portion on the drain side of the storage film. The function of the drain and the source in the injection step and the first charge injection step is exchanged, and the first local portion of the charge storage film is reversed by reversing the direction in which the first polarity charge travels in the channel. A second charge injection step of injecting into the second local portion on the opposite side of the first charge other than the first polarity charge injected by the first charge injection step; A second polarity charge caused by a band-to-band tunnel current is generated on the source / drain region side that functions as the drain when the first polarity charge is injected into the local portion or the second local portion, and the second polarity charge is The first pole injected independently into the first local part or the second local part and injected into the first local part or the second local part by the injected second polarity charge. Including a third charge injection step of electrically offset at least a portion of the charge.

  According to the present invention, in a so-called NAND-type non-volatile memory device capable of storing 1 bit in each of two different parts of the same charge storage film in the memory transistor, a total of 2 bits, data for one memory transistor can be stored. Writing and erasing can be arbitrarily performed in bit units.

  Hereinafter, embodiments of a nonvolatile memory device according to the present embodiment will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a basic configuration of a memory cell array of a NAND MONOS memory device (hereinafter simply referred to as “nonvolatile memory”).
In FIG. 1, NAND strings are repeatedly arranged as a basic configuration of the memory cell array 1. In FIG. 1, four NAND strings are shown.
Each NAND string includes a first select transistor S1, a second select transistor S2, and n (for example, n = 8, 16) memory transistors M1 to Mn cascaded in the column (COLUMN) direction therebetween. It is configured. In FIG. 1, the number of memory transistors in each NAND string is four for convenience of drawing.

In the first NAND string NS1 including the memory transistors M11, M12, M13, and M14, the first select transistor S1 is connected to the bit line BL2, and the second select transistor S2 is connected to the bit line BL1.
In the second NAND string NS2, which is adjacent to the first NAND string NS1 and includes the memory transistors M21, M22, M23 and M24, the first select transistor S1 is connected to the bit line BL2, and the second select transistor S2 is connected to the bit line BL3. Connected.
By repeating the same configuration as the first and second NAND strings NS1, NS2, the third NAND string NS3 including the memory transistors M31, M32, M33 and M34 and the fourth NAND string NS4 including the memory transistors M41, M42, M43 and M44 are performed. And are formed.

In the first to fourth NAND strings NS1 to NS4 arranged in the row (ROW) direction, the first select transistors S1 of the first and third NAND strings NS1 and NS3 are controlled by the first select gate line SG1, and the second and fourth NAND strings. The first select transistors S1 of NS2 and NS4 are controlled by the second select gate line SG2. The second select transistors S2 of the first and third NAND strings NS1 and NS3 are controlled by the third select gate line SG3, and the second select transistors S2 of the second and fourth NAND strings NS2 and NS4 are controlled by the fourth select gate line SG4. Is done.
In the first to fourth NAND strings NS1 to NS4, the four memory transistors M1i, M2i, M3i, and M4i (i = 1 to 4) arranged in each row (LOWROW) are wired in the row direction, respectively. Are controlled by the word lines WL1, WL2, WL3, WL4.

  Thus, in this example, the memory cell array 1 is formed by pairing two adjacent NAND strings. Although the present invention is not limited to such an array configuration, the bit line contacts BC1 to BC5 are shared by two adjacent NAND strings, and the effective cell area per bit is reduced in FIG. The configuration shown is desirable.

FIG. 2 is a cross-sectional view of the first NAND string NS1 in the column direction.
For example, a P-type well (P well) 21 is formed, for example, on the surface side in the N-type semiconductor substrate 20, and transistor rows are arranged on the surface side of the P well 21.

  The memory transistors M11 to M1n have a charge storage film 30 formed by laminating a plurality of dielectric films on the P well 21. Further, word lines WL <b> 1 to WLn are stacked on the charge storage film 30. The word lines WL1 to WLn are generally made of doped polycrystalline silicon into which a P-type or N-type impurity is introduced at a high concentration, or a laminated film of doped polycrystalline silicon and a refractory metal silicide.

Source / drain regions 22 are formed by introducing N-type impurities into the surface portion of the P well 21 below the word lines.
The source / drain region 22 is a region having high conductivity formed by introducing a reverse conductivity type impurity into the P well 21 at a high concentration, and has various forms. Although omitted in the figure, regions of different concentrations called extension regions may be provided at both ends in the column direction of the source / drain regions 22.

  The first and second select transistors S1 and S2 are constituted by normal MOSFETs. Therefore, the gate insulating film 34 is formed of a single layer film made of, for example, silicon dioxide. The gate electrode layers of the first and second select transistors S1 and S2 constitute a first select gate line SG1 and a third select gate line SG3, respectively.

On the select transistor and the memory transistor, an interlayer insulating film 23 made of, for example, silicon dioxide is thickly deposited. The interlayer insulating film 23 is composed of a plurality of films.
N-type impurities are added at a high concentration to the surface portion of the P well 21 adjacent to the first select gate line SG1, thereby forming the source / drain regions 24 of the first select transistor. The source / drain region 24 is shared with another NAND string (not shown) adjacent in the column direction (second NAND string NS2: see FIG. 1), and on top of that, the bit contact BC2 ( 1) is formed.
Similarly, an N-type impurity is added at a high concentration to the surface portion of the P well 21 adjacent to the second select gate line SG2, thereby forming the source / drain region 25 of the second select transistor. A bit contact BC 1 is formed on the source / drain region 25.
Bit contact BC1 is formed by filling the contact hole opened in interlayer insulating film 23 with a metal plug such as tungsten (W) with an adhesion layer such as Ti / TiN interposed therebetween.
A bit line BL1 connected to the bit contact BC1 is formed on the interlayer insulating film 23. For example, the bit line BL1 has a three-layer structure in which a main wiring layer made of aluminum (Al) or the like is sandwiched between an antireflection layer (or a protective layer) and a barrier metal.

The nonvolatile memory transistor having the charge storage means in this embodiment and capable of storing electrical data includes a gate electrode (word lines WL1 to WLn) and a semiconductor region (P well 21) in which a channel is formed. The charge storage film 30 between them is a MONOS type composed of an ONO (Oxide-Nitride-Oxide) film.
Here, the “charge storage means” is a charge storage medium that is formed in the charge storage film 30 and exchanges charges with the substrate side in accordance with the voltage applied to the gate electrode thereabove to hold the charges. Say. The charge storage means in the MONOS type cell means a carrier trap in the nitride film bulk of the ONO film or a deep carrier trap formed near the interface between the oxide film and the nitride film.

The charge storage film 30 in the present embodiment includes a first oxide film 31, a nitride film 32, and a second oxide film 33 in order from the lower layer.
The first oxide film 31 is made of, for example, silicon dioxide (SiO ₂ ) formed by thermal oxidation. Note that a thin nitrided oxide layer may be formed on at least the surface portion of the first oxide film 31 by thermal nitridation.
The nitride film 32 is made of, for example, a silicon nitride (Si _x N _y (0 <x <1, 0 <y <1)) film. The nitride film 32 is produced by, for example, low pressure CVD (LP-CVD).
The second oxide film 33 needs to be formed with a high density of deep carrier traps in the vicinity of the interface with the nitride film 32. For this reason, the second oxide film 33 is formed, for example, by thermally oxidizing the nitride film after film formation. When the second oxide film 33 is formed by thermal oxidation, this trap is formed by heat treatment. The second oxide film 33 has a thickness necessary for effectively preventing hole injection from the gate electrode (word line) and preventing a decrease in the number of times data can be rewritten.

  In manufacturing the NAND string, first, after forming an element isolation insulating layer and a P well 21 (not shown) on the prepared semiconductor substrate 20, ion implantation for adjusting the gate threshold voltage of the memory transistor is required. Depending on.

Next, the charge storage film 30 is formed on the P well 21 by the following procedure, for example.
A heat treatment is performed at 1000 ° C. for 10 seconds by a short time high temperature heat treatment method (RTO method) to form a silicon dioxide film (first oxide film 31).
Next, a silicon nitride film (nitride film 32) is deposited on the first oxide film 31 by LP-CVD so as to have a final film thickness of 8 nm. This CVD is performed at a substrate temperature of 650 ° C. using a gas in which dichlorosilane (DCS) and ammonia are mixed, for example.
The formed silicon nitride film surface is oxidized by a thermal oxidation method to form, for example, a 3.5 nm silicon oxide film (second oxide film 33). This thermal oxidation is performed, for example, for about 40 minutes while maintaining the temperature in the furnace in an H ₂ O atmosphere at 950 ° C. As a result, deep carrier traps having a trap level (energy difference from the conduction band of the silicon nitride film) of about 2.0 eV or less are formed at a density of about 1 to 2 × 10 ¹³ / cm ² . Further, a thermal silicon oxide film (second oxide film 33) is formed to have a thickness of 1.6 nm with respect to 1 nm of the silicon nitride film constituting the nitride film 32, and the underlying silicon nitride film thickness is reduced at this rate. The final film thickness is 8 nm.

  If necessary, the charge storage film 30 having a three-layer structure is removed at a portion other than the memory transistor array, and a silicon oxide film to be the gate insulating film 34 of the select transistors S1 and S2 is formed by thermal oxidation to a few nm. In this case, in order to protect the charge storage film 30, it is desirable to form a film of a material that can be selectively removed later on the charge storage film 30. Since the first and second select transistors S1 and S2 are not subjected to such a high electric field that charge injection occurs, the gate insulating film 34 of these select transistors can have the same structure as the charge storage film 30. In this case, the step of removing the charge storage film 30 is not necessary.

  A conductive film to be a word line is stacked. Then, the conductive film and the charge storage film 30 (and the gate insulating film 34) thereunder are patterned at once. Thereby, the word lines WL1, WL2, WL3,... WLn, the first select gate line SG1 and the third select gate line SG3 are formed simultaneously.

In the state where the parallel stripe-shaped wirings long in the row direction are formed, N-type impurities are ion-implanted into the well surface between the wirings, and annealing is performed. As a result, source / drain regions 22 are formed between the word lines and between the word line and the gate of the select transistor, and further, source / drain regions 24 and 25 are formed between the gates of the select transistor.
Through the above steps, for example, 128 to 256 NAND strings including 8 to 16 memory transistors are formed in the row direction. One rewrite unit (block) is configured by the number of cells of the product of the number of cells connected to one word line and the number of word lines in the NAND string.

By embedding the memory transistor and the select transistor, an interlayer insulating film 23 made of, for example, silicon dioxide is formed by CVD, and an opening for bit contact is formed in the interlayer insulating film 23. In FIG. 2, the opening is opened on the source / drain region 25. A plug material, for example, tungsten is deposited so as to completely fill the opening, and this is etched back on the entire surface to separate the plug material on the interlayer insulating film 23. As a result, a bit contact BC 1 made of a plug connected to the source / drain region 25 is formed so as to be embedded in the interlayer insulating film 23. A bit line BL1 connected to the bit contact BC1 is formed.
Thereafter, if necessary, another interlayer insulating film and an upper layer wiring are formed, and finally the nonvolatile memory cell array is completed through an overcoat film formation and a pad opening process.

  Next, the overall configuration of the non-volatile memory including the peripheral circuit and the schematic operation of the peripheral circuit based on FIG. 1 will be described.

FIG. 3 shows a schematic configuration of the nonvolatile memory device.
The nonvolatile memory device illustrated in FIG. 3 includes a memory cell array (MCA) 1 and a memory peripheral circuit that controls the operation of the memory cell array 1.
The memory peripheral circuit includes a column buffer 2a, a row buffer 2b, a main row decoder (MR.DEC) 3, a sub row decoder (SR.DEC) 4, a column decoder (C.DEC) 5, a word line driving circuit (WDR) 6, Page latch circuit 7, column selection circuit (C.SEL) 8, sense amplifier (SA) array 9, voltage generation circuit 10A for generating voltages to be supplied to word lines, voltage generation for generating voltages to be supplied to wells in each block A circuit 10B and a control circuit (CONT) 11 that controls the operation timing thereof by a control signal CS are provided.

The basic operation of the memory peripheral circuit will be briefly described as follows, for example.
First, an address signal ADR (address bits A1 to Am + n) inputted in a state where a chip enable signal (not shown) is “high (H)” is passed through an address buffer (column buffer 2a and row buffer 2b) to the main row decoder 3. And input to the column decoder 5.
A block selection bit included in a part of the input address signal (address bits Am + 1 to Am + n) is decoded by the main row decoder 3, thereby selecting a block including a NAND string to be operated. The remaining bits of the address bits Am + 1 to Am + n are decoded by the sub row decoder 4, whereby a predetermined word line (memory cell row) in the selected block is selected. A predetermined voltage generated by the voltage generation circuit 10A is connected to the selected word line from the word line driving circuit 6 to the selected word line in the sub-row decoder 4, and a predetermined voltage is applied to the selected word line.
By a similar control, a voltage (pass voltage) that is lower than the selected word line and that turns on the memory transistor is normally applied to the unselected word line. In addition, a voltage corresponding to the power supply voltage is normally applied from the sub row decoder 4 to the select gate line SG in the selected block.

On the other hand, the remaining address bits A 1 to Am of the input address signal ADR are decoded by the column decoder 5, and the column selection signal YS of the selected column designated by this address bit is output to the column selection circuit 8. In the column selection circuit 8, a predetermined voltage generated by the voltage generation circuit 10B is supplied through the page latch circuit 7 to the bit line BL specified according to the column selection signal YS.
The page latch circuit 7 can hold data in units of pages (a group of memory cells connected to one word line), and a selected block in units of arbitrary data (for example, 1 word, 8 bytes) in the page. To the bit line BL. The SA array 9 is activated at the time of reading, amplifies the potential difference appearing on the bit line BL, and outputs it as read data to a bus (not shown).
The voltage generation circuit 10B supplies a predetermined voltage to the well of the selected block in response to the control signal CS from the control circuit 11 and the block selection signal (not shown) from the main row decoder 3.

  In this basic operation, the voltage applied to the word line WL, the voltage applied to the select gate line SG, the voltage applied to the bit line BL, the voltage applied to the well, and their application timing are written, It differs depending on the erasing and reading modes and the specific operation method in each mode. The timing control is controlled in the entire memory peripheral circuit by a control signal CS generated by the control circuit 11 based on the clock.

In this embodiment, the memory cell array shown in FIG. 1 and FIG. 2 copes with byte rewriting use by giving a bias application condition capable of erasing and writing for each bit from the memory peripheral circuit shown in FIG.
Normally, data is rewritten by an erase operation and a subsequent write operation. The operation of writing data by injecting electrons into the charge storage means in the ONO film and erasing data by injecting holes into the charge storage means will be described below. The definition of writing and erasing data may be reversed. That is, the state in which electrons are injected into the memory transistor to be rewritten is the erased state, and data may be written by injecting holes into an arbitrary memory cell from this erased state.

First, data writing will be described.
FIG. 4A shows voltage application conditions in the memory transistor to be written, and FIG. 4B shows voltage application conditions in the memory cell array. FIGS. 5A to 5K are timing charts of the write operation.
Here, at the time of writing, electrons are injected into the local portion of the charge storage film by channel hot electron injection. FIG. 4B illustrates a case where the memory transistor selected by writing is connected to the word line WL3.

First, an outline of voltage application at the time of writing in this embodiment will be described.
From the memory transistors connected to the word line WL3, one memory transistor is selected for every 2 n powers, corresponding to the number of bits of write data (write word). In the example of FIG. 4B, one memory transistor, here, memory transistors M13 and M33 is selected every two because of the relationship shown.
For this purpose, as shown in FIG. 4B, the program voltage 9V, which is the highest positive voltage, is applied to the word line WL3, and the other word lines WL1, WL2, and WL4 apply 6V as the pass voltage.
On the other hand, a write drain voltage of 4.5 V is applied to every other even-numbered bit lines BL2 and BL4. The odd-numbered bit lines BL1, BL3 and BL5 and the P well 21 (see FIG. 2) are held at the ground voltage of 0V. A voltage sufficient to turn on the select transistor, for example, 6 V, is applied to the necessary ones of the first to fourth select gate lines SG1 to SG4.

FIG. 4A shows the memory transistor M13 (and M33) under these voltages. As indicated by reference symbol A in FIG. 4 (A), channel hot is provided locally on the drain side (side supplying a positive voltage of 4.5 V) with respect to the charge storage film 30 of the memory transistor M13 (and M33). Electrons are injected by electron injection.
When electrons are injected into the local portion on the opposite side of the charge storage film 30, the voltage relationship between the bit lines BL1 and BL2, the voltage relationship between the bit lines BL3 and BL4, and the voltage relationship between the select gate lines SG2 and SG4 are as described above. And reverse.

Next, specific voltage application timings for electron injection into the local part A shown in FIG. 4A will be described with reference to FIG.
This description can be similarly applied to the injection of electrons to the local part on the opposite side on the assumption that the voltage relationship is reversed.

During the data writing period, as shown in FIGS. 5I and 5K, the odd-numbered bits BL1, BL3 and BL5 and the P-well are kept at 0V.
In a period (T1) before data writing, write data is set to each bit line from the page latch circuit 7 shown in FIG. Here, as shown in FIG. 5J, for even-numbered bit lines BL2 and BL4, 4.5V is applied when electrons are injected into the drain side local portions of the corresponding memory transistors M13 and M33, and 0V is applied otherwise. Set. In the data setting period T1 for the bit line, all other lines, that is, the word lines WL1 to WL4 and the first to fourth select gate lines SG1 to SG4 are set to 0V.

As shown in FIGS. 5A and 5C, at time T2, the voltages of the first and third select gate lines SG1 and SG3 are raised from 0V to 6V. At the same time (time T2), as shown in FIGS. 5E, 5F, and 5H, the voltages of the unselected word lines WL1, WL2, and WL4 are raised from 0V to 6V.
The voltage of the unselected word lines WL1, WL2, and WL4 is set to 6V because the unselected memory transistors M11, M12, M14, M31, M32, and M34 function as pass transistors, and the even-numbered bit lines BL2 and BL4 are connected to each other. This is because the set voltage (0 V or 4.5 V) is transmitted to the drains of the memory transistors M13 and M33 to be written (source / drain region 22: see FIG. 2).
In FIG. 4B, the memory transistors M23 and M43 that are in the non-selected column and are connected to the word line WL3 have the second select gate SG2 as shown in FIG. The voltage is maintained at 0V. As shown in FIG. 5D, the voltage of the fourth select gate SG4 may be 0V or 6V during the write operation period including this time T2.

At time T2, as shown in FIG. 5G, the selected word line WL3 is kept at 0V, and the memory transistors M13 and M33 to be written are maintained in the OFF state. By doing so, the voltages (0 V or 4.5 V) of the even-numbered bit lines BL2 and BL4 are transmitted to the drains of the transistors M13 and M33 to be written before the actual writing is started (next time T3). Then, a time lag is given to transmit the voltage 0V of the odd-numbered bit lines BL1 and BL3 to the source.
Taking the first NAND string as an example, when the voltage of the bit line BL2 is 4.5V, 4.5V is applied between the source and drain of the memory transistor M13, but when the voltage of the bit line BL2 is 0V. A potential difference does not occur between the source and drain of the memory transistor M13. Further, regarding the memory transistors M11, M12, and M14, these function as pass transistors, and the source voltage and the drain voltage become the same voltage, so that no voltage difference occurs between the source and the drain.

Next, at time T3, as shown in FIG. 5G, the selected word line WL3 is raised from 0V to 9V. As a result, a channel is formed in the memory transistor having a source-drain voltage of 4.5 V among the memory transistors M13 and M33 to be written, and electrons supplied from the source to the channel obtain energy on the drain side, The part becomes hot electrons. A part of the hot electrons is injected into the drain side local portion A of the charge storage film 30 by the program voltage 9 V applied to the word line WL3 (see FIG. 4A).
At a time T4 when a predetermined time corresponding to a predetermined write pulse width elapses, the voltage of the selected word line WL3 is lowered from 9V to 0V.
Thereafter, at time T5, as shown in FIGS. 5A to 5H, all the word lines WL1 to WL4 and all the select gate lines SG1 to SG4 are returned to 0 V, thereby completing the write operation.

  In the above write operation, since the source and drain (and P well) are held at 0 V in the non-selected memory transistors M23 and M43 connected to the word line WL3 and applied with the program voltage 9 V to the gate, the program is performed. When the voltage is high, electrons are injected from the entire surface of the channel by the Fowler-Nordheim (FN) tunnel mechanism. However, in this example, the program voltage is 9 V, which is sufficiently lower than the FG type write voltage, and such electron injection does not occur. In addition, since the pass voltage 6V is sufficiently low as described above in the memory transistors of other non-selected rows, that is, the pass transistors M11 to M41, M12 to M42, and M14 to M44, similarly, the injection of electrons is effectively prevented. The

  When it is desired to further reduce the possibility that electrons are accidentally injected into the non-selected memory transistors M23 and M43 connected to the selected word line WL3 at the time of data writing, the program is changed by changing the device structure. It is effective to reduce the voltage value from 9V. As a result, the reliability of the nonvolatile memory can be improved and the voltage can be lowered, and the high voltage process required for the word line drive circuit (WDR) 6 and the voltage generation circuit 10A shown in FIG. 3 can be simplified or deleted. In this sense, application of this device structure is desirable.

FIG. 6 schematically shows the device structure after this change.
As shown in FIG. 6, for each of two source / drain regions (N ⁺ ) 22 located on both sides of the gate electrode (word line WL) in the channel direction, a P well in which a channel is formed on the opposite side. A high concentration channel region (P ⁺ ) 26 having the same P type as (P ⁻ ) 21 but having a higher concentration is formed. This formation can be easily performed by a method such as oblique ion implantation after forming the gate electrode.
The high-concentration channel region (P ⁺ ) 26 locally increases the channel direction electric field between the high-concentration channel region (P ⁺ ) 26 and the source / drain regions (N ⁺ ), and hot electrons are easily generated here. As a result, the injection efficiency of hot electrons into the ONO film (charge storage film 30) is increased. Therefore, the gate voltage (program voltage) can be lowered if the writing speed is the same.
For example, if the design of the impurity concentration profile of the channel and drain including the high-concentration channel region (P ⁺ ) 26 is optimized, even if the voltage of the selected word line WL3 shown in FIG. The same writing speed can be achieved. As a result, in each of the non-selected memory transistors M23 and M43, 6V is applied between the gate and the P-well (or between the gate and the channel), and electrons are mistakenly applied to the non-selected memory transistors. The possibility of tunnel injection is reduced.

Next, data erasure will be described.
FIG. 7A shows voltage application conditions in the memory transistor to be erased, and FIG. 7B shows voltage application conditions in the memory cell array. FIGS. 8A to 8K are timing charts of the erase operation.
Here, data is erased by injecting hot holes using a band-to-band tunneling current capable of erasing bit by bit into the local portion A (electron holding portion) of the charge storage film. FIG. 7B illustrates a case where the memory transistor selected for erasing is connected to the word line WL3.

First, an outline of voltage application at the time of erasing in the present embodiment will be described.
One memory transistor is selected from the memory transistors connected to the word line WL3 for every 2 n powers, corresponding to the number of bits of erase data (erase word). In the example of FIG. 7B, one memory transistor, two memory transistors M13 and M33 in this example, are selected every two because of the illustrated relationship.
For this purpose, as shown in FIG. 7B, an erase gate voltage (−5V) which is a negative voltage is applied to the word line WL3, and 7V is applied as the pass voltage to the other word lines WL1, WL2 and WL4. To do.
On the other hand, an erase drain voltage of 5 V is applied to every other even-numbered bit lines BL2 and BL4. The odd-numbered bit lines BL1, BL3 and BL5n and the P well 21 (see FIG. 2) are held at the ground voltage of 0V. The P well 21 may be held at about 1V. A voltage sufficient to turn on the select transistor, for example, 7 V, is applied to necessary ones of the first to fourth select gate lines SG1 to SG4.

FIG. 7A shows the memory transistor M13 (and M33) under these voltages. As shown by reference symbol A in FIG. 7A, a band-to-band tunneling current is locally present on the drain side (the side supplying the positive voltage 5 V) with respect to the charge storage film 30 of the memory transistor M13 (and M33). Hot hole injection using this is performed.
When holes are injected into the local portion on the opposite side of the charge storage film 30, the voltage relationship between the bit lines BL1 and BL2, the voltage relationship between the bit lines BL3 and BL4, the voltage relationship between the select gate lines SG1 and SG3, and the select gate The voltage relationship between the lines SG2 and SG4 is reversed from the above.

  Next, a specific voltage application timing of hole injection to the local part A shown in FIG. 7A will be described with reference to FIG. This description can be similarly applied to hole injection into the local part on the opposite side on the assumption that the voltage relationship is reversed.

During the data erasing period, as shown in FIGS. 8I and 8K, the odd-numbered bits BL1, BL3 and BL5 are kept at 0V and the P-well is kept at 0V or 1V.
In a period (T1) before data erasure, erase data is set to each bit line from the page latch circuit 7 shown in FIG. Here, as shown in FIG. 8J, for even-numbered bit lines BL2 and BL4, 5 V is set when holes are injected into the drain side local portions of the corresponding memory transistors M13 and M33, and 0 V is set otherwise. . In the data setting period T1 for the bit line, all other lines, that is, the word lines WL1 to WL4 and the first to fourth select gate lines SG1 to SG4 are set to 0V.

As shown in FIG. 8G, at time T2, the selected word line WL3 is lowered from 0V to −5V.
At subsequent time T3, as shown in FIGS. 8A, 8C, 8F and 8H, the first, third and fourth select gate lines SG1, SG3 and SG4 and the unselected word Lines WL1, WL2 and WL4 are raised from 0V to 7V.
The voltage of the unselected word lines WL1, WL2, and WL4 is set to 7V because the unselected memory transistors M11, M12, M14, M31, M32, and M34 function as pass transistors, and even-numbered bit lines BL2 and BL4 This is because the set voltage (0 V or 5 V) is transmitted to the drains of the memory transistors M13 and M33 to be erased (source / drain region 22: see FIG. 2).
In FIG. 7B, the memory transistors M23 and M43 in the non-selected column and connected to the word line WL3 have the second select gate SG2 as shown in FIG. 8B to prevent erasure. The voltage is maintained at 0V.

At time T3, the selected word line WL3 remains at −5V as shown in FIG. By doing so, in the memory transistor M13 and M33 to be written, the voltage supplied to the drain of the memory transistor M13 through the pass transistor is about 10 V between the drain and the gate (word line WL3). The erase voltage is applied.
As a result, in the drain (source / drain region 22: see FIG. 2), the surface becomes a deep depletion state, the bending of the energy band increases, and the electrons are tunneled from the valence band to the conduction band by the band-band tunneling phenomenon. To do. At this time, an electron-hole pair is generated, and the electron flows into the N-type source / drain region 22 and is absorbed. On the other hand, the generated holes are accelerated by a high electric field applied in the vicinity of the junction to become hot holes, and drift toward the center of the channel formation region. A part of this hot hole is locally injected into the local part A (see FIG. 7) in the charge storage film 30.
For this reason, when the selected memory transistor M13 or M33 is in a writing state in which electrons are injected into the local A and the threshold voltage is high, the electrons accumulated by the injected hot holes are canceled by the holes. As a result, the threshold voltage of the memory transistor is lowered to a low level in the erased state.

During this erase operation, as shown in FIG. 7B, the gate voltages of the third and fourth select gates SG3 and SG4 and the non-selected word line for controlling the non-selected memory transistor row adjacent thereto are controlled. WL4 may be set to 0V. In this case, the select transistor S2 and the non-selected memory transistors M14 and M34 are all turned off, and the sources of the memory transistors M13 and M33 to be erased (the other source / drain region 22: see FIG. 2) are in an electrically floating state. (So-called open state).
At a time T4 when a predetermined time corresponding to a predetermined erase pulse width has elapsed, as shown in FIGS. 8A, 8C, 8F, and 8H, the first, third, and fourth select gate lines. SG1, SG3 and SG4 and unselected word lines WL1, WL2 and WL4 are lowered from 7V to 0V.
Thereafter, at time T5, as shown in FIG. 8G, the selected word line WL3 is returned to 0 V, thereby ending the erase operation.

  As shown in FIG. 7B, the voltage of the P-well 21 is normally 0V, but a small positive voltage (for example, 1V) can be applied. In this case, the NPN transistor operation is performed with the emitter as the source, the P well as the base, and the drain as the collector. Electron-hole pairs are generated positively by impact ionization between the collector and the base, and the amount of generated holes is increased. It is desirable to bias the P-well slightly positive because it increases and erase efficiency is further improved.

  Both the write operation and the erase operation shown above can be selected for each bit. Therefore, conversely, in this embodiment, as described above, the write operation may be regarded as an erase operation, and the erase operation may be regarded as a write operation.

  In the data read operation, the bias of the drain and source when reading data is reversed during normal data read (hereinafter referred to as the forward read method) in which current flows from the drain to the source during data write. The reading is performed by one of reverse readings (hereinafter referred to as a reverse reading method) in which a current flows from the source to the drain during writing. The case of the reverse read method is shown below.

FIG. 9A shows voltage application conditions in the memory transistor to be read, and FIG. 9B shows voltage application conditions in the memory cell array. FIGS. 10A to 10K are timing charts of the read operation.
Here, FIG. 9B illustrates the case where the memory transistor to be read is connected to the word line WL3.

Data reading may be performed in batches of word lines, that is, page reading, but here, a reading operation in which reading can be performed in units of words corresponding to word writing and word erasing is described. Memory transistor connected to word line WL3 One memory transistor is selected every 2 n to the number corresponding to the number of bits of read data (read word). In the example of FIG. 9B, one memory transistor, here, memory transistors M13 and M33 is selected every two because of the illustrated relationship.
For this purpose, as shown in FIG. 9B, a read gate voltage 1... Between a threshold voltage after writing (for example, 2 V) and a threshold voltage after erasing (for example, 0.5 V) is applied to the word line WL3. 5 V is applied, and 3 V is applied to the other word lines WL1, WL2, and WL4 as a voltage that always turns on regardless of the write and erase states of the memory transistor.
On the other hand, in the reverse read method, a reference voltage at the time of reading, for example, 0 V, is applied to every other even-numbered bit lines BL2 and BL4. Further, a read drain voltage of 1.5 V is applied to the odd-numbered bit lines BL1, BL3 and BL5. In the forward read method, the voltages for the even-numbered bit lines and the odd-numbered bit lines are switched.
The P well 21 (see FIG. 2) is held at a ground voltage of 0V. A voltage sufficient to turn on the select transistor, for example, 3 V, is applied to the necessary ones of the first to fourth select gate lines SG1 to SG4.

  FIG. 9A shows the memory transistor M13 (and M33) under these voltages. As indicated by reference numeral A in FIG. 9A, the channel of the memory transistor M13 (and M33) of the memory transistor M13 (and M33) depends on the accumulated charge amount of the local A that has become the drain at the time of writing. Is conductive (on state) or nearly non-conductive (off state). The read current varies depending on whether the channel is on or off. This current fluctuation is amplified by the SA array 9 shown in FIG. 3 and read as data.

Next, specific voltage application timing when data written in the local part A shown in FIG. 9A is read will be described with reference to FIG.
This description can be similarly applied to the case where the data written in the local part on the opposite side is read out on the assumption that the voltage relationship between the odd-numbered bit line and the even-numbered bit line is inverted. Note that the following description can be applied as it is to reading data written in the opposite local part in the forward reading method.

  During the data read period, as shown in FIGS. 10I to 10K, the odd-numbered bits BL1, BL3, and BL5 are held at the read drain voltage of 1.5 V, and the even-numbered bit lines BL2 and BL4, and The P-well is kept at 0V. Note that the odd-numbered bit lines need to be in a floating state by the time T2 after applying 1.5V.

As shown in FIGS. 10A and 10C, at time T2, the voltages of the first and third select gate lines SG1 and SG3 are raised from 0V to 3V. At the same time (time point T2), as shown in FIGS. 10E, 10F, and 10H, the voltages of the unselected word lines WL1, WL2, WL4 are raised from 0 V to 3 V, and FIG. The voltage of the selected word line WL3 is raised from 0V to 1.5V as shown in FIG.
The voltage of the unselected word lines WL1, WL2, and WL4 is set to 3V because the unselected memory transistors M11, M12, M14, M31, M32, and M34 function as pass transistors, and even-numbered bit lines BL2 and BL4 are connected to each other. The set voltage 0V is transmitted to the sources of the memory transistors M13 and M33 to be written, and the voltage 1.5V set to the odd-numbered bit lines BL1, BL3 and BL5 is transferred to the memory transistors M13 and M13 to be written. This is for transmission to the drain of M33.
As shown in FIGS. 10B and 10D, the memory transistors M23 and M43 in the non-selected column and connected to the word line WL3 in FIG. The voltages of the select gate SG2 and the fourth select gate SG4 are maintained at 0V. This voltage 0V is maintained during the reading period including this time T2.

Accordingly, in the memory transistors M13 and M33, the memory transistor is turned on or off in accordance with the data writing state (electron holding charge amount) of the local A shown in FIG. Changes and is amplified by the sense amplifier SA (FIG. 3) and read out to the bus.
As shown in FIGS. 10A, 10 </ b> C, and 10 </ b> E to 10 </ b> H, 3 V or 1.5 V is obtained at time T <b> 3 when a sufficient time necessary for such reading has elapsed from time T <b> 2. All the voltages of the word line or select gate line to which the voltage is applied are returned to 0 V, thereby completing the read operation.

The following changes can be made to the memory transistor structure.
The structure of the charge storage film of the transistor is not limited to the so-called MONOS type, and may be, for example, an MNOS type. The film that mainly accumulates charges is not limited to the nitride film 32. For example, a high dielectric film having discrete charges and wraps such as Al ₂ O ₅ or Ta ₂ O ₃ may be used.
The semiconductor on which the memory transistor is formed is not limited to a well such as a P well or a bulk silicon substrate. For example, an SOI semiconductor layer in an SOI substrate or a thin film polysilicon in a stacked structure of the substrate Also good.

This embodiment has the following advantages.
First, all the operations of writing, erasing and reading can be performed in arbitrary units, that is, in units of words (for example, in units of bytes) or finer in units of bits. This is because, in particular, in the present embodiment, in the write and erase operations, two charge injections that allow charge injection in bit units, that is, channel hot electron injection, and hot holes caused by band-to-band tunneling current. This is an advantage brought about by using a combination with injection.

In such a nonvolatile memory that cannot be rewritten in an arbitrary data unit, when replacing data that has been stored up to now with data that differs only partially, the data must be erased once and then rewritten. It is necessary to write new data with different parts. However, many bits of this data are originally unnecessary to be erased, and erasing them and writing the same bit data is wasteful, wastes power, and takes a long time to rewrite. .
However, according to the present embodiment, only bit portions that need to be rewritten can be erased and new data can be written there, so that power consumption can be reduced and rewriting operation speeded up.
In particular, charge injection using a band-to-band tunneling current is performed without forming a local channel, so that there is an advantage that current consumption can be reduced.

Second, since the high-concentration channel region is provided, the program voltage can be reduced particularly in channel hot electron injection. This benefit was obtained from the fact that the electric field concentration in the channel direction is increased as described above, but the same effect is also effective as the concentration of the accelerating electric field in which holes generated due to the band-to-band tunnel current drift. Therefore, it can contribute to the generation of efficient hot holes. In addition, biasing the well slightly at this time also contributes to this efficient hot hole generation.
As described above, the voltage during writing and erasing can be reduced, or the speed during writing and erasing can be improved.

  Thirdly, two bits of data can be stored in one memory transistor, and in addition, since the bit contact has a cell array structure shared by two NAND strings as shown in FIG. There is an advantage that the occupied area is small.

FIG. 11 is an explanatory diagram of the transistor occupation area.
In general, the area of an effective memory cell is represented by the sum of the area occupied by one memory transistor and the area of a portion obtained by dividing the shared portion by the number of memory transistors.
As shown in FIG. 11, the area occupied by the memory transistor in the present embodiment is 5F ² obtained by multiplying the word line pitch 2.5F (F: minimum dimension in the manufacturing process) by the element isolation insulating layer pitch 2F. . Here, the word line is made of polysilicon.
Since there are 2 bits per cell, the area occupied by the transistors per bit is 2.5 F ² , which is relatively small. However, in practice because it must take into account the area of the select transistor and the bit contact in the NAND string, area per bit is a little larger than 2.5F ^2.

  The present invention has a so-called NAND string (transistor string), and can be widely applied to the use of charge injection in a nonvolatile memory device capable of electrically writing and erasing data to a selected memory transistor.

1 is a circuit diagram showing a basic configuration of a memory cell array of a NAND MONOS memory device according to an embodiment of the present invention. It is sectional drawing of the column direction of a 1st NAND string. It is a block diagram which shows schematic structure of a non-volatile memory device. (A) is explanatory drawing which shows the voltage application conditions in the memory transistor of writing object, (B) is a circuit diagram which shows the voltage application conditions in a memory cell array. (A)-(K) are timing charts of a write operation. It is explanatory drawing of the device structure which has a high concentration channel area | region. (A) is explanatory drawing which shows the voltage application conditions in the memory transistor of the erasure | elimination object, (B) is a circuit diagram which shows the voltage application conditions in a memory cell array. (A)-(K) are timing charts of the erase operation. (A) is explanatory drawing which shows the voltage application conditions in the memory transistor of reading object, (B) is a circuit diagram which shows the voltage application conditions in a memory cell array. (A) to (K) are timing charts of the read operation. It is explanatory drawing of a transistor occupation area.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2a, 2b ... Address buffer, 3 ... Main row coder, 4 ... Sub row decoder, 5 ... Column decoder, 6 ... Word line drive circuit, 7 ... Page latch circuit, 8 ... Column selection circuit, 9 ... Sense Amplifier array, 10A, 10B ... voltage generation circuit, 11 ... control circuit, 20 ... semiconductor substrate, 21 ... P well, 22 ... source / drain region, 30 ... charge storage film, 31 ... first oxide film, 32 ... nitride film 33 ... second oxide film, 34 ... gate insulating film, M13, etc .... memory transistor, BL1, etc .... bit line, WL3, etc .... word line, SG1, etc .... select gate line, S1 ... first select transistor, S2 ... second Select transistor, NS1, etc .... NAND string

Claims (5)

In a nonvolatile memory device having a transistor row including first and second select transistors that are independently controlled to be turned on and off, and a plurality of memory transistors connected in cascade between the first and second select transistors A non-volatile memory device charge injection method for changing a data storage state by injecting charge into a memory transistor selected from the plurality of memory transistors,
A channel is formed between the source and the drain of the selected memory transistor, and the first polarity charge traveling through the channel is transferred to the drain of the charge storage film existing between the gate and the channel of the selected memory transistor. A first charge injection step for injecting the first local portion on the side;
The function of the drain and the source in the first charge injection step is exchanged, and the direction in which the first polarity charge travels in the channel is reversed, so that the charge storage film is opposite to the first local portion. A second charge injection step of injecting into the second local portion of the second local charge, another first polarity charge distinguishable from the first polarity charge injected by the first charge injection step;
A second polarity charge caused by a band-to-band tunnel current is generated on the source / drain region side that functions as the drain when the first polarity charge is injected into the first local portion or the second local portion, and the second polarity charge is generated. Polar charge is injected into the first local part or the second local part independently, and at least a part of the first polar charge injected into the first local part or the second local part is injected by the injected second polar charge. A third charge injection step that electrically cancels;
A method for injecting charges in a nonvolatile memory device comprising: The third charge injection step comprises:
A first step of applying a first polarity voltage to the gate formed on the charge storage film including the first local part or the second local part for injecting the second polar charge;
A second step of applying 0V to the source / drain region on the first local side or the second local side to prevent the injection of the second polarity charge, or bringing into an electrically floating state;
A third step of applying a second polarity voltage to the source / drain region on the first local side or the second local side for injecting the second polarity charge;
The method for injecting charges in a nonvolatile memory device according to claim 1, comprising: In the third charge injection step, a semiconductor region having a conductivity type of opposite polarity, which is in contact with the source / drain region on the first local side or the second local side where the second polarity charge is injected, The method of claim 2, further comprising a fourth step of applying a second polarity voltage lower than the second polarity voltage. The semiconductor in which the memory transistor is a semiconductor region having a conductivity type of opposite polarity in contact with the source / drain region on the first local side or the second local side for injecting the second polarity charge, and in which the channel is formed When the semiconductor region has a higher concentration than the region, in the third charge injection step, the source / drain region on the first local side or the second local side into which the second polarity charge is injected is added to the source / drain region in the third step. The charge injection method for a nonvolatile memory device according to claim 2, wherein a second polarity voltage lower than the second polarity voltage is applied. A semiconductor region between the source / drain region functioning as the source and the source / drain region functioning as the drain is in contact with each of the two source / drain regions and has the same conductivity type as the semiconductor region in which the channel is formed The method for injecting charge into a nonvolatile memory device according to claim 1, wherein a high-concentration channel region having a higher concentration is formed.

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