USRE47815E1 - Nonvolatile semiconductor memory device - Google Patents
Nonvolatile semiconductor memory device Download PDFInfo
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- USRE47815E1 USRE47815E1 US15/961,148 US201815961148A USRE47815E US RE47815 E1 USRE47815 E1 US RE47815E1 US 201815961148 A US201815961148 A US 201815961148A US RE47815 E USRE47815 E US RE47815E
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- H01L27/11582—
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Definitions
- Embodiments of the invention relate generally to a non-volatile semiconductor memory device.
- JP-A 2006-190820 discloses a method for selective erasure by using holes resulting from band-to-band tunneling current.
- this method is prone to degradation in reliability because a local electric field is applied to memory cells.
- the operation is unstable because of the narrow driving margin between the selected cell and the non-selected cell.
- a nonvolatile semiconductor memory device including: a memory unit; and a control unit, the memory unit including a first memory string, a first wiring, a second memory string, and a second wiring, the first memory string including a first memory cell group and a first select transistor, the first memory cell group including a plurality of first memory transistors connected in series, each of the plurality of first memory transistors including a channel formed in a first semiconductor layer, including a first control gate, and allowing data of the each of the plurality of first memory transistors to be electrically rewritten, the first select transistor being provided on one end side of the first memory cell group, including a channel formed in the first semiconductor layer, and including a first select gate, the first wiring being connected to the first semiconductor layer on a side of the first select transistor opposite to the first memory cell group, the second memory string including a second memory cell group and a second select transistor, the second memory cell group including a plurality of second memory transistors connected in series, each of the plurality
- a nonvolatile semiconductor memory device including: a memory unit; and a control unit, the memory unit including a first memory string, a first wiring, a first other wiring, and a first base wiring, the first memory string including a first memory cell group, a first other memory cell group, a first select transistor, a first other select transistor, and a first connecting portion transistor, the first memory cell group including a plurality of first memory transistors connected in series, each of the plurality of first memory transistors including a channel formed in a first semiconductor layer provided in contact with a first base semiconductor layer, including a first control gate, and allowing data of the each of the plurality of first memory transistors to be electrically rewritten, the first select transistor being provided on one end side of the first memory cell group, including a channel formed in the first semiconductor layer, and including a first select gate, the first other select transistor being provided on a side of the first memory cell group opposite to the first select transistor, including a channel formed in the first semiconductor layer,
- FIGS. 1A and 1B are schematic diagrams illustrating the configuration and operation of a nonvolatile semiconductor memory device according to a first embodiment
- FIG. 2 is a schematic perspective view illustrating the configuration of a nonvolatile semiconductor memory device according to a first practical example
- FIG. 3 is a schematic cross-sectional view illustrating the configuration of the nonvolatile semiconductor memory device according to the first practical example
- FIG. 4 is a schematic partial cross-sectional view illustrating the configuration of the nonvolatile semiconductor memory device according to the first practical example
- FIG. 5 is a schematic diagram illustrating the configuration of a nonvolatile semiconductor memory device according to a second embodiment
- FIG. 6 is a table illustrating the operation of the nonvolatile semiconductor memory device according to the second embodiment
- FIG. 7 is a schematic diagram illustrating the configuration of an alternative nonvolatile semiconductor memory device according to the second embodiment
- FIG. 8 is a table illustrating the operation of the alternative nonvolatile semiconductor memory device according to the second embodiment.
- FIG. 9 is a schematic perspective view illustrating the configuration of a nonvolatile semiconductor memory device according to a second practical example.
- FIG. 10 is a schematic cross-sectional view illustrating the configuration of the nonvolatile semiconductor memory device according to the second practical example
- FIG. 11 is a schematic diagram illustrating the configuration of a nonvolatile semiconductor memory device according to a third embodiment
- FIG. 12 is a table illustrating the operation of the nonvolatile semiconductor memory device according to the third embodiment.
- FIG. 13 is a schematic diagram illustrating the configuration of an alternative nonvolatile semiconductor memory device according to the third embodiment.
- FIG. 14 is a table illustrating the operation of the alternative nonvolatile semiconductor memory device according to the third embodiment.
- FIG. 15 is a schematic perspective view illustrating the configuration of a nonvolatile semiconductor memory device according to a third practical example.
- FIGS. 1A and 1B are schematic diagrams illustrating the configuration and operation of a nonvolatile semiconductor memory device according to a first embodiment.
- FIG. 1A is a circuit diagram illustrating the configuration of a nonvolatile semiconductor memory device 101
- FIG. 1B is a table illustrating the operation of the nonvolatile semiconductor memory device 101 .
- FIG. 1A for clarity of illustration, some wirings are not shown.
- the nonvolatile semiconductor memory device 101 includes a memory unit MU and a control unit CTU.
- the memory unit MU includes a first memory string MCS 1 , a first wiring W 11 , a second memory string MCS 2 , and a second wiring W 21 .
- a first bit line BL 1 is used as the first wiring W 11
- a second bit line BL 2 is used as the second wiring W 21 .
- the first memory string MCS 1 includes a first memory cell group MCG 1 and a first select transistor SGT 11 .
- a first drain side select transistor SDT 1 is illustratively used as the first select transistor SGT 11 .
- the first memory cell group MCG 1 includes a plurality of first memory transistors MC 1 A (which are memory cells MC, such as first to fourth memory cells MC 1 to MC 4 ) connected in series. Each of the plurality of first memory transistors MC 1 A allows its data to be electrically rewritten.
- Each of the plurality of first memory transistors MC 1 A includes a first semiconductor layer SEM 1 . That is, the plurality of first memory transistors MC 1 A include a channel formed in the first semiconductor layer SEM 1 . Specifically, a source region, a drain region, and a channel region (channel) of each of the plurality of first memory transistors MC 1 A are provided in the first semiconductor layer SEM 1 .
- Each of the plurality of first memory transistors MC 1 A (first to fourth memory cells MC 1 to MC 4 ) includes a first control gate CG 1 A (control gates CG 1 - 1 to CG 1 - 4 ).
- the first drain side select transistor SDT 1 is provided on one end side of the first memory cell group MCG 1 .
- the first drain side select transistor SDT 1 includes the same first semiconductor layer SEM 1 as the first memory cell group MCG 1 . That is, the first drain side select transistor SDT 1 includes a channel formed in the first semiconductor layer SEM 1 . Specifically, a source region, a drain region, and a channel region (channel) of the first drain side select transistor SDT 1 are provided in the first semiconductor layer SEM 1 .
- the first drain side select transistor SDT 1 includes a first select gate SG 11 . In the following description, a first drain side select gate SGD 1 is illustratively used as the first select gate SG 11 .
- the first bit line BL 1 is connected to the first semiconductor layer SEM 1 on the opposite side of the first drain side select transistor SDT 1 from the first memory cell group MCG 1 .
- the first bit line BL 1 functions as a bit line BL in the first memory string MCS 1 .
- the first memory string MCS 1 further includes a first other select transistor SGT 12 .
- a first source side select transistor SST 1 is illustratively used as the first other select transistor SGT 12 .
- the first source side select transistor SST 1 is provided on the opposite side of the first memory cell group MCG 1 from the first drain side select transistor SDT 1 and includes the first semiconductor layer SEM 1 .
- the first source side select transistor SST 1 includes a first other select gate SG 12 .
- a first source side select gate SGS 1 is illustratively used as the first other select gate SG 12 .
- the memory unit MU further includes a first other wiring W 12 .
- a first source line SL 1 is illustratively used as the first other wiring W 12 .
- the first source line SL 1 is connected to the first semiconductor layer SEM 1 on the opposite side of the first source side select transistor SST 1 from the first memory cell group MCG 1 .
- the first source line SL 1 functions as a source line SL in the first memory string MCS 1 .
- the second memory string MCS 2 includes a second memory cell group MCG 2 and a second select transistor SGT 21 .
- a second drain side select transistor SDT 2 is illustratively used as the second select transistor SGT 21 .
- the second memory cell group MCG 2 includes a plurality of second memory transistors MC 2 A (which are memory cells MC, such as fifth to eighth memory cells MC 5 to MC 8 ) connected in series. Each of the plurality of second memory transistors MC 2 A allows its data to be electrically rewritten.
- the plurality of second memory transistors MC 2 A include a second semiconductor layer SEM 2 electrically isolated from the first semiconductor layer SEM 1 . That is, the plurality of second memory transistors MC 2 A include a channel formed in the second semiconductor layer SEM 2 . Specifically, a source region, a drain region, and a channel region (channel) of each of the plurality of second memory transistors MC 2 A are provided in the second semiconductor layer SEM 2 separate from the first semiconductor layer SEM 1 .
- the respective control gates of the fifth to eighth memory cells MC 5 to MC 8 are commonly connected to the control gates (first control gates CG 1 A, or control gates CG 1 - 1 to CG 1 - 4 ) of the first to fourth memory cells MC 1 to MC 4 .
- the second drain side select transistor SDT 2 is provided on one end side of the second memory cell group MCG 2 .
- the second drain side select transistor SDT 2 includes the same second semiconductor layer SEM 2 as the second memory cell group MCG 2 . That is, the second drain side select transistor SDT 2 includes a channel formed in the second semiconductor layer SEM 2 . Specifically, the source region, the drain region, and the channel region (channel) of the second drain side select transistor SDT 2 are provided in the second semiconductor layer SEM 2 .
- the second drain side select transistor SDT 2 includes a select gate connected to the first drain side select gate SGD 1 .
- the second bit line BL 2 is connected to the second semiconductor layer SEM 2 on the opposite side of the second drain side select transistor SDT 2 from the second memory cell group MCG 2 .
- the second bit line BL 2 functions as a bit line BL in the second memory string MCS 2 .
- the second memory string MCS 2 further includes a second other select transistor SGT 22 .
- a second source side select transistor SST 2 is illustratively used as the second other select transistor SGT 22 .
- the second source side select transistor SST 2 is provided on the opposite side of the second memory cell group MCG 2 from the second drain side select transistor SDT 2 and includes the second semiconductor layer SEM 2 .
- the second source side select transistor SST 2 includes a select gate connected to the first source side select gate SGS 1 .
- the memory unit MU further includes a second other wiring W 22 .
- a second source line SL 2 is illustratively used as the second other wiring W 22 .
- the second source line SL 2 is connected to the second semiconductor layer SEM 2 on the opposite side of the second source side select transistor SST 2 from the second memory cell group MCG 2 .
- the second source line SL 2 functions as a source line SL in the second memory string MCS 2 .
- the number of first and second memory transistors MC 1 A and MC 2 A is four for each.
- the number of first and second memory transistors MC 1 A and MC 2 A is arbitrary as long as it is more than one for each.
- the geometry of the first semiconductor layer SEM 1 and the second semiconductor layer SEM 2 is arbitrary as long as they are electrically isolated from each other.
- the first and second semiconductor layers SEM 1 and SEM 2 are provided on a substrate (e.g., silicon substrate) so as to align in the direction perpendicular to the major surface of the substrate.
- the first and second semiconductor layers SEM 1 and SEM 2 may be an SOI (silicon on insulator) provided on a substrate. In this case, the first and second semiconductor layers SEM 1 and SEM 2 align in a plane parallel to the major surface of the substrate.
- the number of semiconductor layers is arbitrary as long as the first to n-th semiconductor layers are electrically isolated from each other, where n is any integer of two or more.
- the geometry (e.g., positional relation to the major surface of the substrate) of the first to n-th semiconductor layer is arbitrary.
- the first to n-th semiconductor layers are not limited to linearly aligning in one direction but may be folded back in a “U-shape” or “W-shape”, for instance.
- first and second semiconductor layers SEM 1 and SEM 2 illustratively align in one direction.
- the control unit CTU controls the memory unit MU thus configured.
- the control unit CTU is connected to the first drain side select gate SGD 1 and the first bit line BL 1 .
- the control unit CTU is connected to various electrodes and wirings described above to control respective potentials (voltages).
- the erase operation in the nonvolatile semiconductor memory device 101 is the operation for performing at least one of injection of holes into the charge retention layer of the memory cell MC and extraction of electrons from the charge retention layer.
- the charge retention layer is a layer for retaining charge in the memory cell MC and illustratively includes a charge storage layer made of an insulating layer and a floating electrode made of a conductive layer.
- the charge retention layer is illustratively provided between the channel region and the control gate (gate electrode) of the memory cell MC.
- a tunnel insulating film is provided between the charge retention layer and the channel region, and a block insulating film is provided between the charge retention layer and the control gate.
- control unit CTU in selective erasure in the nonvolatile semiconductor memory device 101 .
- the control unit CTU performs the following operation.
- the control unit CTU applies a first voltage V 1 to the first bit line BL 1 .
- the first voltage V 1 is illustratively a high voltage Vpp.
- the high voltage Vpp is illustratively set to 20 volts (V).
- control unit CTU applies a second voltage V 2 lower than the first voltage V 1 to the selected cell gate (control gate CG 1 - 3 ) of the selected cell transistor CL 1 .
- the second voltage V 2 is illustratively 0 volts (0 V, or ground potential, which may be a reference potential).
- control unit CTU applies a third voltage V 3 not higher than the first voltage V 1 and higher than the second voltage V 2 to the non-selected cell gates (in this example, control gate CG 1 - 1 , control gate CG 1 - 2 , and control gate CG 1 - 4 ) of the first memory transistors MC 1 A (in this example, first memory cell MC 1 , second memory cell MC 2 , and fourth memory cell MC 4 ) other than the selected cell transistor CL 1 .
- the third voltage V 3 is illustratively a medium voltage Vm between the high voltage Vpp and 0 V.
- the medium voltage Vm is illustratively set to 10 V.
- control unit CTU applies the first voltage V 1 (high voltage Vpp) or a fourth voltage V 4 not higher than the first voltage V 1 and not lower than the third voltage V 3 to the first drain side select gate SGD 1 of the first drain side select transistor SDT 1 .
- the fourth voltage V 4 is illustratively the medium voltage Vm. In the following description, the medium voltage Vm is illustratively used as the fourth voltage V 4 .
- control unit CTU applies a fifth voltage V 5 higher than the second voltage V 2 and not higher than the third voltage V 3 to the second bit line BL 2 or sets the second bit line BL 2 in a floating state OPN.
- the fifth voltage V 5 is illustratively a low voltage Vcc, which is a voltage higher than the second voltage V 2 (0 V) and not higher than the third voltage V 3 (medium voltage Vm).
- the low voltage Vcc is illustratively set to 3 V.
- the control unit CTU may apply the second voltage V 2 (0 V) to the second bit line BL 2 .
- the first source line SL 1 is subjected to the first voltage V 1 (high voltage Vpp), the low voltage Vcc, or the second voltage V 2 (0 V), or the first source line SL 1 is set in the floating state OPN. Furthermore, the first source side select gate SGS 1 is subjected to the first voltage V 1 (high voltage Vpp) or the fourth voltage V 4 (medium voltage Vm), which is equal to the voltage applied to the first drain side select gate SGD 1 . Furthermore, the second source line SL 2 is subjected to the second voltage (0 V) or the fifth voltage V 5 (low voltage Vcc), which is equal to the voltage applied to the second bit line BL 2 .
- the same voltage as the voltage applied to the control gate (control gates CG 1 - 1 to CG 1 - 4 ) of the first memory string MCS 1 is applied to the control gate of each of the fifth to eighth memory cells MC 5 to MC 8 of the second memory string MCS 2 because the second memory string MCS 2 shares the control gate (control gates CG 1 - 1 to CG 1 - 4 ) with the first memory string MCS 1 .
- the selected cell gate (control gate CG 1 - 3 ) of the selected cell transistor CL 1 is subjected to 0 V, and the first bit line BL 1 and the first source line SL 1 are subjected to the high voltage Vpp.
- the low voltage Vcc is applied to the second bit line BL 2 and the second source line SL 2 .
- the second bit line BL 2 and the second source line SL 2 of the non-selected second memory string MCS 2 may be subjected to the second voltage V 2 (0 V).
- the third memory string MCS 3 includes a third memory cell group MCG 3 and a third select transistor SGT 31 .
- a third drain side select transistor SDT 3 is illustratively used as the third select transistor SGT 31 .
- Each of the plurality of third memory transistors MC 3 A includes a third semiconductor layer SEM 3 .
- the third semiconductor layer SEM 3 is electrically isolated from the first semiconductor layer SEM 1 and the second semiconductor layer SEM 2 .
- Each of the plurality of third memory transistors MC 3 A includes a channel formed in the third semiconductor layer SEM 3 .
- Each of the plurality of third memory transistors MC 3 A (ninth to twelfth memory cells MC 9 to MC 12 ) includes a second control gate CG 2 A (control gates CG 2 - 1 to CG 2 - 4 ).
- the third drain side select transistor SDT 3 is provided on one end side of the third memory cell group MCG 3 .
- the third drain side select transistor SDT 3 includes the same third semiconductor layer SEM 3 as the third memory cell group MCG 3 . That is, the third drain side select transistor SDT 3 includes a channel formed in the third semiconductor layer SEM 3 .
- the third drain side select transistor SDT 3 includes a second select gate SG 21 . In the following description, a second drain side select gate SGD 2 is illustratively used as the second select gate SG 21 .
- the second drain side select gate SGD 2 is electrically isolated from the first drain side select gate SGD 1 .
- the third source side select transistor SST 3 includes the third semiconductor layer SEM 3 .
- the third source side select transistor SST 3 includes a second other select gate SG 22 .
- a second source side select gate SGS 2 is illustratively used as the second other select gate SG 22 .
- the control unit CTU further performs the following operation in the selective erase operation.
- the second control gates CG 2 A control gates CG 2 - 1 to CG 2 - 4 ) of the third memory transistors MC 3 A are subjected to the third voltage V 3 (medium voltage Vm) or a sixth voltage V 6 lower than the third voltage V 3 .
- the sixth voltage V 6 can be equal to the second voltage V 2 , such as 0 V.
- the second drain side select gate SGD 2 of the third drain side select transistor SDT 3 is subjected to a seventh voltage V 7 lower than the third voltage V 3 .
- the seventh voltage V 7 can be equal to the second voltage V 2 , such as 0 V.
- the memory unit MU further includes a fourth memory string MCS 4 .
- the fourth memory cell group MCG 4 includes a plurality of fourth memory transistors MC 4 A (which are memory cells MC, such as thirteenth to sixteenth memory cells MC 13 to MC 16 ) connected in series. Each of the plurality of fourth memory transistors MC 4 A allows its data to be electrically rewritten.
- the plurality of fourth memory transistors MC 4 A (thirteenth to sixteenth memory cells MC 13 to MC 16 ) include a fourth semiconductor layer SEM 4 .
- the fourth semiconductor layer SEM 4 is electrically isolated from the first semiconductor layer SEM 1 , the second semiconductor layer SEM 2 , and the third semiconductor layer SEM 3 .
- Each of the plurality of fourth memory transistors MC 4 A includes a channel formed in the fourth semiconductor layer SEM 4 .
- the respective control gates of the plurality of fourth memory transistors MC 4 A are commonly connected to the second control gates CG 2 A (control gates CG 2 - 1 to CG 2 - 4 ) of the plurality of third memory transistors MC 3 A (ninth to twelfth memory cells MC 9 to MC 12 ).
- the second bit line BL 2 is connected to the fourth semiconductor layer SEM 4 on the opposite side of the fourth drain side select transistor SDT 4 from the fourth memory cell group MCG 4 (thirteenth to sixteenth memory cells MC 13 to MC 16 ). That is, one end of the second semiconductor layer SEM 2 and one end of the fourth semiconductor layer SEM 4 are commonly connected to the second bit line BL 2 .
- the fourth memory string MCS 4 further includes a fourth other select transistor SGT 42 provided on the opposite side of the fourth memory cell group MCG 4 from the fourth drain side select transistor SDT 4 .
- a fourth source side select transistor SST 4 is illustratively used as the fourth other select transistor SGT 42 .
- the fourth source side select transistor SST 4 includes the fourth semiconductor layer SEM 4 .
- the select gate of the fourth source side select transistor SST 4 is connected to the second source side select gate SGS 2 .
- the second source line SL 2 is connected to the fourth semiconductor layer SEM 4 on the opposite side of the fourth source side select transistor SST 4 from the fourth memory cell group MCG 4 . That is, the second source line SL 2 functions as a source line SL in the fourth memory string MCS 4 , as well as functioning as a source line SL in the second memory string MCS 2 .
- control gates CG 2 - 1 to CG 2 - 4 shared with the third memory string MCS 3 are subjected to the sixth voltage V 6 (e.g., equal to the second voltage V 2 , or 0 V).
- the select gate of the fourth drain side select transistor SDT 4 is subjected to the seventh voltage V 7 (e.g., equal to the second voltage V 2 , or 0 V) in common with the second drain side select gate SGD 2 .
- the second bit line BL 2 and the second source line SL 2 connected to the fourth semiconductor layer SEM 4 of the fourth memory string MCS 4 are subjected to the fifth voltage V 5 (low voltage Vcc) or the second voltage V 2 (0 V) or are set in the floating state OPN.
- the write operation is the operation for performing at least one of injection of electrons into the charge retention layer of the memory cell MC and extraction of holes from the charge retention layer.
- control unit CTU applies a high voltage Vpp (e.g., the aforementioned first voltage V 1 ) to the selected cell gate (CG 1 - 3 ) of the selected cell transistor CL 1 .
- Vpp e.g., the aforementioned first voltage V 1
- the first bit line BL 1 is subjected to 0 V (e.g., the second voltage V 2 lower than the aforementioned first voltage V 1 ).
- the second bit line BL 2 is subjected to a voltage (e.g., low voltage Vcc) higher than the second voltage V 2 and not higher than the third voltage V 3 .
- a voltage e.g., low voltage Vcc
- control unit CTU can further perform the following operation.
- the control unit CTU applies 0 V (e.g., a voltage lower than the aforementioned third voltage V 3 , such as the second voltage V 2 ) to the second control gates CG 2 A (control gates CG 2 - 1 to CG 2 - 4 ) of the third memory transistors MC 3 A (ninth to twelfth memory cells MC 9 to MC 12 ).
- 0 V e.g., a voltage lower than the aforementioned third voltage V 3 , such as the second voltage V 2
- the second source side select gate SGS 2 of the third memory string MCS 3 is subjected to a voltage lower than the third voltage V 3 (e.g., 0 V).
- the select gate of the fourth drain side select transistor SDT 4 is subjected to the same voltage (0 V) as the second drain side select gate SGD 2
- the select gate of the fourth source side select transistor SST 4 is subjected to the same voltage (0 V) as the second source side select gate SGS 2 . This can prevent erroneous writing in the fourth memory transistors MC 4 A (thirteenth to sixteenth memory cells MC 13 to MC 16 ) of the fourth memory string MCS 4 .
- the control unit CTU applies a reading bit line voltage Ve not higher than the fifth voltage V 5 (e.g., low voltage Vcc) and higher than the second voltage V 2 (e.g., 0 V) to the first bit line BL 1 .
- the reading bit line voltage Ve can illustratively be 1 V to 2 V.
- the second bit line BL 2 is subjected to the second voltage V 2 (e.g., 0 V).
- V 2 e.g., 0 V
- the data written in the memory cell MC can be read.
- control unit CTU can further perform the following operation.
- the first source line SL 1 and the second source line SL 2 are subjected to the second voltage V 2 (e.g., 0 V). Furthermore, the first source side select gate SGS 1 of the first memory string MCS 1 is illustratively subjected to the low voltage Vcc.
- control unit CTU illustratively applies 0 V (second voltage V 2 ) to the second control gates CG 2 A (control gates CG 2 - 1 to CG 2 - 4 ) of the third memory transistors MC 3 A (ninth to twelfth memory cells MC 9 to MC 12 ).
- the second source side select gate SGS 2 of the third memory string MCS 3 is also subjected to 0 V.
- the select gate of the fourth drain side select transistor SDT 4 is subjected to 0 V, which is equal to the voltage applied to the second drain side select gate SGD 2
- the select gate of the fourth source side select transistor SST 4 is subjected to 0 V, which is equal to the voltage applied to the second source side select gate SGS 2 .
- This can prevent erroneous writing in the fourth memory transistors MC 4 A (thirteenth to sixteenth memory cells MC 13 to MC 16 ) of the fourth memory string MCS 4 .
- FIGS. 2, 3, and 4 are a schematic perspective view, a schematic cross-sectional view, and a schematic partial cross-sectional view, respectively, illustrating the configuration of the nonvolatile semiconductor memory device according to the first practical example.
- FIG. 2 shows only the conductive portions and omits the insulating portions.
- the nonvolatile semiconductor memory device 110 includes a memory unit MU and a control unit CTU.
- the memory unit MU and the control unit CTU are provided on the major surface 11 a of a substrate 11 illustratively made of single crystal silicon.
- the control unit CTU may be provided on a substrate different from the substrate on which the memory unit MU is provided. In the following description, it is assumed that the memory unit MU and the control unit CTU are provided on the same substrate (substrate 11 ).
- At least part of the control unit CTU can illustratively be provided in at least one of the peripheral region circuit PR 1 and the circuit unit CU described above.
- the memory unit MU includes a matrix memory cell unit MU 1 including a plurality of memory transistors and a wiring connecting unit MU 2 for connecting wirings in the matrix memory cell unit MU 1 .
- FIG. 2 illustrates the configuration of the matrix memory cell unit MU 1 .
- FIG. 3 illustrates part of the A-A′ cross section of FIG. 2 and part of the B-B′ cross section of FIG. 2 .
- a multilayer structure ML is provided on the major surface 11 a of the substrate 11 .
- the multilayer structure ML includes a plurality of electrode films WL and a plurality of interelectrode insulating films 14 alternately stacked in the direction perpendicular to the major surface 11 a.
- the direction perpendicular to the major surface 11 a of the substrate 11 is referred to as a Z-axis direction (first direction). Furthermore, one of the directions in the plane parallel to the major surface 11 a is referred to as a Y-axis direction (second direction). Furthermore, the direction perpendicular to the Z axis and the Y axis is referred to as an X-axis direction (third direction).
- the stacking direction of the electrode films WL and the interelectrode insulating films 14 in the multilayer structure ML is the Z-axis direction. That is, the electrode films WL and the interelectrode insulating films 14 are provided parallel to the major surface 11 a.
- the electrode films WL are illustratively divided into erase blocks.
- FIG. 4 illustrates the configuration of the matrix memory cell unit MU 1 , illustratively corresponding to part of the B-B′ cross section of FIG. 3 .
- the memory unit MU of the nonvolatile semiconductor memory device 110 includes the aforementioned multilayer structure ML, a semiconductor pillar SP (first semiconductor pillar SP 1 ) piercing the multilayer structure ML in the Z-axis direction, a memory layer 48 , an inner insulating film 42 , and an outer insulating film 43 .
- the memory layer 48 is provided between each of the electrode films WL and the semiconductor pillar SP.
- the inner insulating film 42 is provided between the memory layer 48 and the semiconductor pillar SP.
- the outer insulating film 43 is provided between each of the electrode films WL and the memory layer 48 .
- the outer insulating film 43 , the memory layer 48 , and the inner insulating film 42 are formed in this order on the inner wall surface of the through hole TH piercing the multilayer structure ML in the Z-axis direction, and the remaining space is filled with a semiconductor to form the semiconductor pillar SP.
- a memory cell MC is provided at the intersection between the electrode film WL of the multilayer structure ML and the semiconductor pillar SP. That is, memory transistors including the memory layer 48 are provided in a three-dimensional matrix, each at the intersection between the electrode film WL and the semiconductor pillar SP. Each of the memory transistors functions as a memory cell MC for storing data by storing charge in the memory layer 48 .
- the semiconductor pillars SP constitute the first to fourth semiconductor layers SEM 1 to SEM 4 .
- the memory transistors formed in the semiconductor pillars SP constitute the first to fourth memory cell groups MCG 1 to MCG 4 .
- the inner insulating film 42 functions as a tunnel insulating film in the memory transistor of the memory cell MC.
- the outer insulating film 43 functions as a block insulating film in the memory transistor of the memory cell MC.
- the interelectrode insulating film 14 functions as an interlayer insulating film for insulating the electrode films WL from each other.
- the electrode film WL can be made of any conductive material, such as amorphous silicon or polysilicon provided with conductivity by impurity doping, or can be made of metals and alloys. A prescribed electrical signal is applied to the electrode film WL, which functions as a word line of the nonvolatile semiconductor memory device 110 .
- the interelectrode insulating film 14 , the inner insulating film 42 , and the outer insulating film 43 can illustratively be silicon oxide films. It is noted that the interelectrode insulating film 14 , the inner insulating film 42 , and the outer insulating film 43 may be a monolayer film or a multilayer film.
- the memory layer 48 can illustratively be a silicon nitride film and functions as a portion for storing data by storing or releasing charge by an electric field applied between the semiconductor pillar SP and the electrode film WL.
- the memory layer 48 may be a monolayer film or a multilayer film.
- the interelectrode insulating film 14 , the inner insulating film 42 , the memory layer 48 , and the outer insulating film 43 can be made of any material, not limited to the materials illustrated above.
- FIGS. 2 and 3 illustrate the case where the multilayer structure ML includes four electrode films WL
- the number of electrode films WL provided in the multilayer structure ML is arbitrary. In the following description, it is assumed that the number of electrode films WL is four.
- select gates SG are provided above and below the multilayer structure ML.
- an upper select gate USG (illustratively serving as a drain side select gate) is provided above the multilayer structure ML, and a lower select gate LSG (illustratively serving as a source side select gate) is provided below the multilayer structure ML.
- An upper select gate insulating film USGI illustratively made of silicon oxide is provided between the upper select gate USG and the semiconductor pillar SP, and a lower select gate insulating film LSGI illustratively made of silicon oxide is provided between the lower select gate LSG and the semiconductor pillar SP.
- a source line SL is provided below the lower select gate LSG.
- An interlayer insulating film 13 a is provided below the source line SL, and an interlayer insulating film 13 b is provided between the source line SL and the lower select gate LSG.
- the semiconductor pillar SP is connected to the source line SL below the lower select gate LSG and to a bit line BL above the upper select gate USG.
- the upper select gate USG and the lower select gate LSG are divided in the Y-axis direction by an interlayer insulating film 17 and an interlayer insulating film 13 c, respectively, and shaped like strips aligning along the X-axis direction.
- the aforementioned select gates SG can be made of any conductive material, such as polysilicon or amorphous silicon.
- bit line BL connected to the upper portion of the semiconductor pillar SP and the source line SL connected to the lower portion of the semiconductor pillar SP are shaped like strips aligning in the Y-axis direction.
- the electrode film WL is a conductive film shaped like a strip aligning in the X-axis direction.
- One of the upper select gates USG constitutes the first drain side select gate SGD 1
- another of the upper select gates USG constitutes the second drain side select gate SGD 2
- One of the lower select gates LSG constitutes the first source side select gate SGS 1
- another of the lower select gates LSG constitutes the second source side select gate SGS 2 .
- the first drain side select transistor SDT 1 is provided at the intersection between the first semiconductor pillar SP 1 and the first drain side select gate SGD 1 .
- the second drain side select transistor SDT 2 is provided at the intersection between the second semiconductor pillar SP 2 and the first drain side select gate SGD 1 .
- the third drain side select transistor SDT 3 is provided at the intersection between the third semiconductor pillar SP 3 and the second drain side select gate SGD 2 .
- the fourth drain side select transistor SDT 4 is provided at the intersection between the fourth semiconductor pillar SP 4 and the second drain side select gate SGD 2 .
- the first to fourth memory strings MCS 1 to MCS 4 are formed on the basis of the first to fourth semiconductor pillars SP 1 to SP 4 .
- the control unit CTU performs the operation illustrated in FIG. 1B .
- the selective erase operation ER can be performed, and the operational reliability can be improved. Further, it is possible to rewrite data at high speed by selective erasure.
- the desired operation can be performed by the write operation WR and the read operation RD illustrated in FIG. 1B .
- the semiconductor pillars SP are illustratively used as the first to fourth semiconductor layers SEM 1 to SEM 4 , which align in the direction perpendicular to the major surface 11 a of the substrate 11 .
- the first to fourth semiconductor layers SEM 1 to SEM 4 may illustratively be made of a material, such as SOI, aligning in the direction parallel to the major surface 11 a of the substrate 11 .
- FIG. 5 is a schematic diagram illustrating the configuration of a nonvolatile semiconductor memory device according to a second embodiment. More specifically, FIG. 5 is a circuit diagram illustrating the configuration of a nonvolatile semiconductor memory device 102 . In FIG. 5 , for clarity of illustration, some wirings are not shown.
- FIG. 6 is a table illustrating the operation of the nonvolatile semiconductor memory device according to the second embodiment.
- the nonvolatile semiconductor memory device 102 includes a connecting portion transistor CPT (first to fourth connecting portion transistors CPT 1 to CPT 4 ) halfway through each of the memory strings (first to fourth memory strings MCS 1 to MCS 4 ) of the nonvolatile semiconductor memory device 101 illustrated in FIG. 1 .
- Each of the memory strings illustratively has a folded structure.
- the memory unit MU further includes a first source line SL 1 and a second source line SL 2 in addition to the first memory string MCS 1 , the first bit line BL 1 , the second memory string MCS 2 , and the second bit line BL 2 .
- the first memory string MCS 1 further includes a first other memory cell group MCH 1 , a first source side select transistor SST 1 , and a first connecting portion transistor CPT 1 .
- the first source side select transistor SST 1 is provided on the opposite side of the first memory cell group MCG 1 from the first drain side select transistor SDT 1 .
- the first source side select transistor SST 1 includes a channel formed in the first semiconductor layer SEM 1 and includes a first source side select gate SGS 1 .
- the first connecting portion transistor CPT 1 is provided between the first memory cell group MCG 1 and the first source side select transistor SST 1 , includes a channel formed in the first semiconductor layer SEM 1 , and includes a first connecting portion gate CPG 1 .
- a first back gate BG 1 is illustratively used as the first connecting portion gate CPG 1 .
- the first other memory cell group MCH 1 is provided between the first source side select transistor SST 1 and the first connecting portion transistor CPT 1 and includes a plurality of first other memory transistors MC 1 B (memory cells MC) connected in series. As described previously, the first memory cell group MCG 1 includes the first memory transistors MC 1 A (memory cells MC).
- Each of the plurality of first other memory transistors MC 1 B includes a channel formed in the first semiconductor layer SEM 1 , includes a first other control gate CG 1 B (control gates CG 1 / 2 - 5 to CG 1 / 2 - 8 ), and allows its data to be electrically rewritten.
- the first source line SL 1 is connected to the first semiconductor layer SEM 1 on the opposite side of the first source side select transistor SST 1 from the first other memory cell group MCH 1 .
- the first control gates CG 1 A of the first memory cell group MCG 1 are control gates CG 0 / 1 - 1 to CG 0 / 1 - 4 .
- the second memory string MCS 2 further includes a second other memory cell group MCH 2 , a second source side select transistor SST 2 , and a second connecting portion transistor CPT 2 .
- the second source side select transistor SST 2 is provided on the opposite side of the second memory cell group MCG 2 from the second drain side select transistor SDT 2 , includes a channel formed in the second semiconductor layer SEM 2 , and includes a second source side select gate SGS 2 .
- the second connecting portion transistor CPT 2 is provided between the second memory cell group MCG 2 and the second source side select transistor SST 2 , includes a channel formed in the second semiconductor layer SEM 2 , and includes a connecting portion gate electrically connected to the first back gate BG 1 .
- the second other memory cell group MCH 2 is provided between the second source side select transistor SST 2 and the second connecting portion transistor CPT 2 and includes a plurality of second other memory transistors MC 2 B (memory cells MC) connected in series. As described previously, the second memory cell group MCG 2 includes the second memory transistors MC 2 A (memory cells MC).
- Each of the plurality of second other memory transistors MC 2 B includes a channel formed in the second semiconductor layer SEM 2 , includes a control gate (second other control gate) electrically connected to the first other control gate CG 1 B, and allows its data to be electrically rewritten.
- the second source line SL 2 is connected to the second semiconductor layer SEM 2 on the opposite side of the second source side select transistor SST 2 from the second other memory cell group MCH 2 .
- control unit CTU in selective erasure in the nonvolatile semiconductor memory device 102 .
- the control unit CTU performs the following operation.
- this selected cell transistor CL 1 includes the control gate CG 1 - 3 .
- the control unit CTU applies a first voltage V 1 (high voltage Vpp, such as 20 V) to the first bit line BL 1 .
- the selected cell gate (control gate CG 0 / 1 - 3 ) of the selected cell transistor CL 1 is subjected to a second voltage V 2 (e.g., 0 V) lower than the first voltage V 1 .
- the non-selected cell gates (control gate CG 0 / 1 - 1 , control gate CG 0 / 1 - 2 , and control gate CG 0 / 1 - 4 ) of the first memory transistors MC 1 A other than the selected cell transistor CL 1 are subjected to a third voltage V 3 (a medium voltage Vm between the high voltage Vpp and 0 V, such as 10 V) not higher than the first voltage V 1 and higher than the second voltage V 2 .
- a third voltage V 3 a medium voltage Vm between the high voltage Vpp and 0 V, such as 10 V
- the first drain side select gate SGD 1 of the first drain side select transistor SDT 1 is subjected to the first voltage V 1 (high voltage Vpp) or a fourth voltage V 4 (e.g., medium voltage Vm) not higher than the first voltage V 1 and not lower than the third voltage V 3 .
- V 1 high voltage Vpp
- V 4 medium voltage Vm
- the second bit line BL 2 is subjected to a fifth voltage V 5 (e.g., low voltage Vcc) higher than the second voltage V 2 and not higher than the third voltage V 3 .
- V 5 e.g., low voltage Vcc
- the second bit line BL 2 may be subjected to the second voltage V 2 (e.g., 0 V).
- the control unit CTU applies the fifth voltage V 5 (low voltage Vcc) or the second voltage (0 V) to the first source line SL 1 .
- the first other control gate CG 1 B is subjected to the third voltage V 3 (medium voltage Vm).
- the first source side select gate SGS 1 is subjected to an eighth voltage V 8 lower than the third voltage V 3 .
- the eighth voltage V 8 can illustratively be the second voltage (0 V).
- the first back gate BG 1 is subjected to a ninth voltage V 9 lower than the first voltage V 1 (high voltage Vpp) and higher than the second voltage V 2 (0 V).
- the ninth voltage V 9 can illustratively be the medium voltage Vm.
- the second source line SL 2 is subjected to the second voltage V 2 (0 V)
- the second control gates CG 2 A control gates CG 2 / 3 - 1 to CG 2 / 3 - 4
- the sixth voltage V 6 (0 V) or the third voltage V 3 (medium voltage Vm)
- the second drain side select gate SGD 2 is subjected to the eighth voltage V 8
- the second source side select gate SGS 2 is subjected to the eighth voltage V 8 .
- the control gate of the non-selected memory cells is subjected to the medium voltage Vm (e.g., 10 V), and hence the applied electric field is low. Thus, the non-selected memory cells are not erased.
- Vm medium voltage
- the select gate SG (second drain side select gate SGD 2 and second source side select gate SGS 2 ) is subjected to the eighth voltage V 8 , or 0 V, thereby cut off. Thus, no erasure occurs.
- control gates CG 1 / 2 - 5 to CG 1 / 2 - 8 of the first other control gate CG 1 B) shared with the first other memory cell group MCH 1 of the selected memory string (first memory string MCS 1 ) are subjected to the medium voltage Vm (e.g., 10V), and hence the applied electric field is low.
- Vm medium voltage
- no erroneous writing occurs in the memory cells MC (memory cells included in the second other memory cell group MCH 2 ) associated with the control gates.
- the third memory string MCS 3 further includes a third other memory cell group MCH 3 , a third source side select transistor SST 3 , and a third connecting portion transistor CPT 3 .
- the fourth memory string MCS 4 further includes a fourth other memory cell group MCH 4 , a fourth source side select transistor SST 4 , and a fourth connecting portion transistor CPT 4 .
- the configuration of the third and fourth other memory cell groups MCH 3 and MCH 4 and the third and fourth source side select transistors SST 3 and SST 4 is the same as in the first and second memory strings MCS 1 and MCS 2 , and hence the description thereof is omitted.
- the control gates of the third and fourth memory cell groups MCG 3 and MCG 4 are connected to the first and second control gates CG 1 A and CG 2 A of the first and second memory cell groups MCG 1 and MCG 2 , respectively.
- control gates of the third and fourth other memory cell groups MCH 3 and MCH 4 are connected to the first other control gate CG 1 B of the first and second other memory cell groups MCH 1 and MCH 2 .
- control gates of the third and fourth drain side select transistors SDT 3 and SDT 4 are connected to the first and second drain side select gates SGD 1 and SGD 2 of the first and second drain side select transistors SDT 1 and SDT 2 , respectively.
- control gates of the third and fourth source side select transistors SST 3 and SST 4 are connected to the first and second source side select gates SGS 1 and SGS 2 of the first and second source side select transistors SST 1 and SST 2 , respectively.
- the third connecting portion transistor CPT 3 is provided between the third memory cell group MCG 3 and the third source side select transistor SST 3 , includes a channel formed in the third semiconductor layer SEM 3 , and includes a second connecting portion gate CPG 2 .
- a second back gate BG 2 is illustratively used as the second connecting portion gate CPG 2 .
- the fourth connecting portion transistor CPT 4 is provided between the fourth memory cell group MCG 4 and the fourth source side select transistor SST 4 , includes a channel formed in the fourth semiconductor layer SEM 4 , and includes a select gate connected to the second connecting portion gate CPG 2 .
- the control unit CTU in the selective erase operation ER in a selected cell transistor CL 1 of the first memory transistors MC 1 A (memory cells MC belonging to the first memory cell group MCG 1 ), the control unit CTU further applies the second voltage (0 V) to the second back gate BG 2 .
- control unit CTU performs the following operation.
- the control unit CTU applies the second voltage V 2 (0 V) to the first bit line BL 1 . Furthermore, the selected cell gate (control gate CG 0 / 1 - 3 ) of the selected cell transistor CL 1 is subjected to the first voltage V 1 (high voltage Vpp).
- the non-selected cell gates (control gate CG 0 / 1 - 1 , control gate CG 0 / 1 - 2 , and control gate CG 0 / 1 - 4 ) of the first memory transistors MC 1 A other than the selected cell transistor CL 1 are subjected to the fifth voltage V 5 (e.g., low voltage Vcc).
- V 5 e.g., low voltage Vcc
- the first drain side select gate SGD 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second bit line BL 2 is subjected to the fifth voltage V 5 (low voltage Vcc).
- control unit CTU applies the fifth voltage V 5 (low voltage Vcc) or the second voltage V 2 (0 V) to the first source line SL 1 or sets the first source line SL 1 in the floating state OPN.
- the first other control gate CG 1 B is subjected to the fifth voltage V 5 (low voltage Vcc).
- the first source side select gate SGS 1 is subjected to the second voltage V 2 (0 V).
- the first back gate BG 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second source line SL 2 is subjected to the second voltage V 2 (0 V).
- the second control gates CG 2 A (control gate CG 2 / 3 - 1 to control gate CG 2 / 3 - 4 ) are subjected to the second voltage V 2 (0 V) or the fifth voltage (low voltage Vcc).
- the second drain side select gate SGD 2 is subjected to the second voltage V 2 (0 V).
- the second source side select gate SGS 2 is subjected to the second voltage V 2 (0 V).
- the second back gate BG 2 is subjected to the second voltage (0 V).
- the desired select transistor in this case, the selected cell transistor CL 1 belonging to the first memory transistors MC 1 A
- the desired select transistor in this case, the selected cell transistor CL 1 belonging to the first memory transistors MC 1 A
- control unit CTU performs the following operation.
- the control unit CTU applies a reading bit line voltage Ve lower than the fifth voltage V 5 (e.g., low voltage Vcc) and higher than the second voltage V 2 (e.g., 0 V) to the first bit line BL 1 .
- the reading bit line voltage Ve can illustratively be 1 V to 2 V.
- the selected cell gate (control gate CG 0 / 1 - 3 ) of the selected cell transistor CL 1 is subjected to the sense voltage Vse.
- the non-selected cell gates (control gate CG 0 / 1 - 1 , control gate CG 0 / 1 - 2 , and control gate CG 0 / 1 - 4 ) of the first memory transistors MC 1 A other than the selected cell transistor CL 1 are subjected to the fifth voltage V 5 (low voltage Vcc).
- the first drain side select gate SGD 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second bit line BL 2 is subjected to the second voltage V 2 (0 V).
- control unit CTU applies the second voltage V 2 (0 V) to the first source line SL 1 .
- the first other control gate CG 1 B is subjected to the fifth voltage V 5 (low voltage Vcc).
- the first source side select gate SGS 1 is subjected to the fifth voltage V 5 (Vcc).
- the first back gate BG 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second source line SL 2 is subjected to the second voltage V 2 (0 V).
- the second control gates CG 2 A (control gate CG 2 / 3 - 1 to control gate CG 2 / 3 - 4 ) are subjected to the second voltage V 2 (0 V).
- the second drain side select gate SGD 2 is subjected to the second voltage V 2 (0 V).
- the second source side select gate SGS 2 is subjected to the second voltage V 2 (0 V).
- the second back gate BG 2 is subjected to the second voltage (0 V).
- the data stored in the desired select transistor (in this case, the selected cell transistor CL 1 belonging to the first memory transistors MC 1 A) can be read.
- the selected memory cells are the selected cell transistors CL 2 , CL 3 , and CL 4 belonging, respectively, to the second, third, and fourth memory strings MCS 2 , MCS 3 , and MCS 4 .
- the voltages under the condition illustrated in FIG. 6 can be used to perform the selective erase operation ER.
- the positions of the first memory cell group MCG 1 , the first other memory cell group MCH 1 , the second memory cell group MCG 2 , the second other memory cell group MCH 2 , the third memory cell group, the third other memory cell group, the fourth memory cell group, the fourth other memory cell group and the like can be regarded to change with the position of the selected memory cell, and the positions of each wiring, each select gate, each control gate, and each connecting portion gate can be changed accordingly to selectively erase the desired memory cell MC by a similar operation.
- write operation WR and the read operation RD can be performed likewise.
- FIG. 7 is a schematic diagram illustrating the configuration of an alternative nonvolatile semiconductor memory device according to the second embodiment.
- FIG. 7 is a circuit diagram illustrating the configuration of a nonvolatile semiconductor memory device 102 a. In FIG. 7 , for clarity of illustration, some wirings are not shown.
- FIG. 8 is a table illustrating the operation of the alternative nonvolatile semiconductor memory device according to the second embodiment.
- the first other control gate CG 1 B and the second other control gate CG 2 B are not common and are independent of each other. The rest is same as the nonvolatile semiconductor memory device 102 .
- each of the plurality of second other memory transistors MC 2 B includes a channel formed in the second semiconductor layer SEM 2 , includes a second other control gate CG 2 B, and allows its data to be electrically rewritten.
- the control unit CTU applies the second voltage (0 V) to the second control gates CG 2 A (control gate CG 2 - 1 to control gate CG 2 - 4 ) and the second other control gates CG 2 B (control gate CG 2 - 5 to control gate CG 2 - 8 ).
- the rest is same as the nonvolatile semiconductor memory device 102 .
- the control unit CTU applies the second voltage V 2 (0 V) or the fifth voltage V 5 (lower voltage Vcc) to the first source line SL 1 or sets the first source line in the floating state OPN.
- the second control gate CG 2 A and the second other control gate CG 2 B are subjected to the second voltage V 2 (0 V).
- the rest is same as the nonvolatile semiconductor memory device 102 .
- control unit CTU applies the second voltage V 2 (0 V) to the second control gate CG 2 A and the second other control gate CG 2 B.
- the rest is same as the nonvolatile semiconductor memory device 102 .
- nonvolatile semiconductor memory device 120 of a second practical example according to the second embodiment is described.
- FIGS. 9 and 10 are a schematic perspective view and a schematic cross-sectional view, respectively, illustrating the configuration of the nonvolatile semiconductor memory device according to the second practical example.
- FIG. 9 shows only the conductive portions and omits the insulating portions.
- the nonvolatile semiconductor memory device 120 As shown in FIGS. 9 and 10 , in the nonvolatile semiconductor memory device 120 according to this embodiment, two of the semiconductor pillars SP described with reference to the first practical example are connected by a connecting portion CP.
- the memory unit MU further includes a second semiconductor pillar SP 2 (semiconductor pillar SP) and a first connecting portion CP 1 (connecting portion CP).
- the second semiconductor pillar SP 2 is adjacent to the first semiconductor pillar SP 1 (semiconductor pillar SP) illustratively in the Y-axis direction and pierces the multilayer structure ML in the Z-axis direction.
- the first connecting portion CP 1 electrically connects the first semiconductor pillar SP 1 and the second semiconductor pillar SP 2 on the same side (substrate 11 side) in the Z-axis direction.
- the first connecting portion CP 1 aligns in the Y-axis direction.
- the first connecting portion CP 1 is made of the same material as the first and second semiconductor pillars SP 1 and SP 2 .
- a back gate BG (connecting portion conductive layer) is provided on the major surface 11 a of the substrate 11 via the interlayer insulating film 13 .
- a trench is provided in portions of the first back gate BG 1 (back gate BG) opposed to the first and second semiconductor pillars SP 1 and SP 2 .
- An outer insulating film 43 , a memory layer 48 , and an inner insulating film 42 are formed inside the trench, and the remaining space is filled with a connecting portion CP made of a semiconductor.
- the formation of the outer insulating film 43 , the memory layer 48 , the inner insulating film 42 , and the connecting portion CP in the trench is performed simultaneously and collectively with the formation of the outer insulating film 43 , the memory layer 48 , the inner insulating film 42 , and the semiconductor pillar SP in the through hole TH.
- the back gate BG is provided opposite to the connecting portion CP.
- the first connecting portion CP 1 and the first back gate BG 1 constitute the first connecting portion transistor CPT 1 illustrated in FIG. 5 .
- the first and second semiconductor pillars SP 1 and SP 2 and the connecting portion CP constitute a U-shaped semiconductor pillar, which serves as a U-shaped memory string.
- the electrode film WL between the first and second semiconductor pillars SP 1 and SP 2 is divided by an insulating layer IL.
- the end of the first semiconductor pillar SP 1 opposite to the first connecting portion CP 1 is connected to a bit line BL (first bit line BL 1 ), and the end of the second semiconductor pillar SP 2 opposite to the first connecting portion CP 1 is connected to a source line SL (first source line SL 1 ).
- the semiconductor pillar SP is connected to the bit line BL by a via VA 1 and a via VA 2 .
- bit line BL aligns in the Y-axis direction
- source line SL aligns in the X-axis direction
- a first drain side select gate SGD 1 is provided opposite to the first semiconductor pillar SP 1
- a first source side select gate SGS 1 is provided opposite to the second semiconductor pillar SP 2 .
- a third semiconductor pillar SP 3 a fourth semiconductor pillar SP 4 , and a second connecting portion CP 2 (connecting portion CP) are provided.
- the third semiconductor pillar SP 3 is adjacent to the second semiconductor pillar SP 2 on the opposite side of the second semiconductor pillar SP 2 from the first semiconductor pillar SP 1 in the Y-axis direction and pierces the multilayer structure ML in the Z-axis direction.
- the fourth semiconductor pillar SP 4 is adjacent to the third semiconductor pillar SP 3 on the opposite side of the third semiconductor pillar SP 3 from the second semiconductor pillar SP 2 in the Y-axis direction and pierces the multilayer structure ML in the Z-axis direction.
- the second connecting portion CP 2 electrically connects the third semiconductor pillar SP 3 and the fourth semiconductor pillar SP 4 on the same side in the Z-axis direction (on the same side as the first connecting portion CP 1 ).
- the second connecting portion CP 2 aligns in the Y-axis direction and is opposed to the first back gate BG 1 .
- the memory layer 48 is provided also between each of the electrode films WL and the third and fourth semiconductor pillars SP 3 and SP 4 and between the back gate BG and the second connecting portion CP 2 .
- the inner insulating film 42 is provided also between the third and fourth semiconductor pillars SP 3 and SP 4 and the memory layer 48 and between the memory layer 48 and the second connecting portion CP 2 .
- the outer insulating film 43 is provided also between each of the electrode films WL and the memory layer 48 and between the memory layer 48 and the back gate BG.
- the source line SL is connected to the third end portion on the opposite side of the third semiconductor pillar SP 3 from the second connecting portion CP 2 .
- the bit line BL is connected to the fourth end portion on the opposite side of the fourth semiconductor pillar SP 4 from the second connecting portion CP 2 .
- a second source side select gate SGS 2 is provided opposite to the third semiconductor pillar SP 3
- a second drain side select gate SGD 2 is provided opposite to the fourth semiconductor pillar SP 4 .
- the select gates SG can be made of any conductive material, such as polysilicon or amorphous silicon.
- the select gates SG are divided in the Y-axis direction and shaped like strips aligning along the X-axis direction.
- the wording “semiconductor pillar SP” is used.
- the wording “n-th semiconductor pillar SPn” (n is any integer of one or more) is used.
- the wording “n-th connecting portion CPn” is used.
- the first and second semiconductor pillars SP 1 and SP 2 and the first connecting portion CP 1 correspond to the first semiconductor layer SEM 1
- the third and fourth semiconductor pillars SP 3 and SP 4 and the second connecting portion CP 2 correspond to the second semiconductor layer SEM 2 .
- fifth to eighth semiconductor pillars SP 5 to SP 8 and third and fourth connecting portions CP 3 and CP 4 are provided adjacent in the X-axis direction to the first to fourth semiconductor pillars SP 1 -SP 4 and the first and second connecting portions CP 1 and CP 2 .
- the fifth and sixth semiconductor pillars SP 5 and SP 6 and the third connecting portion CP 3 correspond to the third semiconductor layer SEM 3
- the seventh and eighth semiconductor pillars SP 7 and SP 8 and the fourth connecting portion CP 4 correspond to the fourth semiconductor layer SEM 4 .
- the third and fourth connecting portions CP 3 and CP 4 align in the Y-axis direction and is opposed to the second back gate BG 2 , which aligns parallel to the first back gate BG 1 .
- an interlayer insulating film 15 is provided at the top (on the side farthest from the substrate 11 ) of the multilayer structure ML. Furthermore, an interlayer insulating film 16 is provided on the multilayer structure ML, a select gate SG is provided thereon, and an interlayer insulating film 17 is provided between the select gates SG.
- a through hole TH is provided in the select gate SG, a select gate insulating film SG 1 of a select transistor is provided on the inner side surface thereof, and a semiconductor is filled inside it. This semiconductor is included in the semiconductor pillar SP.
- an interlayer insulating film 18 is provided on the interlayer insulating film 17 .
- a source line SL and vias 22 are provided thereon, and an interlayer insulating film 19 is provided around the source line SL.
- an interlayer insulating film 23 is provided on the source line SL, and a bit line BL is provided thereon.
- the bit line BL is shaped like a strip along the Y axis.
- the interlayer insulating films 15 , 16 , 17 , 18 , 19 , and 23 and the select gate insulating film SG 1 can illustratively be made of silicon oxide.
- one electrode film WL is connected to a word line 32 by a via plug 31 and electrically connected to, for instance, a driving circuit provided in the substrate 11 .
- another electrode film WL is connected to the word line by the via plug and electrically connected to the driving circuit.
- the length in the X-axis direction of each of the electrode films WL stacked in the Z-axis direction is varied stepwise, so that electrical connection to the driving circuit is implemented by the one electrode film WL at one end in the X-axis direction and by the other electrode film WL at the other end in the X-axis direction.
- the control unit CTU performs the operation illustrated in FIG. 6 .
- the selective erase operation ER can be performed, and the operational reliability of the device can be improved. Further, it is possible to rewrite data at high speed by selective erasure.
- the desired operation can be performed by the write operation WR and the read operation RD illustrated in FIG. 6 .
- FIG. 11 is a schematic diagram illustrating the configuration of a nonvolatile semiconductor memory device according to a third embodiment.
- FIG. 11 is a circuit diagram illustrating the configuration of a nonvolatile semiconductor memory device 103 .
- FIG. 11 for clarity of illustration, some wirings are not shown.
- FIG. 12 is a table illustrating the operation of the nonvolatile semiconductor memory device according to the third embodiment.
- the semiconductor layer of the memory string includes a base semiconductor layer.
- Each of the memory strings has a folded structure.
- the nonvolatile semiconductor memory device 103 includes a memory unit MU and a control unit CTU.
- the memory unit MU includes a first memory string MCS 1 , a first wiring W 11 , a first other wiring W 12 , and a first base wiring SB 1 .
- a first bit line BL 1 is used as the first wiring W 11
- a first source line SL 1 is used as the first other wiring W 12 .
- the first base wiring SB 1 is one of a plurality of base wirings SB provided in the device.
- the first memory string MCS 1 includes a first memory cell group MCG 1 , a first other memory cell group MCH 1 , a first select transistor SGT 11 , a first other select transistor SGT 12 , and a first connecting portion transistor CPT 1 .
- a first drain side select transistor SDT 1 is used as the first select transistor SGT 11
- a first source side select transistor SST 1 is used as the first other select transistor SGT 12 .
- the first memory cell group MCG 1 includes a plurality of first memory transistors MC 1 A connected in series. Each of the plurality of first memory transistors MC 1 A includes a channel formed in a first semiconductor layer SEM 1 provided in contact with a first base semiconductor layer BSEM 1 . Each of the plurality of first memory transistors MC 1 A includes a first control gate CG 1 A and allows its data to be electrically rewritten.
- the first drain side select transistor SDT 1 is provided on one end side of the first memory cell group MCG 1 , includes a channel formed in the first semiconductor layer SEM 1 , and includes a first select gate SG 11 .
- a first drain side select gate SGD 1 is illustratively used as the first select gate SG 11 .
- the first source side select transistor SST 1 is provided on the opposite side of the first memory cell group MCG 1 from the first drain side select transistor SDT 1 , includes a channel formed in the first semiconductor layer SEM 1 , and includes a first other select gate SG 12 .
- a first source side select gate SGS 1 is illustratively used as the first other select gate SG 12 .
- the first connecting portion transistor CPT 1 is provided between the first memory cell group MCG 1 and the first source side select transistor SST 1 , includes a channel formed in the first semiconductor layer SEM 1 , and includes a first connecting portion gate CPG 1 .
- a first back gate BG 1 is illustratively used as the first connecting portion gate CPG 1 .
- the first other memory cell group MCH 1 is provided between the first source side select transistor SST 1 and the first connecting portion transistor CPT 1 and includes a plurality of first other memory transistors MC 1 B connected in series.
- Each of the plurality of first other memory transistors MC 1 B includes a channel formed in the first semiconductor layer SEM 1 , includes a first other control gate CG 1 B, and allows its data to be electrically rewritten.
- the first bit line BL 1 is connected to the first semiconductor layer SEM 1 on the opposite side of the first drain side select transistor SDT 1 from the first memory cell group MCG 1 .
- the first source line SL 1 is connected to the first semiconductor layer SEM 1 on the opposite side of the first source side select transistor SST 1 from the first other memory cell group MCH 1 .
- the first base wiring SB 1 is connected to the first base semiconductor layer BSEM 1 .
- bit line and the source line are arranged parallel to each other and cross (e.g., orthogonally) the select gate, the control gate, and the back gate.
- the control unit CTU performs the following operation.
- this selected cell transistor CL 1 includes the control gate CG 1 - 3 .
- the control unit CTU applies a first voltage V 1 (e.g., high voltage Vpp, such as 20 V) to the first bit line BL 1 and the first source line SL 1 .
- V 1 e.g., high voltage Vpp, such as 20 V
- the control unit CTU sets the first bit line BL 1 and the first source line SL 1 in the floating state OPN.
- the selected cell gate CG 1 - 3 of the selected cell transistor CL 1 is subjected to a second voltage V 2 (e.g., 0 V) lower than the first voltage V 1 .
- the non-selected cell gates (control gate CG 1 - 1 , control gate CG 1 - 2 , and control gate CG 1 - 4 ) of the first memory transistors MC 1 A other than the selected cell transistor CL 1 are subjected to a third voltage V 3 (e.g., medium voltage Vm, such as 10 V) lower than the first voltage V 1 and higher than the second voltage V 2 .
- a third voltage V 3 e.g., medium voltage Vm, such as 10 V
- the first other control gates CG 1 B (control gate CG 1 - 5 to control gate CG 1 - 8 ) are subjected to the third voltage V 3 (e.g., medium voltage Vm).
- V 3 e.g., medium voltage Vm
- the first drain side select gate SGD 1 and the first source side select gate SGS 1 are subjected to a tenth voltage V 10 lower than the first voltage V 1 and higher than the second voltage V 2 .
- the medium voltage Vm e.g., 10 V
- the medium voltage Vm is illustratively used as the tenth voltage V 10 .
- the first back gate BG 1 is subjected to an eleventh voltage V 11 lower than the first voltage V 1 and higher than the second voltage V 2 .
- the medium voltage Vm can be used as the eleventh voltage V 11 .
- the first base wiring SB 1 is subjected to the first voltage V 1 (e.g., high voltage Vpp, such as 20 V).
- V 1 e.g., high voltage Vpp, such as 20 V.
- the control gates are subjected to the medium voltage Vm (e.g., 10 V), and hence the applied electric field is low. Thus, the non-selected memory cells are not erased.
- Vm medium voltage
- the memory unit MU can further include a second memory string MCS 2 .
- the second memory string MCS 2 includes a second memory cell group MCG 2 , a second other memory cell group MCH 2 , a second select transistor SGT 21 , a second other select transistor SGT 22 , and a second connecting portion transistor CPT 2 .
- a second drain side select transistor SDT 2 is used as the second select transistor SGT 21
- a second source side select transistor SST 2 is used as the second other select transistor SGT 22 .
- the second drain side select transistor SDT 2 is provided on one end side of the second memory cell group MCG 2 , includes a channel formed in the second semiconductor layer SEM 2 , and includes a second select gate SG 21 .
- a second drain side select gate SGD 2 is illustratively used as the second select gate SG 21 .
- the second source side select transistor SST 2 is provided on the opposite side of the second memory cell group MCG 2 from the second drain side select transistor SDT 2 , includes a channel formed in the second semiconductor layer SEM 2 , and includes a second other select gate SG 22 .
- a second source side select gate SGS 2 is illustratively used as the second other select gate SG 22 .
- the second connecting portion transistor CPT 2 is provided between the second memory cell group MCG 2 and the second source side select transistor SST 2 , includes a channel formed in the second semiconductor layer SEM 2 , and includes a second connecting portion gate CPG 2 .
- a second back gate BG 2 is illustratively used as the second connecting portion gate CPG 2 .
- the control unit CTU applies the third voltage V 3 (medium voltage Vm) to the second control gates CG 2 A (control gate CG 2 - 1 to control gate CG 2 - 4 ) and the second other control gates CG 2 B (control gate CG 2 - 5 to control gate CG 2 - 8 ).
- the non-selected memory cells of the second memory transistors MC 2 A and the second other memory transistors MC 2 B belonging to the second memory string MCS 2 are not erased.
- the memory unit MU can further include a third memory string MCS 3 , a second wiring W 21 , a second other wiring W 22 , and a second base wiring SB 2 .
- a second bit line BL 2 is used as the second wiring W 21
- a second source line SL 2 is used as the second other wiring W 22 .
- the second base wiring SB 2 is one of the plurality of base wirings SB provided in the device.
- the third drain side select transistor SDT 3 is provided on one end side of the third memory cell group MCG 3 , includes a channel formed in the third semiconductor layer SEM 3 , and is connected to the first select gate SG 11 .
- the third other memory cell group MCH 3 is provided between the third source side select transistor SST 3 and the third connecting portion transistor CPT 3 and includes a plurality of third other memory transistors MC 3 B connected in series.
- the second source line SL 2 is connected to the third semiconductor layer SEM 3 on the opposite side of the third source side select transistor SST 3 from the third other memory cell group MCH 3 .
- the second base wiring SB 2 is connected to the third base semiconductor layer BSEM 3 .
- the control unit CTU further applies a twelfth voltage V 12 lower than the first voltage V 1 and higher than the second voltage V 2 to the second bit line BL 2 and the second source line SL 2 .
- the control unit CTU sets the second bit line BL 2 and the second source line SL 2 in the floating state OPN.
- the medium voltage Vm e.g., 10V
- the second base wiring SB 2 is subjected to a thirteenth voltage V 13 lower than the first voltage V 1 and higher than the second voltage V 2 .
- the medium voltage Vm e.g., 10 V
- the second base wiring SB 2 may be set in the floating state OPN.
- the second bit line BL 2 and the second source line SL 2 are subjected to the medium voltage Vm (10 V) or set in the floating state OPN, and hence no electric field is applied thereto.
- Vm 10 V
- the memory unit MU can further include a fourth memory string MCS 4 .
- the fourth memory string MCS 4 includes a fourth memory cell group MCG 4 , a fourth other memory cell group MCH 4 , a fourth select transistor SGT 41 , a fourth other select transistor SGT 42 , and a fourth connecting portion transistor CPT 4 .
- a fourth drain side select transistor SDT 4 is used as the fourth select transistor SGT 41
- a fourth source side select transistor SST 4 is used as the fourth other select transistor SGT 42 .
- the fourth memory cell group MCG 4 includes a plurality of fourth memory transistors MC 4 A connected in series.
- Each of the plurality of fourth memory transistors MC 4 A includes a channel formed in a fourth semiconductor layer SEM 4 provided in contact with a fourth base semiconductor layer BSEM 4 and electrically isolated from the first semiconductor layer SEM 1 , the second semiconductor layer SEM 2 , and the third semiconductor layer SEM 3 , is connected to the second control gate CG 2 A, and allows its data to be electrically rewritten.
- the fourth drain side select transistor SDT 4 is provided on one end side of the fourth memory cell group MCG 4 , includes a channel formed in the fourth semiconductor layer SEM 4 , and is connected to the second select gate SG 21 .
- the fourth source side select transistor SST 4 is provided on the opposite side of the fourth memory cell group MCG 4 from the fourth drain side select transistor SDT 4 , includes a channel formed in the fourth semiconductor layer SEM 4 , and is connected to the second other select gate SG 22 .
- the fourth connecting portion transistor CPT 4 is provided between the fourth memory cell group MCG 4 and the fourth source side select transistor SST 4 , includes a channel formed in the fourth semiconductor layer SEM 4 , and is connected to the second connecting portion gate CPG 2 .
- the fourth other memory cell group MCH 4 is provided between the fourth source side select transistor SST 4 and the fourth connecting portion transistor CPT 4 and includes a plurality of fourth other memory transistors MC 4 B connected in series.
- Each of the plurality of fourth other memory transistors MC 4 B includes a channel formed in the fourth semiconductor layer SEM 4 , is connected to the second other control gate CG 2 B, and allows its data to be electrically rewritten.
- the second bit line BL 2 is further connected to the fourth semiconductor layer SEM 4 on the opposite side of the fourth drain side select transistor SDT 4 from the fourth memory cell group MCG 4 .
- the second source line SL 2 is further connected to the fourth semiconductor layer SEM 4 on the opposite side of the fourth source side select transistor SST 4 from the fourth other memory cell group MCH 4 .
- the second base wiring SB 2 is further connected to the fourth base semiconductor layer BSEM 4 .
- each memory cell MC of the fourth memory string MCS 4 thus configured, like the second memory string MCS 2 and the third memory string MCS 3 , no erasure occurs.
- control unit CTU performs the following operation.
- the control unit CTU applies the second voltage V 2 (0 V) to the first bit line BL 1 . Furthermore, the selected cell gate (control gate CG 1 - 3 ) of the selected cell transistor CL 1 is subjected to the first voltage V 1 (high voltage Vpp).
- control gate CG 1 - 1 , control gate CG 1 - 2 , and control gate CG 1 - 4 are subjected to the fifth voltage V 5 (low voltage Vcc).
- the first drain side select gate SGD 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second bit line BL 2 is subjected to the fifth voltage V 5 (low voltage Vcc). Alternatively, the second bit line BL 2 is set in the floating state OPN.
- the first base wiring SB 1 is subjected to the second voltage V 2 (0 V).
- control unit CTU applies the second voltage V 2 (0 V) or the fifth voltage V 5 (low voltage Vcc) to the first source line SL 1 or sets the first source line SL 1 in the floating state OPN.
- the first other control gates CG 1 B (control gate CG 1 - 5 to control gate CG 1 - 8 ) are subjected to the fifth voltage V 5 (low voltage Vcc).
- the first source side select gate SGS 1 is subjected to the second voltage V 2 (0 V).
- the first back gate BG 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second source line SL 2 is subjected to the second voltage V 2 (0 V) or the fifth voltage V 5 (low voltage Vcc), or the second source line SL 2 is set in the floating state OPN.
- the second control gates CG 2 A (control gate CG 2 - 1 to control gate CG 2 - 4 ) and the second other control gates CG 2 B (control gate CG 2 - 5 to control gate CG 2 - 8 ) are subjected to the second voltage V 2 (0 V) or the low voltage Vcc.
- the second drain side select gate SGD 2 and the second back gate BG 2 are subjected to the second voltage V 2 (0 V) or the low voltage Vcc, or the second drain side select gate SGD 2 and the second back gate BG 2 are set in the floating state OPN.
- the second control gate CG 2 A and the second other control gate CG 2 B, and the second drain side select gate SGD 2 and the second back gate BG 2 may be subjected to 0 V also in the case where the second voltage V 2 is not 0 V.
- the second source side select gate SGS 2 is subjected to the second voltage V 2 (0 V) or the fifth voltage (low voltage Vcc), or the second source side select gate SGS 2 is set in the floating state OPN.
- the second base wiring SB 2 is subjected to the low voltage Vcc.
- the second base wiring SB 2 is set in the floating state OPN.
- the second base wiring SB 2 may be subjected to 0 V.
- the desired select transistor in this case, the selected cell transistor CL 1 belonging to the first memory transistors MC 1 A
- the desired select transistor in this case, the selected cell transistor CL 1 belonging to the first memory transistors MC 1 A
- a high electric field is applied between the charge retention layer of the selected cell transistor CL 1 and the first base semiconductor layer BSEM 1 .
- electrons are injected into the charge retention layer, or holes are released into the first base semiconductor layer BSEM 1 .
- the threshold voltage of the selected cell transistor CL 1 exceeds 0V.
- the applied electric field is low, and hence no writing occurs.
- writing is prevented in the memory cells MC included in the memory string adjacent to the memory string commonly connected to the first control gate CG 1 A and the first other control gates CG 1 B (control gate CG 1 - 1 to control gate CG 1 - 8 ), the first drain side select gate SGD 1 , the first source side select gate SGS 1 , and the first back gate BG 1 and including the selected cell transistor CL because the second bit line BL 2 is subjected to the low voltage Vcc (e.g., 3 V) or set in the floating state OPN and the second source line SL 2 is subjected to the second voltage V 2 (0 V) or the fifth voltage (low voltage Vcc), or the second source side select gate SGS 2 is set in the floating state OPN.
- Vcc low voltage
- control unit CTU performs the following operation.
- the control unit CTU applies a reading bit line voltage Ve not higher than the fifth voltage V 5 (e.g., low voltage Vcc) and higher than the second voltage V 2 (e.g., 0 V) to the first bit line BL 1 .
- the reading bit line voltage Ve can illustratively be 1 V to 2 V.
- the selected cell gate (control gate CG 1 - 3 ) of the selected cell transistor CL 1 is subjected to the sense voltage Vse.
- control gate CG 1 - 1 , control gate CG 1 - 2 , and control gate CG 1 - 4 are subjected to the fifth voltage V 5 (low voltage Vcc).
- the first drain side select gate SGD 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second bit line BL 2 is subjected to the second voltage V 2 (0 V).
- the first base wiring SB 1 is subjected to the second voltage V 2 (0 V).
- control unit CTU applies the second voltage V 2 (0 V) to the first source line SL 1 .
- the first other control gates CG 1 B (control gate CG 1 - 5 to control gate CG 1 - 8 ) are subjected to the fifth voltage V 5 (low voltage Vcc).
- the first source side select gate SGS 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the first back gate BG 1 is subjected to the fifth voltage V 5 (low voltage Vcc).
- the second source line SL 2 is subjected to the second voltage V 2 (0 V).
- the second control gates CG 2 A (control gate CG 2 - 1 to control gate CG 2 - 4 ) and the second other control gates CG 2 B (control gate CG 2 - 5 to control gate CG 2 - 8 ) are subjected to the second voltage V 2 (0 V).
- the second drain side select gate SGD 2 is subjected to the second voltage V 2 (0 V).
- the second source side select gate SGS 2 is subjected to the second voltage V 2 (0 V).
- the second back gate BG 2 is subjected to the second voltage V 2 (0 V).
- the second base wiring SB 2 is subjected to the second voltage V 2 (0 V).
- the data stored in the desired select transistor (in this case, the selected cell transistor CL 1 belonging to the first memory transistors MC 1 A) can be read.
- the selected memory cells are the selected cell transistors CL 2 , CL 3 , and CL 4 belonging, respectively, to the second, third, and fourth memory string, MCS 2 , MCS 3 , and MCS 4 .
- the voltages under the condition illustrated in FIG. 12 can be used to perform the selective erase operation ER.
- write operation WR and the read operation RD can be performed likewise.
- the base semiconductor layer is not isolated for each memory cell group, but is shared by the adjacent memory cell groups like each bit line BL and each source line SL.
- selective erasure can be performed by applying the second voltage V 2 (0 V) to the select gate SG, control gate CG, and back gate BG of the memory cell groups sharing the bit line BL and the source line SL. This has the advantage of reducing the number of terminals to be energized.
- FIG. 13 is a schematic diagram illustrating the configuration of an alternative nonvolatile semiconductor memory device according to the third embodiment.
- FIG. 13 is a circuit diagram illustrating the configuration of a nonvolatile semiconductor memory device 103 a. In FIG. 13 , for clarity of illustration, some wirings are not shown.
- FIG. 14 is a table illustrating the operation of the alternative nonvolatile semiconductor memory device according to the third embodiment.
- the first other control gate CG 1 B of the first other memory transistor MC 1 B is electrically connected to the control gate of the second other memory transistor MC 2 B.
- the rest is same as the nonvolatile semiconductor memory device 103 .
- each of the plurality of second other memory transistors MC 2 B includes a channel formed in the second semiconductor layer SEM 2 , includes the control gate (second other control gate) electrically connected to the first other control gate CG 1 B, and allows its data to be electrically rewritten.
- the control unit CTU implements the same operations as the nonvolatile semiconductor memory device 103 .
- nonvolatile semiconductor memory device 130 of a third practical example according to the third embodiment is described.
- FIG. 15 is a schematic perspective view illustrating the configuration of the nonvolatile semiconductor memory device according to the third practical example.
- FIG. 15 illustrates the configuration of the first and third memory strings MCS 1 and MCS 3 .
- the central portion of the semiconductor layer SEML away from the electrode film WL serves as a base semiconductor layer (first base semiconductor layer BSEM 1 ).
- a p + -region P 01 for instance, having a higher impurity concentration than the first base semiconductor layer BSEM 1 is provided in an upper portion of the first base semiconductor layer BSEM 1 and serves as a contact portion of the first base wiring SB 1 in the first base semiconductor layer BSEM 1 .
- a first drain side select transistor SDT 1 is provided on one wall surface side of the trench TR, and a first source side select transistor SST 1 is provided on the other wall surface side of the trench TR. That is, the select gate SG on one wall surface side of the trench TR serves as a first drain side select gate SGD 1 , and the select gate SG on the other wall surface side of the trench TR serves as a first source side select gate SGS 1 .
- the stacking direction of the multilayer structure ML is the Z-axis direction
- the direction in which the wall surfaces of the trench TR are opposed to each other is the Y-axis direction.
- the direction perpendicular to the Z-axis direction and the Y-axis direction is the X-axis direction.
- n + -region P 02 illustratively having a higher impurity concentration than the first base semiconductor layer BSEM 1 is provided in an upper portion of the first semiconductor layer SEM 1 .
- the n + -region P 02 on one wall surface side of the trench TR constitutes a drain side contact DC 01
- the n + -region P 02 on the other wall surface side of the trench TR constitutes a source side contact SC 01 .
- a third memory string MCS 3 having the same configuration as the first memory string MCS 1 is provided adjacent to the first memory string MCS 1 in the X-axis direction.
- the interelectrode insulating film 14 , the inner insulating film 42 , and the outer insulating film 43 can be a monolayer film made of a material selected from a group including silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate, or a multilayer film made of a plurality of materials selected from the group.
- the memory layer 48 can be a monolayer film made of a material selected from a group including silicon nitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnia, hafnium aluminate, hafnia nitride, hafnium nitride aluminate, hafnium silicate, hafnium nitride silicate, lanthanum oxide, and lanthanum aluminate, or a multilayer film made of a plurality of materials selected from the group.
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Abstract
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Also Published As
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USRE45972E1 (en) | 2016-04-12 |
USRE46809E1 (en) | 2018-04-24 |
JP5052575B2 (en) | 2012-10-17 |
US8320182B2 (en) | 2012-11-27 |
US20110051527A1 (en) | 2011-03-03 |
JP2011054234A (en) | 2011-03-17 |
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