JP2001274093A - Semiconductor base and its manufacturing method - Google Patents

Semiconductor base and its manufacturing method

Info

Publication number
JP2001274093A
JP2001274093A JP2000083324A JP2000083324A JP2001274093A JP 2001274093 A JP2001274093 A JP 2001274093A JP 2000083324 A JP2000083324 A JP 2000083324A JP 2000083324 A JP2000083324 A JP 2000083324A JP 2001274093 A JP2001274093 A JP 2001274093A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor layer
semiconductor
growth
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000083324A
Other languages
Japanese (ja)
Other versions
JP4665286B2 (en
Inventor
Kazuyuki Tadatomo
一行 只友
Hiroaki Okagawa
広明 岡川
Masahiro Koto
雅弘 湖東
Yoichiro Ouchi
洋一郎 大内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Cable Industries Ltd
Original Assignee
Mitsubishi Cable Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Cable Industries Ltd filed Critical Mitsubishi Cable Industries Ltd
Priority to JP2000083324A priority Critical patent/JP4665286B2/en
Publication of JP2001274093A publication Critical patent/JP2001274093A/en
Application granted granted Critical
Publication of JP4665286B2 publication Critical patent/JP4665286B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor base that has a high-quality epitaxial film where dislocation density is reduced using a mask material such as SiO2 that is used for conventional selective growth, and a growth method. SOLUTION: First, a projection part 11 and a recessed part 12 are provided on the crystal growth surface of a substrate 1. After that, a feed gas for semiconductor crystal growth such as a GaN-family compound semiconductor is supplied to the substrate, and crystal growth is simply carried out from the upper part of the projection part 11, thus forming a first semiconductor layer 2. At this time, lateral direction growth occurs, thus setting the recessed part 12 to a cavity part 13 for remaining. A substance (an anti-surfactant material) for changing a surface state operates on the surface of the first semiconductor layer 2 to fix an anti-surfactant material 3. After that, the feed gas is supplied, a second semiconductor layer 4 that is generated with dot structure made of a semiconductor crystal as a new crystal growth nucleus is used, and the semiconductor base is completed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明が属する技術分野】本発明は、半導体基材及びそ
の製造方法に関し、特に用いる材料がGaN系化合物半
導体の場合に好適な半導体基材及びその製造方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method of manufacturing the same, and more particularly to a semiconductor substrate suitable for a case where a material used is a GaN-based compound semiconductor and a method of manufacturing the same.

【0002】[0002]

【従来の技術】GaN系化合物半導体結晶のエピタキシ
ャル成長は、格子整合する基板の入手が困難であるた
め、一般にサファイア基板などの上にバッファ層を介し
て行われている。この場合、エピタキシャル膜と基板と
の格子不整合のため、成長界面から転位などの格子欠陥
が導入され、エピタキシャル膜の表面には約1010cm
-2オーダーの転位が存在する。前記エピタキシャル膜中
の転位は、デバイスにおいてリーク電流、非発光センタ
ーや電極材料の拡散の原因となるため、転位密度を減ら
す方法が試みられている。
2. Description of the Related Art Epitaxial growth of GaN-based compound semiconductor crystals is generally performed on a sapphire substrate or the like via a buffer layer because it is difficult to obtain a lattice-matched substrate. In this case, lattice defects such as dislocations are introduced from the growth interface due to lattice mismatch between the epitaxial film and the substrate, and about 10 10 cm
There are -2 order dislocations. Dislocations in the epitaxial film cause leakage current, non-light-emitting centers, and diffusion of electrode materials in the device. Therefore, a method of reducing the dislocation density has been attempted.

【0003】その一つとして、例えば特開平10−31
2971号公報に記載されているような、選択成長を用
いた方法がある。この方法は、SiOなどのマスク材
料を用いて基板上にパターニングを施与して選択成長を
行い、さらにこのマスク材料を埋め込むまで成長を続け
ることで、マスク材料により転位が遮断され、或いはマ
スク上における結晶成長過程で転位の伝搬方向が曲げら
れるなどの効果により、転位密度の低減がなされるもの
である。
As one of them, for example, Japanese Patent Laid-Open No. 10-31
There is a method using selective growth as described in Japanese Patent No. 2971. According to this method, patterning is performed on a substrate by using a mask material such as SiO 2 to perform selective growth, and further, growth is continued until the mask material is buried. The dislocation density is reduced by the effect of bending the dislocation propagation direction during the crystal growth process.

【0004】[0004]

【発明が解決しようとする課題】しかしながら上記の方
法では、マスク材料を埋め込む際に、マスク上を成長面
に対して横方向に成長した結晶が、成長が進むにつれそ
の結晶軸が傾く(Tilt;チルト)という現象がおこ
る。マスク上ではチルトした結晶同士が合体するのでそ
こで新たな欠陥が発生する。結晶軸がチルトする原因は
定かではないが、マスク材料が影響しているものと考え
られる。また、マスクを作製する工程はエピタキシャル
結晶成長装置から一旦外部に取り出してから行う必要が
あるため、工程の複雑化、基板の汚染、又は基板表面が
損傷を受ける可能性がある等の問題を有している。特に
上記のマスクを使った選択成長プロセスを多重化する場
合の、エピタキシャル成長装置から一旦外部に取り出す
工程の煩雑さと汚染・表面損傷の可能性の問題は大き
い。
However, in the above method, when the mask material is buried, the crystal grown on the mask in the lateral direction with respect to the growth surface has its crystal axis tilted as the growth proceeds (Tilt; A phenomenon called tilt occurs. Since the tilted crystals are united on the mask, a new defect is generated there. Although the cause of the tilt of the crystal axis is not clear, it is considered that the mask material has an effect. In addition, since the step of fabricating the mask needs to be performed once after being taken out of the epitaxial crystal growth apparatus, there are problems such as complication of the process, contamination of the substrate, or damage to the substrate surface. are doing. In particular, when multiplexing the selective growth process using the above-mentioned mask, there is a large problem in that the step of once taking out from the epitaxial growth apparatus to the outside and the possibility of contamination and surface damage are large.

【0005】近年、ハライド気相エピタキシャル法(H
VPE)等を使って高品質のGaN基板が得られる様に
なってきてはいる。しかし、それでも105〜107cm-2
の転位密度の基板であり、デバイスの高性能化には更に
転位密度を下げることが要求され、また不可欠でもあ
る。
In recent years, the halide vapor phase epitaxial method (H
High quality GaN substrates can be obtained using VPE). However, still 10 5 -10 7 cm -2
It is a substrate having a dislocation density of 2. Therefore, it is required and indispensable to further reduce the dislocation density in order to improve the performance of the device.

【0006】従って本発明は、GaN系化合物半導体結
晶のエピタキシャル成長において、従来の選択成長に用
いられるSiO2などのマスク材料を用いること無しに
転位密度を低減させた、従って成長が進むにつれその結
晶軸が傾くチルト現象が著しく改善された高品質なエピ
タキシャル膜を備える半導体基材、及びエピタキシャル
成長装置に基板を装填してから外部に取り出すことなく
低転位密度のエピタキシャル膜が得られる成長方法を提
供することを目的とし、特に、比較的高品質なGaN基
板を、更に転位密度を低減させ、より高品質なエピタキ
シャル膜を得るための成長方法を提供することを目的と
する。
Accordingly, the present invention reduces the dislocation density in epitaxial growth of a GaN-based compound semiconductor crystal without using a mask material such as SiO 2 used in the conventional selective growth. To provide a semiconductor substrate having a high-quality epitaxial film in which a tilt phenomenon in which a tilt is remarkably improved is improved, and a growth method in which an epitaxial film having a low dislocation density can be obtained without loading a substrate into an epitaxial growth apparatus and taking out the substrate to the outside. In particular, it is an object of the present invention to provide a growth method for obtaining a higher-quality epitaxial film by further reducing the dislocation density of a relatively high-quality GaN substrate.

【0007】[0007]

【課題を解決するための手段】本発明の半導体基材は、
基板の結晶成長面が凹凸面とされ、該凹凸面における凸
部の上方部から専ら結晶成長させて第1半導体層が形成
され、その上にアンチサーファクタント材料が固定化さ
れた界面又は領域を介して第2半導体層が形成されてい
ることを特徴とするものである。
The semiconductor substrate of the present invention comprises:
The crystal growth surface of the substrate is an uneven surface, and the first semiconductor layer is formed exclusively by crystal growth from above the convex portion of the uneven surface, and the first semiconductor layer is formed thereon via an interface or region where an anti-surfactant material is fixed. And a second semiconductor layer is formed.

【0008】また、本発明の半導体基材の製造方法は、
基板上に半導体結晶を気相成長させるにあたり、予め基
板表面に凹凸面加工を施した後に該基板に対して原料ガ
スを供給し、前記凹凸面における凸部の上方部から専ら
結晶成長させて第1の半導体層を形成する工程と、前記
第1の半導体層の表面状態をアンチサーファクタント材
料により変化させ、しかる後原料ガスを供給することで
前記第1の半導体層表面に成長される半導体結晶からな
るドット構造を新たな結晶成長核として生成される第2
の半導体層を形成する工程とを有することを特徴とす
る。
Further, the method for producing a semiconductor substrate according to the present invention comprises:
In vapor-phase growing a semiconductor crystal on a substrate, a raw material gas is supplied to the substrate after subjecting the substrate surface to uneven surface processing in advance, and the crystal is grown exclusively from above the convex portion on the uneven surface. Forming a first semiconductor layer, and changing a surface state of the first semiconductor layer with an anti-surfactant material, and then supplying a raw material gas from a semiconductor crystal grown on the surface of the first semiconductor layer. Generated as a new crystal growth nucleus using the dot structure
Forming a semiconductor layer.

【0009】上記の場合において、アンチサーファクタ
ント材料としてはSiを用いることが好ましい。また、
第1の半導体層の成長を、基板の凹部を第1の半導体層
が覆う前に停止し、次いでその表面状態をアンチサーフ
ァクタント材料により変化させるようにすることは、好
ましい態様である。
In the above case, it is preferable to use Si as the anti-surfactant material. Also,
It is a preferable embodiment that the growth of the first semiconductor layer is stopped before the first semiconductor layer covers the concave portion of the substrate, and then the surface state is changed by the anti-surfactant material.

【0010】[0010]

【作用】基板の結晶成長面が凹凸面とし、該凹凸面にお
ける凸部の上方部から専ら結晶成長させて第1半導体層
を形成する過程は、当該凸部からの結晶成長部だけから
発生した、或いは凸部に存する転位線を承継つつ成長す
るモードと、ラテラル方向成長をなし実質的に無転位状
態の成長モードとを有し、約1桁の転位密度低減効果を
生む。本発明においては、このようにして形成した第1
の半導体層の表面状態をアンチサーファクタント材料に
より変化させ、しかる後第2の半導体層を形成する。ア
ンチサーファクタント材料を供給によって改質された表
面には、アンチサーファクタント材料が固定化されるこ
とになるのであるが、当該固定化されたアンチサーファ
クタント材料が転位線の延伸を阻止する作用をなす。こ
れにより、第1の半導体層中に残留している転位線の延
伸が遮断され、その上に成長される第2の半導体層はさ
らなる低転位密度化が図られるものである。
The crystal growth surface of the substrate is an uneven surface, and the process of forming the first semiconductor layer by exclusively growing the crystal from above the convex portion on the uneven surface occurs only from the crystal growth portion from the convex portion. Alternatively, it has a mode of growing while inheriting dislocation lines existing in the convex portion, and a growth mode of laterally growing and substantially dislocation-free, producing an effect of reducing dislocation density by about one digit. In the present invention, the thus formed first
The surface state of the semiconductor layer is changed by an anti-surfactant material, and then the second semiconductor layer is formed. The antisurfactant material is immobilized on the surface modified by supplying the antisurfactant material, and the immobilized antisurfactant material acts to prevent dislocation lines from extending. Thus, the extension of the dislocation lines remaining in the first semiconductor layer is blocked, and the second semiconductor layer grown thereon further lowers the dislocation density.

【0011】[0011]

【発明の実施の態様】以下図面に基づいて本発明の実施
態様を説明する。図1は本発明にかかる半導体基材の製
造プロセスを示す図である。図において、先ず(a)に
示す通り、基板1の結晶成長面に凸部11と凹部12と
を設ける。その後、この基板に例えばGaN系化合物半
導体などの半導体結晶成長用の原料ガスを供給し、凸部
11の上方部から専ら結晶成長させることで第1の半導
体層2を形成する(図1(b))。この際、ラテラル方
向成長が生じることで凹部12が空洞部13となって残
留する。そして第1の半導体層2の表面に、表面状態を
変化させる物質(アンチサーファクタント材料)を作用
させ、アンチサーファクタント材料3を固定化させる
(図1(c))。しかる後、原料ガスを供給し、半導体
結晶からなるドット構造を新たな結晶成長核として生成
される第2の半導体層4を形成して(図1(d))、本
発明の半導体基材が完成する。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a manufacturing process of a semiconductor substrate according to the present invention. In the figure, first, as shown in (a), a convex portion 11 and a concave portion 12 are provided on a crystal growth surface of a substrate 1. Thereafter, a source gas for growing a semiconductor crystal such as a GaN-based compound semiconductor is supplied to the substrate, and the first semiconductor layer 2 is formed by exclusively growing the crystal from above the convex portion 11 (FIG. 1B). )). At this time, the concave portion 12 becomes the hollow portion 13 due to the lateral growth and remains. Then, a substance (anti-surfactant material) that changes the surface state acts on the surface of the first semiconductor layer 2 to immobilize the anti-surfactant material 3 (FIG. 1C). Thereafter, a source gas is supplied to form a second semiconductor layer 4 that is generated using a dot structure made of a semiconductor crystal as a new crystal growth nucleus (FIG. 1D), and the semiconductor substrate of the present invention is formed. Complete.

【0012】上記した半導体基材について詳述する。基
板1の結晶成長面に形成される凸部11は、その上方部
から専ら結晶成長が行われるような形状とされる。「上
方部から専ら結晶成長が行われる」とは、凸部11の頂
点ないし頂面及びその近傍での結晶成長が優勢に行い得
る状態をいい、成長初期には凹部12での成長が生じて
もよいが最終的には凸部11の結晶成長が優勢となるこ
とを指す。つまり上方部を新たな結晶成長核としたラテ
ラル成長により低転位領域が形成されれば、従来のマス
クを要する選択成長と同様の効果がある。これが基板へ
の凹凸部施与によりマスクレスで成長可能となる。
The above semiconductor substrate will be described in detail. The convex portion 11 formed on the crystal growth surface of the substrate 1 has a shape such that crystal growth is performed exclusively from above. “Crystal growth is performed exclusively from the upper part” refers to a state in which crystal growth can be predominantly performed at the apex or top surface of the convex part 11 and in the vicinity thereof. However, it means that the crystal growth of the convex portion 11 becomes dominant eventually. In other words, if a low dislocation region is formed by lateral growth using the upper part as a new crystal growth nucleus, the same effect as the selective growth requiring a conventional mask can be obtained. This can be grown without a mask by applying the uneven portion to the substrate.

【0013】この実施例では凸部11をストライプ状に
形成した場合を示しており、凹凸の形状にもよるが、こ
の場合第1の半導体層2の原料ガスが凹部12及びその
近傍に十分至らず、凸部11の上方部からしか結晶成長
が起こらない。従って、結晶成長初期は凸部11の上方
部にその断面形状がキノコ状の結晶単位が生成される。
このような状況下、結晶成長が続けられると凸部11の
上方部を起点とし横方向に成長した膜がつながって、や
がて図1(b)のように凹部に空洞部13を残したまま、
基板1の凹凸面を第1の半導体層12が覆うことにな
る。この場合、横方向に成長した部分、つまり凹部12
上部には低転位領域が形成され、作製した膜の高品質化
が図れているのである。
In this embodiment, the case where the projections 11 are formed in a stripe shape is shown, and depending on the shape of the projections and depressions, in this case, the source gas of the first semiconductor layer 2 can sufficiently reach the depressions 12 and its vicinity. In other words, crystal growth occurs only from the upper part of the protrusion 11. Therefore, in the initial stage of crystal growth, a crystal unit having a mushroom-shaped cross section is generated above the convex portion 11.
Under such circumstances, when the crystal growth is continued, the films grown in the lateral direction are connected starting from the upper part of the convex part 11, and eventually the cavity 13 is left in the concave part as shown in FIG.
The first semiconductor layer 12 covers the uneven surface of the substrate 1. In this case, the portion grown in the lateral direction, that is, the concave portion 12 is formed.
A low dislocation region is formed in the upper part, and the quality of the formed film is improved.

【0014】ついで第1の半導体層2の表面にアンチサ
ーファクタント材料を固定化させるのであるが、その方
法としては表面とアンチサーファクタント材料を接触さ
せる手法が挙げられる。接触の方法は限定されないが、
例えば有機金属気相成長法(MOCVD法)を用いる場
合であれば、MOCVD装置内に前記第1の半導体層2
を成長させた基板を据え付け、装置内にアンチサーファ
クタント材料を供給すればよい。その供給方法として
は、例えばテトラエチルシラン(TESi)、シラン
(SiH4)等のSiを含む化合物をガス状として供給
する方法が挙げられる。
Next, an anti-surfactant material is immobilized on the surface of the first semiconductor layer 2, and a method of contacting the anti-surfactant material with the surface is exemplified. The method of contact is not limited,
For example, when the metal organic chemical vapor deposition method (MOCVD method) is used, the first semiconductor layer 2 is placed in a MOCVD apparatus.
What is necessary is just to install the substrate on which the substrate is grown, and supply the anti-surfactant material into the apparatus. As the supply method, for example, tetraethyl silane (TESi), silane method for supplying a compound containing Si (SiH 4) or the like as a gaseous and the like.

【0015】アンチサーファクタント材料を表面に作用
させることにより、表面エネルギーが高い、微小な領域
が表面に多数存在するようになる。すなわち、アンチサ
ーファクタント材料3が基板表面に固定化されることに
なる(図1(c))。
By making the antisurfactant material act on the surface, a large number of minute regions having a high surface energy are present on the surface. That is, the anti-surfactant material 3 is immobilized on the substrate surface (FIG. 1C).

【0016】その後連続して第2の半導体層4の材料と
しての、例えばGaN系化合物半導体材料を供給する
と、表面エネルギーの高い領域からはGaN系化合物半
導体は成長しにくく、ドット構造が形成される。この現
象は、アンチサーファクタント材料が基板上に吸着又は
化学結合により固定化されて結晶表面を覆い、GaN系
結晶の二次元成長を阻害するとも解釈される。即ち、あ
たかも選択成長に用いるSiO2マスクの如く作用する
ものであって、このような作用は、Ge、Mg、Zn等
のアンチサーファクタント材料でも得られる。しかしな
がら、結晶の汚染の問題を回避するという点において、
Siを用いることが望ましい。
Subsequently, when, for example, a GaN-based compound semiconductor material is continuously supplied as the material of the second semiconductor layer 4, the GaN-based compound semiconductor hardly grows from a region having a high surface energy, and a dot structure is formed. . This phenomenon is also interpreted as that the antisurfactant material is immobilized on the substrate by adsorption or chemical bonding to cover the crystal surface and inhibit two-dimensional growth of the GaN-based crystal. That is, it acts as if it were a SiO 2 mask used for selective growth, and such an effect can be obtained even with an anti-surfactant material such as Ge, Mg, Zn or the like. However, in avoiding the problem of crystal contamination,
It is desirable to use Si.

【0017】本発明におけるドット構造とは、アンチサ
ーファクタント材料が作用していない領域、或いはGa
Nの成長を阻害しない領域から発生する微小構造体を指
し、その形状は多面構造、ドーム状、棒状など、様々な
形態を呈し、かかる形態は結晶成長条件、下地の結晶
性、アンチサーファクタント材料の分布密度などにより
異なることになる。
The dot structure according to the present invention refers to a region where an anti-surfactant material does not act,
This refers to a microstructure generated from a region that does not inhibit the growth of N, and has various shapes such as a polyhedral structure, a dome shape, a rod shape, and the like. It depends on the distribution density.

【0018】アンチサーファクタント材料が作用する領
域の密度は、アンチサーファクタント材料の供給量、供
給時間または基板の温度などにより制御できる。
The density of the region where the anti-surfactant material acts can be controlled by the supply amount, the supply time or the substrate temperature of the anti-surfactant material.

【0019】ドット構造が形成されたあと、さらに連続
してGaN系化合物半導体の成長を行うと、ドット構造
を新たな結晶成長核としてエピタキシャル成長が起こ
り、第2の半導体層4が形成される(図1(d))。ドッ
ト構造は微小開口領域からのエピタキシャル成長によっ
て形成されるため、転位線がこの開口を通して延伸する
確率は極めて低くなり、また下地から伸びた転位線はア
ンチサーファクタント材料のマスクとしての作用で遮断
されるため、エピタキシャル膜表面での転位密度は低減
されることになる。
When the GaN-based compound semiconductor is further continuously grown after the dot structure is formed, epitaxial growth occurs with the dot structure as a new crystal growth nucleus, and the second semiconductor layer 4 is formed. 1 (d)). Since the dot structure is formed by epitaxial growth from the minute opening region, the probability that dislocation lines extend through these openings is extremely low, and dislocation lines extending from the base are blocked by the action of the anti-surfactant material as a mask. The dislocation density on the surface of the epitaxial film is reduced.

【0020】本発明によれば、基板1への凹凸面形成に
よるラテラル方向成長にて第1の半導体層2を成長し、
その表面上へのアンチサーファクタント材料3の固定化
(原子レベルのマスクといえる)によるラテラル方向成
長にて第2の半導体層4を成長するので、転位線の遮断
を2段階で行うことができるので、成長結晶層の一層の
低転位密度化が図られる。このような多段階の転位線遮
断は、基板1へ施与した凹凸面を第1の半導体層2の表
面に施与することでも達成できるが、この場合は一旦基
板を成長炉から取り出して凹凸加工をせねばならず、作
業性の観点からは不都合が有るが、本発明の方法では連
続的にこれらの工程を行えるので好ましい。
According to the present invention, the first semiconductor layer 2 is grown by lateral growth by forming an uneven surface on the substrate 1,
Since the second semiconductor layer 4 is grown by lateral growth by immobilizing the anti-surfactant material 3 on the surface (it can be called an atomic level mask), dislocation lines can be cut off in two stages. In addition, the dislocation density of the grown crystal layer can be further reduced. Such multi-stage dislocation line blocking can also be achieved by applying the uneven surface applied to the substrate 1 to the surface of the first semiconductor layer 2, but in this case, the substrate is once taken out of the growth furnace and Processing must be performed, which is inconvenient from the viewpoint of workability, but the method of the present invention is preferable because these steps can be performed continuously.

【0021】なお、第1の半導体層2の成長において、
該層が凹部12を覆う前に、即ち上述したキノコ状の結
晶単位の段階で第1の半導体層2の成長を停止し、アン
チサーファクタント材料3を前記キノコ状の結晶単位の
表面に固定化するようにしてもよい。転位線は成長条件
によってはラテラル方向に延伸する場合があり、そして
このような転位線の複数が互いに合流して大きな転位欠
陥を生起する場合があるが、キノコ状の結晶単位の段階
でアンチサーファクタント材料3を固定化して転位線の
延伸を遮断すれば、このような転位欠陥の生成を低減で
きる意味において有用である。
In the growth of the first semiconductor layer 2,
Before the layer covers the concave portion 12, that is, at the stage of the above-mentioned mushroom-shaped crystal unit, the growth of the first semiconductor layer 2 is stopped, and the anti-surfactant material 3 is fixed on the surface of the mushroom-shaped crystal unit. You may do so. Depending on the growth conditions, the dislocation lines may extend in the lateral direction, and a plurality of such dislocation lines may merge with each other to generate a large dislocation defect. It is useful to fix the material 3 to block the dislocation lines from being stretched in order to reduce the generation of such dislocation defects.

【0022】上記した基板1とは、各種の半導体結晶層
を成長させるためのベースとなる基板であって、格子整
合のためのバッファ層等も未だ形成されていない状態の
ものを言う。このような基板としては、サファイア(C
面、A面、R面)、SiC(6H、4H、3C)、Ga
N、Si、スピネル、ZnO,GaAs,NGOなどを
用いることができるが、発明の目的に対応するならばこ
のほかの材料を用いてもよい。なお、基板の面方位は特
に限定されなく、ジャスト基板でも良いしオフ角を付与
した基板であっても良い。更に、サファイア基板などに
数μmのGaN系半導体をエピタキシャル成長してある
基板を用いても良い。
The above-mentioned substrate 1 is a substrate serving as a base for growing various semiconductor crystal layers, and has no buffer layer or the like for lattice matching. As such a substrate, sapphire (C
Plane, A plane, R plane), SiC (6H, 4H, 3C), Ga
N, Si, spinel, ZnO, GaAs, NGO, and the like can be used, but other materials may be used as long as they correspond to the object of the invention. The plane orientation of the substrate is not particularly limited, and may be a just substrate or a substrate having an off angle. Further, a substrate in which a GaN-based semiconductor of several μm is epitaxially grown on a sapphire substrate or the like may be used.

【0023】基板1上に成長される半導体結晶としては
種々の半導体材料を用いることができ、AlxGa1-x-y
InyN(0≦x≦1、0≦y≦1、0≦x+y≦1)で
はx、yの組成比を変化させたGaN、Al0.5Ga0.5
N、In0.5Ga0.5Nなどが例示できる。
Various semiconductor materials can be used for the semiconductor crystal grown on the substrate 1, and Al x Ga 1-xy
For In y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1), GaN, Al 0.5 Ga 0.5 in which the composition ratio of x and y is changed
N, In 0.5 Ga 0.5 N and the like can be exemplified.

【0024】中でも、AlGaN等のAlを含有する半
導体材料の場合、従来のマスク方式ではSiO2マスク
層上に成長するという問題があったが、本発明によると
マスクレス化によりかかる問題が解消されるため、従来
できなかったAlGaNのラテラル成長が可能となり低
転位で高品質な膜の成長が基板直上から可能となる。こ
のため紫外線発光素子等で問題となるGaN層による光
吸収がなくなり応用上特に好適である。
Above all, in the case of a semiconductor material containing Al such as AlGaN, there is a problem that the conventional mask method grows on a SiO 2 mask layer, but according to the present invention, such a problem is solved by maskless operation. Therefore, lateral growth of AlGaN, which could not be performed conventionally, becomes possible, and a high-quality film with low dislocations can be grown directly above the substrate. Therefore, light absorption by the GaN layer, which is a problem in an ultraviolet light emitting element or the like, is eliminated, which is particularly preferable in application.

【0025】[0025]

【実施例】以下具体的な実施例につき説明する。 [実施例1]c面サファイア基板上にフォトレジストの
パターニング(幅:2μm、周期:4μm、ストライプ
方位:ストライプ延伸方向がサファイア基板の<11−
20>方向)を行い、RIE(Reactive Ion Etching)
装置で5μmの深さまで断面方形型にエッチングした。
この時のアスペクト比は2.5であった。フォトレジス
トを除去後、MOVPE装置に基板を装着した。その
後、水素雰囲気下で1100℃まで昇温し、サーマルエ
ッチングを行った。その後温度を500℃まで下げ、3
族原料としてトリメチルガリウム(以下TMG)を、N
原料としてアンモニアを流し、GaN低温バッファー層
を成長した。つづいて温度を1000℃に昇温し原料と
してTMG・アンモニアを、ドーパントとしてシランを
流し、第1の半導体層としてのn型GaN層を成長し
た。その時の成長時間は、通常の凹凸の施していない場
合のGaN成長における4μmに相当する時間とした。
これにより、図1(b)に示すように凹部に空洞部13を
残したまま凹凸部を覆い、平坦になったGaN膜からな
る第1の半導体層2が得られた。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments will be described below. Example 1 Patterning of photoresist on a c-plane sapphire substrate (width: 2 μm, period: 4 μm, stripe orientation: stripe extension direction is <11−
20> direction) and RIE (Reactive Ion Etching)
The apparatus was etched in a rectangular shape in cross section to a depth of 5 μm.
The aspect ratio at this time was 2.5. After removing the photoresist, the substrate was mounted on a MOVPE apparatus. Thereafter, the temperature was raised to 1100 ° C. in a hydrogen atmosphere, and thermal etching was performed. Then lower the temperature to 500 ° C,
Trimethylgallium (hereinafter referred to as TMG)
Ammonia was flowed as a raw material to grow a GaN low temperature buffer layer. Subsequently, the temperature was raised to 1000 ° C., TMG / ammonia was flowed as a raw material, and silane was flowed as a dopant, to grow an n-type GaN layer as a first semiconductor layer. The growth time at that time was set to a time corresponding to 4 μm in the GaN growth in the case where the normal unevenness was not applied.
Thus, as shown in FIG. 1B, the first semiconductor layer 2 made of a flat GaN film was obtained by covering the uneven portion while leaving the hollow portion 13 in the concave portion.

【0026】次にTMG、アンモニアの供給を止め、成
長温度をそのままとして、続いてH2をキャリアガスと
して、アンチサーファクタント材料としてのSiを含む
化合物であるテトラエチルシランを供給し、第1の半導
体層2の表面に10秒間接触させた。
Next, supply of TMG and ammonia is stopped, the growth temperature is kept as it is, and subsequently, tetraethylsilane, which is a compound containing Si as an antisurfactant material, is supplied using H2 as a carrier gas, and the first semiconductor layer 2 is formed. For 10 seconds.

【0027】テトラエチルシランの供給を止め、再び第
2の半導体層4形成のための原料としてのTMG、アン
モニアを供給し、GaNからなるドット構造を形成し
た。その後連続して原料を供給し、ドット同士が合体
し、表面が平坦に埋め込まれるまで成長を続けた。これ
により、厚さ2μmのGaNからなる第2の半導体層4
を形成した。
The supply of tetraethylsilane was stopped, and TMG and ammonia were again supplied as raw materials for forming the second semiconductor layer 4 to form a dot structure made of GaN. Thereafter, the raw material was continuously supplied, and the growth was continued until the dots were united and the surface was buried flat. Thereby, the second semiconductor layer 4 made of GaN having a thickness of 2 μm is formed.
Was formed.

【0028】このようにして成長した第2の半導体層4
表面の転位密度を測定したところ、105cm-2であっ
た。また断面TEM観察から、空洞上部での新たな欠陥
の発生は観察されなかった。
The second semiconductor layer 4 thus grown
When the dislocation density on the surface was measured, it was 10 5 cm -2 . From the cross-sectional TEM observation, no new defect was observed in the upper part of the cavity.

【0029】[実施例2]上記実施例1で得られた半導
体基材における第2の半導体層4の表面に、上記と同様
にしてアンチサーファクタント材料の供給源としてのテ
トラエチルシランを供給し、その後結晶成長させる工程
を繰り返し、アンチサーファクタント材料が固定化され
た界面を5つ多重化したGaN半導体結晶を作製した。
5つ目の界面上に成長したGaN半導体結晶層の転位密
度を測定したところ、102cm-2まで低下した。
[Example 2] Tetraethylsilane as a source of an anti-surfactant material was supplied to the surface of the second semiconductor layer 4 in the semiconductor substrate obtained in Example 1 in the same manner as described above. The step of growing the crystal was repeated to produce a GaN semiconductor crystal in which five interfaces where the anti-surfactant material was fixed were multiplexed.
When the dislocation density of the GaN semiconductor crystal layer grown on the fifth interface was measured, it was reduced to 10 2 cm −2 .

【0030】[0030]

【発明の効果】以上説明した通りの本発明の半導体基材
及びその製造方法によれば、マスク材料を用いること無
しに転位密度の低減させることができる。これにより高
品質なGaN系化合物半導体結晶の作製が可能となる。
この上にLEDやLDなどの半導体発光素子や受光素
子、電子デバイスを作製すれば、その特性は飛躍的に向
上することが期待される。
According to the semiconductor substrate and the method of manufacturing the same of the present invention as described above, the dislocation density can be reduced without using a mask material. This makes it possible to produce a high-quality GaN-based compound semiconductor crystal.
If semiconductor light-emitting elements such as LEDs and LDs, light-receiving elements, and electronic devices are fabricated thereon, the characteristics thereof are expected to be dramatically improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体基材の製造工程を示す概略図で
ある。
FIG. 1 is a schematic view showing a manufacturing process of a semiconductor substrate of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 11 凸部 12 凹部 13 空洞部 2 第1の半導体層 3 アンチサーファクタント材料 4 第2の半導体層 DESCRIPTION OF SYMBOLS 1 Substrate 11 Convex part 12 Concavity 13 Cavity part 2 First semiconductor layer 3 Anti-surfactant material 4 Second semiconductor layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大内 洋一郎 兵庫県伊丹市池尻4丁目3番地 三菱電線 工業株式会社伊丹製作所内 Fターム(参考) 5F041 AA40 CA33 CA40 CA65 CA74 5F045 AA04 AB14 AC01 AC08 AC09 AC12 AF02 AF04 AF09 AF12 AF14 BB12 DA52 DA53 5F073 CA01 CB05 CB19 DA05  ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Yoichiro Ouchi 4-3 Ikejiri, Itami-shi, Hyogo Mitsubishi Electric Cable Industry Co., Ltd. Itami Works F-term (reference) 5F041 AA40 CA33 CA40 CA65 CA74 5F045 AA04 AB14 AC01 AC08 AC09 AC12 AF02 AF04 AF09 AF12 AF14 BB12 DA52 DA53 5F073 CA01 CB05 CB19 DA05

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板の結晶成長面が凹凸面とされ、該凹
凸面における凸部の上方部から専ら結晶成長させて第1
半導体層が形成され、その上にアンチサーファクタント
材料が固定化された界面又は領域を介して第2半導体層
が形成されていることを特徴とする半導体基材。
1. A crystal growth surface of a substrate is an uneven surface, and a crystal is exclusively grown from an upper portion of a convex portion on the uneven surface to form a first crystal.
A semiconductor substrate having a semiconductor layer formed thereon and a second semiconductor layer formed thereon via an interface or region where an anti-surfactant material is fixed.
【請求項2】 基板上に半導体結晶を気相成長させるに
あたり、予め基板表面に凹凸面加工を施した後に該基板
に対して原料ガスを供給し、前記凹凸面における凸部の
上方部から専ら結晶成長させて第1の半導体層を形成す
る工程と、前記第1の半導体層の表面状態をアンチサー
ファクタント材料により変化させ、しかる後原料ガスを
供給することで前記第1の半導体層表面に成長される半
導体結晶からなるドット構造を新たな結晶成長核として
生成される第2の半導体層を形成する工程とを有するこ
とを特徴とする半導体基材の成長方法。
2. In growing a semiconductor crystal on a substrate in a vapor phase, a raw material gas is supplied to the substrate after subjecting the substrate surface to an uneven surface processing in advance, and the raw material gas is exclusively supplied from an upper portion of the convex portion on the uneven surface. Forming a first semiconductor layer by crystal growth, changing the surface state of the first semiconductor layer with an anti-surfactant material, and then supplying a source gas to grow the first semiconductor layer on the surface of the first semiconductor layer Forming a second semiconductor layer generated using a dot structure made of the semiconductor crystal to be used as a new crystal growth nucleus.
【請求項3】 アンチサーファクタント材料がSiであ
ることを特徴とする請求項1又は2記載の成長方法。
3. The growth method according to claim 1, wherein the anti-surfactant material is Si.
JP2000083324A 2000-03-24 2000-03-24 Semiconductor substrate and manufacturing method thereof Expired - Fee Related JP4665286B2 (en)

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WO2003071610A1 (en) * 2002-02-25 2003-08-28 Mitsubishi Cable Industries, Ltd. Light emitting device and lighting fixture using it
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JP2008219025A (en) * 2002-12-05 2008-09-18 Ngk Insulators Ltd Semiconductor lamination structure and method for reducing dislocation of group iii nitride layer group
US6927149B2 (en) 2003-01-14 2005-08-09 Matsushita Electric Industrial Co., Ltd. Nitride semiconductor device and fabrication method thereof, and method for forming nitride semiconductor substrate
JP2009510729A (en) * 2005-09-30 2009-03-12 晶能光▲電▼(江西)有限公司 Method for producing an indium gallium aluminum nitride thin film on a silicon substrate
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