JP2001257217A - Structure and method for mounting semiconductor device - Google Patents

Structure and method for mounting semiconductor device

Info

Publication number
JP2001257217A
JP2001257217A JP2000066527A JP2000066527A JP2001257217A JP 2001257217 A JP2001257217 A JP 2001257217A JP 2000066527 A JP2000066527 A JP 2000066527A JP 2000066527 A JP2000066527 A JP 2000066527A JP 2001257217 A JP2001257217 A JP 2001257217A
Authority
JP
Japan
Prior art keywords
semiconductor device
mounting
lead portion
die pad
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000066527A
Other languages
Japanese (ja)
Inventor
Katsuki Uchiumi
勝喜 内海
Toru Nomura
徹 野村
Shigeji Oida
成志 老田
Masaji Funakoshi
正司 舩越
Noboru Tani
昇 谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000066527A priority Critical patent/JP2001257217A/en
Publication of JP2001257217A publication Critical patent/JP2001257217A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the mounting strength of a semiconductor device at the time of mounting the device on a mounting substrate, by increasing the joining spots between the device and substrate when a lead section arranged on the bottom face of the device is joined to the substrate by soldering. SOLUTION: The semiconductor device is mounted on the mounting substrate by joining the exposed bottom face section and one external side face of a lead section 2 arranged on the bottom face of the device to the substrate by soldering 8 and, in addition, the terminal end sections 3a of a hanging lead section 3 which is exposed on the bottom face of the device and has no electrical relation with the device are joined to the substrate by soldering 8 as mounting reinforcing sections. Consequently, the number of joining spots is increased and, accordingly, the mounting strength is improved and the influence of the stress which is impressed upon the device depending upon the used condition of the device is eliminated. Therefore, the reliability of secondary mounting can be improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の底面に
面配置されたリード部等の電極端子がプリント基板上に
接合材を用いて実装された半導体装置の実装構造および
半導体装置の実装方法に関するものであり、特にその基
板実装において、実装強度を向上させ、二次実装の信頼
性を向上させることができる半導体装置の実装構造およ
び半導体装置の実装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure in which electrode terminals such as leads arranged on the bottom surface of a semiconductor device are mounted on a printed circuit board using a bonding material, and a method of mounting the semiconductor device. More particularly, the present invention relates to a semiconductor device mounting structure and a semiconductor device mounting method capable of improving the mounting strength and improving the reliability of the secondary mounting in the substrate mounting.

【0002】[0002]

【従来の技術】従来、配線が形成されたプリント基板上
に対して半導体装置を実装する方法として、半導体装置
の底面に配置されたリード部をハンダを接合材として用
いて実装していた。
2. Description of the Related Art Conventionally, as a method of mounting a semiconductor device on a printed circuit board on which wiring has been formed, a lead portion disposed on the bottom surface of the semiconductor device has been mounted using solder as a bonding material.

【0003】以下、従来の半導体装置の実装構造および
半導体装置の実装方法について、図面を参照しながら説
明する。
A conventional semiconductor device mounting structure and a conventional semiconductor device mounting method will be described below with reference to the drawings.

【0004】まず図5、図6は従来のプリント基板に実
装される半導体装置を示す図であり、図5(a)は平面
図、図5(b)は底面図である。図6(a)は内部構成
を示した平面透視図、図6(b)は図6(a)のA−A
1箇所の断面図、図6(c)は図6(a)のB−B1箇
所の断面図である。
FIGS. 5 and 6 show a conventional semiconductor device mounted on a printed circuit board. FIG. 5A is a plan view and FIG. 5B is a bottom view. FIG. 6A is a perspective plan view showing the internal configuration, and FIG. 6B is a sectional view taken along line AA in FIG.
FIG. 6C is a cross-sectional view of one location B-B1 in FIG. 6A.

【0005】従来の基板に実装される半導体装置は、図
5に示すように、パッケージを構成する封止樹脂1の底
面にリード部2が配列され、封止樹脂1の端部に吊りリ
ード部3の末端部3aが露出した構造を有している。具
体的には図6に示すように、半導体素子4と、その半導
体素子4を支持したダイパッド部5と、ダイパッド部5
をその先端部で支持した吊りリード部3と、ダイパッド
部5に先端部が配置されたリード部2と、そのリード部
2と半導体素子4とを電気的に接続した金属細線6と、
吊りリード部3の末端部3aおよびリード部2の一側面
と底面とを露出させ、半導体素子4、ダイパッド部5、
金属細線6の外囲を封止した封止樹脂1とよりなる半導
体装置である。なお、図6において、半導体素子4は破
線で示している。
In a conventional semiconductor device mounted on a substrate, as shown in FIG. 5, leads 2 are arranged on the bottom surface of a sealing resin 1 constituting a package, and hanging leads 3 has a structure in which the end 3a is exposed. Specifically, as shown in FIG. 6, a semiconductor element 4, a die pad portion 5 supporting the semiconductor element 4, and a die pad portion 5
, A lead portion 2 having a tip portion disposed on a die pad portion 5, a thin metal wire 6 electrically connecting the lead portion 2 and the semiconductor element 4,
The terminal 3a of the suspension lead 3 and one side and bottom of the lead 2 are exposed, and the semiconductor element 4, the die pad 5,
This is a semiconductor device including a sealing resin 1 in which the outer periphery of the thin metal wire 6 is sealed. In FIG. 6, the semiconductor element 4 is shown by a broken line.

【0006】以上のように構成された従来の半導体装置
をプリント基板等の実装基板に実装するには、図7の実
装構造を示す断面図に示すように、半導体装置のリード
部2と実装基板7の電極、配線等の接続箇所とをハンダ
8を用いて実装するものである。
In order to mount the conventional semiconductor device configured as described above on a mounting substrate such as a printed circuit board, as shown in a sectional view showing the mounting structure of FIG. 7 and the connection portions such as wiring and the like are mounted using solder 8.

【0007】つまり従来の半導体装置の実装において
は、半導体装置の底面に配列されたリード部2と実装基
板7とをハンダ8で接合するというものであった。
In other words, in the conventional mounting of the semiconductor device, the leads 2 arranged on the bottom surface of the semiconductor device and the mounting substrate 7 are joined by the solder 8.

【0008】[0008]

【発明が解決しようとする課題】しかしながら従来の半
導体装置の実装構造では、基板実装において実装強度が
十分でない場合があり、より接合強度を向上させた実装
構造が必要であった。すなわち従来は半導体装置の底面
に面配置されたリード部の底面および露出した一側面と
実装基板とをハンダにより接合しているものであり、接
合箇所が少ないため実装強度が不十分であるという課題
があった。特に基板実装後の使用状態によっては、応力
が印加される場合があり、そのような過酷な使用状況で
は従来の実装構造では対応できない恐れがあった。
However, in the conventional mounting structure of a semiconductor device, the mounting strength may not be sufficient for mounting on a substrate, and a mounting structure with further improved bonding strength is required. That is, conventionally, the bottom surface and one exposed side surface of the lead portion arranged on the bottom surface of the semiconductor device are joined to the mounting board by soldering, and the mounting strength is insufficient because the number of joints is small. was there. Particularly, stress may be applied depending on the use state after mounting on the board, and there is a possibility that the conventional mounting structure cannot cope with such severe use conditions.

【0009】またQFP(Quad Flat Pac
kage)等の半導体装置のように、リード部がパッケ
ージ本体から突出している場合は、基板実装時にリード
部の底面と各側面とをハンダ等の接合材により接合で
き、接合箇所が確保でき、相当の実装強度を得ることが
できるが、前記したリード部が面配置されたような最近
のQFN(Quad Flat Non−leaded
Package)では実装強度の向上が要望されてい
た。
Further, QFP (Quad Flat Pac)
In the case where the lead portion protrudes from the package body as in the case of a semiconductor device such as a semiconductor device such as a semiconductor device, the bottom surface and each side surface of the lead portion can be joined with a joining material such as solder at the time of mounting on a substrate, so that a joining portion can be secured. However, recent QFNs (Quad Flat Non-leaded) in which the above-described leads are arranged on the surface can be obtained.
(Package) demanded an improvement in mounting strength.

【0010】本発明は前記従来の半導体装置の実装構造
での課題を解決するとともに、最近のQFN型の半導体
装置において、飛躍的に実装強度を向上させ、使用状況
による影響を解消し、二次実装の信頼性を向上させるこ
とができる半導体装置の実装構造および半導体装置の実
装方法を提供するものである。
The present invention solves the above-mentioned problems in the conventional mounting structure of a semiconductor device, and in a recent QFN type semiconductor device, dramatically improves the mounting strength and eliminates the influence of the use situation, It is an object of the present invention to provide a semiconductor device mounting structure and a semiconductor device mounting method capable of improving mounting reliability.

【0011】[0011]

【課題を解決するための手段】前記従来の課題を解決す
るために本発明の半導体装置の実装構造は、その底面に
電気的接続用のリード部と、封止された半導体素子を支
持したダイパッド部を支持している吊リードの末端部と
が配列された半導体装置を実装基板に実装した半導体装
置の実装構造であって、少なくとも前記リード部の底面
が接合材で実装されるとともに、実装補強部として前記
半導体装置の底面から露出した前記吊りリード部の末端
部が接合材で実装されている半導体装置の実装構造であ
る。
In order to solve the above-mentioned conventional problems, a mounting structure of a semiconductor device according to the present invention comprises a lead portion for electrical connection on a bottom surface thereof, and a die pad supporting a sealed semiconductor element. A mounting structure of a semiconductor device in which a semiconductor device in which end portions of suspension leads that support a portion are arranged is mounted on a mounting board, at least a bottom surface of the lead portion is mounted with a bonding material, and mounting reinforcement is provided. FIG. 4 is a mounting structure of the semiconductor device in which a terminal portion of the suspension lead portion exposed from a bottom surface of the semiconductor device is mounted with a bonding material.

【0012】より具体的には、半導体素子と、前記半導
体素子を支持したダイパッド部と、前記ダイパッド部を
その先端部で支持した吊りリード部と、前記ダイパッド
部に先端部が配置されたリード部と、前記リード部と前
記半導体素子とを電気的に接続した接続手段と、前記吊
りリード部の末端部および前記リード部の一側面と底面
とを露出させ、前記半導体素子、前記ダイパッド部、前
記接続手段の外囲を封止した封止樹脂とよりなる半導体
装置を実装基板に実装した半導体装置の実装構造であっ
て、前記リード部の一側面と底面とが接合材で実装され
るとともに、実装補強部として前記半導体装置の底面の
端部から露出した吊りリード部の末端部が接合材で実装
されている半導体装置の実装構造である。
More specifically, a semiconductor element, a die pad portion supporting the semiconductor element, a suspension lead portion supporting the die pad portion at a tip end thereof, and a lead portion having a tip end portion arranged on the die pad portion Connecting means for electrically connecting the lead portion and the semiconductor element, and exposing an end portion of the suspension lead portion and one side surface and bottom surface of the lead portion, the semiconductor element, the die pad portion, A mounting structure of a semiconductor device in which a semiconductor device made of a sealing resin that seals the outer periphery of the connection means is mounted on a mounting substrate, and one side surface and a bottom surface of the lead portion are mounted with a bonding material, This is a mounting structure of a semiconductor device in which a terminal portion of a suspension lead portion exposed from an end portion of a bottom surface of the semiconductor device as a mounting reinforcing portion is mounted with a bonding material.

【0013】また本発明の半導体装置の実装方法は、半
導体素子と、前記半導体素子を支持したダイパッド部
と、前記ダイパッド部をその先端部で支持した吊りリー
ド部と、前記ダイパッド部に先端部が配置されたリード
部と、前記リード部と前記半導体素子とを電気的に接続
した接続手段と、前記吊りリード部の末端部および前記
リード部の一側面と底面とを露出させ、前記半導体素
子、前記ダイパッド部、前記接続手段の外囲を封止した
封止樹脂とよりなる半導体装置を実装基板に実装するに
際し、前記半導体装置の前記リード部の一側面と底面と
を接合材で実装するとともに、実装補強部として前記半
導体装置の底面の端部から露出した吊りリード部の末端
部をも前記接合材で実装する半導体装置の実装方法であ
る。
The method of mounting a semiconductor device according to the present invention may further comprise a semiconductor element, a die pad supporting the semiconductor element, a suspension lead supporting the die pad at its tip, and a tip attached to the die pad. The arranged lead portion, connection means for electrically connecting the lead portion and the semiconductor element, and exposing the end portion of the suspension lead portion and one side surface and the bottom surface of the lead portion, the semiconductor element, When mounting the die pad portion, a semiconductor device made of a sealing resin that seals the outer periphery of the connection means on a mounting substrate, mounting one side surface and the bottom surface of the lead portion of the semiconductor device with a bonding material A method of mounting a semiconductor device in which a terminal of a suspension lead exposed from an end of a bottom surface of the semiconductor device as a mounting reinforcing portion is also mounted with the bonding material.

【0014】また、接合材はハンダを用いるものであ
り、プリント基板に半導体装置を実装するものである。
The bonding material uses solder, and is used for mounting a semiconductor device on a printed circuit board.

【0015】前記構成の通り、半導体装置の底面に配置
されたリード部の露出した底面部と外方の一側面とをハ
ンダにより実装基板に接合して実装する構造に加えて、
底面に露出した電気的に関係のない吊りリード部の末端
部をも実装補強部として実装基板に接合して実装する構
造であるため、接合箇所が増加するため、飛躍的に実装
強度を向上させ、使用状況により印加される応力による
影響を解消し、二次実装の信頼性を向上させることがで
きるものである。
As described above, in addition to the structure in which the exposed bottom surface portion of the lead portion disposed on the bottom surface of the semiconductor device and one outer side surface are joined to a mounting substrate by soldering,
The structure is such that the end of the electrically unrelated suspension lead exposed on the bottom surface is also joined to the mounting board as a mounting reinforcement, and the number of joints increases, dramatically increasing the mounting strength. In addition, it is possible to eliminate the influence of the stress applied depending on the use condition and improve the reliability of the secondary mounting.

【0016】特に露出した吊りリード部の末端部が半導
体装置の底面(実装面)の各角部の端部に配置している
場合は、実装強度を向上させるとともに、実装バランス
の均整による実装信頼性を向上させることができる。
In particular, when the end portions of the exposed suspension leads are arranged at the ends of the corners of the bottom surface (mounting surface) of the semiconductor device, the mounting strength is improved and the mounting reliability is improved by balancing the mounting balance. Performance can be improved.

【0017】[0017]

【発明の実施の形態】以下、本発明の半導体装置の実装
構造および半導体装置の実装方法の一実施形態につい
て、図面を参照しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device mounting structure and a semiconductor device mounting method according to the present invention will be described below with reference to the drawings.

【0018】まず図1、図2は本実施形態におけるプリ
ント基板に実装される半導体装置を示す図であり、図1
(a)は平面図、図1(b)は底面図である。図2
(a)は内部構成を示した平面透視図、図2(b)は図
2(a)のC−C1箇所の断面図、図2(c)は図2
(a)のD−D1箇所の断面図である。
FIGS. 1 and 2 show a semiconductor device mounted on a printed circuit board according to this embodiment.
1A is a plan view, and FIG. 1B is a bottom view. FIG.
2A is a perspective plan view showing an internal configuration, FIG. 2B is a cross-sectional view taken along a line C-C1 in FIG. 2A, and FIG.
It is sectional drawing of DD1 location of (a).

【0019】本実施形態の基板実装される半導体装置
は、図1に示すように、パッケージを構成する封止樹脂
1の底面の端部にリード部2がその底面と外方の一側面
を露出して配列され、封止樹脂1の各角部の端部には吊
りリード部3の末端部3aが露出し、実装補強部を構成
した構造を有している。
As shown in FIG. 1, in the semiconductor device mounted on a substrate according to the present embodiment, a lead portion 2 exposes the bottom surface and one outer side surface at the end of the bottom surface of a sealing resin 1 constituting a package. The end portions 3a of the suspension leads 3 are exposed at the ends of the respective corners of the sealing resin 1 to form a mounting reinforcement portion.

【0020】具体的には図2に示すように、半導体素子
4と、その半導体素子4を支持したダイパッド部5と、
ダイパッド部5をその先端部で支持した吊りリード部3
と、ダイパッド部5に先端部が配置されたリード部2
と、そのリード部2と半導体素子4とを電気的に接続し
た金属細線6と、吊りリード部3の末端部3aおよびリ
ード部2の一側面と底面とを露出させ、半導体素子4、
ダイパッド部5、金属細線6の外囲を封止した封止樹脂
1とよりなるQFN型の半導体装置である。また吊りリ
ード部3は段差部(折り曲げ部)を有し、ダイパッド部
5がリード部2に対してアップセットされた構造を有し
ているものである。したがってダイパッド部5の底面領
域にはアップセット分の厚みで封止樹脂1が存在してい
るものである。また、リード部2、吊りリード部3の末
端部3aの底面は、50[μm]程度の僅かな突出量で
封止樹脂1の面から突出して露出しているものである。
なお、図2において、半導体素子4は破線で示してい
る。
More specifically, as shown in FIG. 2, a semiconductor element 4 and a die pad 5 supporting the semiconductor element 4 are provided.
Suspended lead 3 supporting die pad 5 at its tip
And a lead portion 2 having a tip portion disposed on a die pad portion 5.
To expose the thin metal wire 6 electrically connecting the lead portion 2 and the semiconductor element 4, the end portion 3 a of the suspension lead portion 3 and one side surface and the bottom surface of the lead portion 2,
This is a QFN type semiconductor device including a die pad portion 5 and a sealing resin 1 which seals the outer periphery of the fine metal wire 6. Further, the suspension lead portion 3 has a step portion (bent portion), and has a structure in which the die pad portion 5 is set up with respect to the lead portion 2. Therefore, the sealing resin 1 is present in the bottom region of the die pad portion 5 in a thickness corresponding to the upset. Also, the bottom surfaces of the end portions 3a of the lead portions 2 and the suspension lead portions 3 are projected and exposed from the surface of the sealing resin 1 with a slight protrusion amount of about 50 [μm].
In FIG. 2, the semiconductor element 4 is indicated by a broken line.

【0021】以上のように構成された半導体装置をプリ
ント基板等の実装基板に実装するには、図3(a)の実
装構造を示す断面図に示すように、半導体装置底面のリ
ード部2の底面および外方の一側面と実装基板7の電
極、配線等の接続箇所とを接合材のハンダ8を用いて実
装するものである。そして本実施形態では図3(b)に
示すように、さらに半導体装置底面の各角部の端部に露
出した吊りリード部3の末端部3aと実装基板7の電
極、配線等の接続箇所とをハンダ8を用いて実装するも
のである。本実施形態の半導体装置のリード部2の幅と
しては、200[μm]であり、吊りリード3および末
端部3aの幅としては、180[μm]である。したが
って、吊りリード部3の末端部3aとハンダ8との接合
が可能であり、実装強度の向上に寄与できるものであ
る。
In order to mount the semiconductor device configured as described above on a mounting board such as a printed board, as shown in the cross-sectional view showing the mounting structure of FIG. The bottom surface and one side surface on the outside and the connection portions such as electrodes and wirings of the mounting substrate 7 are mounted using solder 8 of a bonding material. In this embodiment, as shown in FIG. 3 (b), the end 3a of the suspension lead 3 exposed at the end of each corner of the bottom surface of the semiconductor device and the connection points of the mounting board 7 such as electrodes and wiring are further formed. Is mounted using the solder 8. The width of the lead 2 of the semiconductor device of the present embodiment is 200 [μm], and the width of the suspension lead 3 and the end 3a is 180 [μm]. Therefore, the end portion 3a of the suspension lead 3 and the solder 8 can be joined, which can contribute to an improvement in mounting strength.

【0022】本実施形態では、半導体装置の底面に配置
されたリード部2の露出した底面部と外方の一側面とを
ハンダ8により実装基板に接合して実装する構造に加え
て、底面に露出した電気的に関係のない吊りリード部3
の末端部3aをも実装補強部として実装基板に接合して
実装する構造であるため、接合箇所が増加するため、飛
躍的に実装強度を向上させ、使用状況により印加される
応力による影響を解消し、二次実装の信頼性を向上させ
ることができるものである。
In the present embodiment, in addition to the structure in which the exposed bottom surface of the lead portion 2 disposed on the bottom surface of the semiconductor device and one outer side surface are joined to the mounting substrate by solder 8 and mounted, Exposed electrically unrelated suspension leads 3
The end 3a is also joined to the mounting board as a mounting reinforcement part, so that the number of joints increases, so that the mounting strength is dramatically improved and the influence of the stress applied depending on the use situation is eliminated. However, the reliability of the secondary mounting can be improved.

【0023】特に露出した吊りリード部3の末端部3a
が各々同一面積で、半導体装置の底面(実装面)の各角
部の端部に配置している場合は、実装強度を向上させる
とともに、実装バランスの均整による実装信頼性を向上
させることができる。
In particular, the exposed end 3a of the suspension lead 3
Are arranged at the ends of the respective corners of the bottom surface (mounting surface) of the semiconductor device, the mounting strength can be improved, and the mounting reliability can be improved by balancing the mounting balance. .

【0024】また本実施形態では、図1に示したよう
に、パッケージを構成する封止樹脂1の各角部を面取り
した構成とし、吊りリード部3の末端部3aの端部(端
面)がその面取り部分に露出するように構成している
が、図4に示すように、パッケージを構成する封止樹脂
1の平面形状を面取りのない四角形とし、吊りリード部
3の末端部3aの端部(端面)を角部として露出させて
もよい。この場合、吊りリード部3の末端部3aがパッ
ケージの角部に近づき、角部でも実装できるので、実装
強度をさらに向上させることができる。ここで図4は本
実施形態におけるプリント基板に実装される半導体装置
を示す図であり、図4(a)は平面図、図4(b)は底
面図である。
Further, in this embodiment, as shown in FIG. 1, each corner of the sealing resin 1 constituting the package is chamfered, and the end (end face) of the end 3a of the suspension lead 3 is formed. Although it is configured so as to be exposed at the chamfered portion, as shown in FIG. The (end face) may be exposed as a corner. In this case, since the end 3a of the suspension lead 3 approaches the corner of the package and can be mounted at the corner, the mounting strength can be further improved. Here, FIG. 4 is a diagram showing a semiconductor device mounted on a printed circuit board according to the present embodiment, wherein FIG. 4A is a plan view and FIG. 4B is a bottom view.

【0025】本実施形態の半導体装置の実装方法として
は、半導体装置を実装基板に実装するに際し、半導体装
置のリード部3の一側面と底面とを接合材であるハンダ
8で実装するとともに、実装補強部として半導体装置の
底面の端部から露出した吊りリード部3の末端部3aを
もハンダ8で実装するものであり、ハンダリフロー工程
で一括で接合するものである。
The method of mounting the semiconductor device according to the present embodiment is as follows. When the semiconductor device is mounted on a mounting board, one side surface and the bottom surface of the lead portion 3 of the semiconductor device are mounted with solder 8 as a bonding material. The end 3a of the suspension lead 3 exposed from the end of the bottom surface of the semiconductor device as a reinforcement is also mounted with solder 8, and is joined together in a solder reflow process.

【0026】以上、本実施形態では、底面にリード部が
その底面と外方の一側面とを露出して配列されたQFN
型の半導体装置を例として説明したが、SON(Sma
llOutline Non−leaded Pack
age)型の半導体装置であっても同様の実装強度向上
の効果がある。またダイパッド部が底面に露出したタイ
プの半導体装置であっても同様の実装強度向上の効果が
ある。つまり、半導体装置の底面に電気的に関係のない
吊りリード部の末端部が露出したタイプの半導体装置で
あれば、リード部と基板との接合に加えて、露出した吊
りリード部の末端部と基板とをも接合させることができ
るので、実装強度を向上させることができる。特に近年
の小型化した携帯電話に半導体装置を搭載した際にはそ
の使用状況が過酷となり、実装基板に撓み等による応力
が印加され、接合部分に応力が印加されても、その影響
を解消し、二次実装の信頼性を向上させることができる
ものである。
As described above, in this embodiment, the QFN in which the lead portions are arranged on the bottom surface with the bottom surface and one outer side surface exposed.
Although the semiconductor device of the SON (Sma) type has been described as an example,
llOutline Non-leaded Pack
An age-type semiconductor device has the same effect of improving the mounting strength. Also, a semiconductor device of the type in which the die pad portion is exposed on the bottom surface has the same effect of improving the mounting strength. In other words, in the case of a semiconductor device in which the end of the suspension lead that is not electrically related to the bottom surface of the semiconductor device is exposed, in addition to the joining of the lead and the substrate, the end of the exposed suspension lead is Since it can be joined to the substrate, the mounting strength can be improved. In particular, when a semiconductor device is mounted on a miniaturized mobile phone in recent years, its use becomes severe, and stress due to bending or the like is applied to the mounting substrate, and even if stress is applied to the joint portion, the effect is eliminated. And the reliability of the secondary mounting can be improved.

【0027】[0027]

【発明の効果】本発明の半導体装置の実装構造および半
導体装置の実装方法は、半導体装置の底面に配置された
リード部の露出した底面部と外方の一側面とをハンダに
より実装基板に接合して実装する構造に加えて、底面に
露出した電気的に関係のない吊りリード部の末端部をも
実装補強部として実装基板に接合して実装する構造であ
るため、接合箇所が増加するため、飛躍的に実装強度を
向上させ、使用状況により印加される応力による影響を
解消し、二次実装の信頼性を向上させることができるも
のである。さらに、半導体装置の底面に電気的に関係の
ない吊りリード部の末端部が露出したタイプの半導体装
置であれば、リード部と基板との接合に加えて、露出し
た吊りリード部の末端部と基板とをも接合させることが
できるので、実装強度を向上させることができるもので
ある。
According to the semiconductor device mounting structure and the semiconductor device mounting method of the present invention, the exposed bottom surface of the lead portion disposed on the bottom surface of the semiconductor device and one outer side surface are joined to the mounting substrate by soldering. In addition to the structure to be mounted and mounted, the end of the electrically unrelated suspension lead exposed on the bottom surface is also bonded to the mounting board as a mounting reinforcement part and mounted, so the number of joints increases In addition, it is possible to remarkably improve the mounting strength, eliminate the influence of the applied stress depending on the use condition, and improve the reliability of the secondary mounting. Furthermore, in the case of a semiconductor device in which the end of the suspension lead portion that is not electrically related to the bottom surface of the semiconductor device is exposed, in addition to the joining of the lead portion and the substrate, the exposed end portion of the suspension lead portion Since it can be joined to the substrate, the mounting strength can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態の半導体装置の実装構造の
半導体装置を示す図
FIG. 1 is a view showing a semiconductor device having a mounting structure of a semiconductor device according to an embodiment of the present invention;

【図2】本発明の一実施形態の半導体装置の実装構造の
半導体装置を示す図
FIG. 2 is a view showing a semiconductor device having a semiconductor device mounting structure according to an embodiment of the present invention;

【図3】本発明の一実施形態の半導体装置の実装構造を
示す断面図
FIG. 3 is a sectional view showing a mounting structure of the semiconductor device according to the embodiment of the present invention;

【図4】本発明の一実施形態の半導体装置の実装構造の
半導体装置を示す図
FIG. 4 is a diagram showing a semiconductor device having a semiconductor device mounting structure according to an embodiment of the present invention;

【図5】従来の半導体装置の実装構造の半導体装置を示
す図
FIG. 5 is a diagram showing a semiconductor device having a conventional semiconductor device mounting structure.

【図6】従来の半導体装置の実装構造の半導体装置を示
す図
FIG. 6 is a diagram showing a semiconductor device having a conventional semiconductor device mounting structure.

【図7】従来の半導体装置の実装構造を示す図FIG. 7 is a diagram showing a mounting structure of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 封止樹脂 2 リード部 3 吊りリード部 3a 末端部 4 半導体素子 5 ダイパッド部 6 金属細線 7 実装基板 8 ハンダ DESCRIPTION OF SYMBOLS 1 Sealing resin 2 Lead part 3 Suspended lead part 3a Terminal part 4 Semiconductor element 5 Die pad part 6 Thin metal wire 7 Mounting board 8 Solder

フロントページの続き (72)発明者 老田 成志 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 舩越 正司 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 (72)発明者 谷 昇 大阪府高槻市幸町1番1号 松下電子工業 株式会社内 Fターム(参考) 5F047 AA11 AB00 5F067 BB00 BD00 Continued on the front page (72) Inventor Narishi Ota 1-1, Sachimachi, Takatsuki-shi, Osaka, Japan Matsushita Electronics Corporation (72) Inventor Masashi Funakoshi 1-1, Sachimachi, Takatsuki-shi, Osaka, Matsushita Electronics Corporation (72) Inventor Noboru Tani 1-1 Fukumachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation F term (reference) 5F047 AA11 AB00 5F067 BB00 BD00

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 その底面に電気的接続用のリード部と、
封止された半導体素子を支持したダイパッド部を支持し
ている吊リードの末端部とが配列された半導体装置を実
装基板に実装した半導体装置の実装構造であって、少な
くとも前記リード部の底面が接合材で実装されるととも
に、実装補強部として前記半導体装置の底面から露出し
た前記吊りリード部の末端部が接合材で実装されている
ことを特徴とする半導体装置の実装構造。
A lead portion for electrical connection on a bottom surface thereof;
A mounting structure of a semiconductor device in which a semiconductor device in which a terminal portion of a suspension lead supporting a die pad portion supporting a sealed semiconductor element is arranged is mounted on a mounting substrate, at least a bottom surface of the lead portion is provided. A mounting structure of a semiconductor device, wherein the mounting portion is mounted with a bonding material, and an end of the suspension lead portion exposed from a bottom surface of the semiconductor device as a mounting reinforcing portion is mounted with a bonding material.
【請求項2】 半導体素子と、前記半導体素子を支持し
たダイパッド部と、前記ダイパッド部をその先端部で支
持した吊りリード部と、前記ダイパッド部に先端部が配
置されたリード部と、前記リード部と前記半導体素子と
を電気的に接続した接続手段と、前記吊りリード部の末
端部および前記リード部の一側面と底面とを露出させ、
前記半導体素子、前記ダイパッド部、前記接続手段の外
囲を封止した封止樹脂とよりなる半導体装置を実装基板
に実装した半導体装置の実装構造であって、前記リード
部の一側面と底面とが接合材で実装されるとともに、実
装補強部として前記半導体装置の底面の端部から露出し
た吊りリード部の末端部が接合材で実装されていること
を特徴とする半導体装置の実装構造。
2. A semiconductor device, a die pad portion supporting the semiconductor device, a suspension lead portion supporting the die pad portion at a distal end thereof, a lead portion having a distal end portion disposed on the die pad portion, and the lead. Connecting means for electrically connecting the portion and the semiconductor element, and exposing the end portion of the suspension lead portion and one side surface and the bottom surface of the lead portion,
The semiconductor device, the die pad portion, a mounting structure of a semiconductor device in which a semiconductor device made of a sealing resin that seals the outer periphery of the connection means is mounted on a mounting substrate, and one side surface and a bottom surface of the lead portion. Is mounted with a bonding material, and a terminal of a suspension lead portion exposed from an end of a bottom surface of the semiconductor device as a mounting reinforcing portion is mounted with a bonding material.
【請求項3】 接合材はハンダであることを特徴とする
請求項1または請求項2に記載の半導体装置の実装構
造。
3. The mounting structure of a semiconductor device according to claim 1, wherein the bonding material is solder.
【請求項4】 実装基板はプリント基板であることを特
徴とする請求項1または請求項2に記載の半導体装置の
実装構造。
4. The mounting structure for a semiconductor device according to claim 1, wherein the mounting substrate is a printed circuit board.
【請求項5】 半導体素子と、前記半導体素子を支持し
たダイパッド部と、前記ダイパッド部をその先端部で支
持した吊りリード部と、前記ダイパッド部に先端部が配
置されたリード部と、前記リード部と前記半導体素子と
を電気的に接続した接続手段と、前記吊りリード部の末
端部および前記リード部の一側面と底面とを露出させ、
前記半導体素子、前記ダイパッド部、前記接続手段の外
囲を封止した封止樹脂とよりなる半導体装置を実装基板
に実装するに際し、前記半導体装置の前記リード部の一
側面と底面とを接合材で実装するとともに、実装補強部
として前記半導体装置の底面の端部から露出した吊りリ
ード部の末端部をも前記接合材で実装することを特徴と
する半導体装置の実装方法。
5. A semiconductor device, a die pad portion supporting the semiconductor device, a suspension lead portion supporting the die pad portion at a tip end thereof, a lead portion having a tip end portion arranged on the die pad portion, and the lead Connecting means for electrically connecting the portion and the semiconductor element, and exposing the end portion of the suspension lead portion and one side surface and the bottom surface of the lead portion,
When mounting a semiconductor device comprising the semiconductor element, the die pad portion, and a sealing resin that seals an outer periphery of the connection means on a mounting board, one side surface and a bottom surface of the lead portion of the semiconductor device are bonded with a bonding material. And mounting at an end of a suspension lead portion exposed from an end of a bottom surface of the semiconductor device as a mounting reinforcing portion with the bonding material.
【請求項6】 接合材はハンダを用いることを特徴とす
る請求項5に記載の半導体装置の実装方法。
6. The method according to claim 5, wherein solder is used as the bonding material.
【請求項7】 プリント基板に半導体装置を実装するこ
とを特徴とする請求項5に記載の半導体装置の実装方
法。
7. The method for mounting a semiconductor device according to claim 5, wherein the semiconductor device is mounted on a printed circuit board.
JP2000066527A 2000-03-10 2000-03-10 Structure and method for mounting semiconductor device Pending JP2001257217A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000066527A JP2001257217A (en) 2000-03-10 2000-03-10 Structure and method for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000066527A JP2001257217A (en) 2000-03-10 2000-03-10 Structure and method for mounting semiconductor device

Publications (1)

Publication Number Publication Date
JP2001257217A true JP2001257217A (en) 2001-09-21

Family

ID=18585879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000066527A Pending JP2001257217A (en) 2000-03-10 2000-03-10 Structure and method for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JP2001257217A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014801A (en) * 2002-06-06 2004-01-15 Renesas Technology Corp Semiconductor device and its manufacturing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004014801A (en) * 2002-06-06 2004-01-15 Renesas Technology Corp Semiconductor device and its manufacturing device
KR100961602B1 (en) 2002-06-06 2010-06-04 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device and method of manufacturing the same

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