JP2001257139A - 半導体基板とその作製方法 - Google Patents

半導体基板とその作製方法

Info

Publication number
JP2001257139A
JP2001257139A JP2001000633A JP2001000633A JP2001257139A JP 2001257139 A JP2001257139 A JP 2001257139A JP 2001000633 A JP2001000633 A JP 2001000633A JP 2001000633 A JP2001000633 A JP 2001000633A JP 2001257139 A JP2001257139 A JP 2001257139A
Authority
JP
Japan
Prior art keywords
substrate
layer
semiconductor
mark
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001000633A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001257139A5 (https=
Inventor
Kiyobumi Sakaguchi
清文 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2001000633A priority Critical patent/JP2001257139A/ja
Publication of JP2001257139A publication Critical patent/JP2001257139A/ja
Publication of JP2001257139A5 publication Critical patent/JP2001257139A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
    • H10W46/103—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols alphanumeric information, e.g. words, letters or serial numbers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/201—Marks applied to devices, e.g. for alignment or identification located on the periphery of wafers, e.g. orientation notches or lot numbers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/401—Marks applied to devices, e.g. for alignment or identification for identification or tracking

Landscapes

  • Element Separation (AREA)
JP2001000633A 2000-01-07 2001-01-05 半導体基板とその作製方法 Pending JP2001257139A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001000633A JP2001257139A (ja) 2000-01-07 2001-01-05 半導体基板とその作製方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000-1478 2000-01-07
JP2000001478 2000-01-07
JP2001000633A JP2001257139A (ja) 2000-01-07 2001-01-05 半導体基板とその作製方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006266518A Division JP2007036279A (ja) 2000-01-07 2006-09-29 半導体基板の作製方法

Publications (2)

Publication Number Publication Date
JP2001257139A true JP2001257139A (ja) 2001-09-21
JP2001257139A5 JP2001257139A5 (https=) 2006-01-12

Family

ID=26583230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001000633A Pending JP2001257139A (ja) 2000-01-07 2001-01-05 半導体基板とその作製方法

Country Status (1)

Country Link
JP (1) JP2001257139A (https=)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005079109A (ja) * 2003-08-29 2005-03-24 Sumitomo Mitsubishi Silicon Corp 貼合せｓｏｉウェーハの製造方法及び該方法により製造された貼合せｓｏｉウェーハ
JP2007243038A (ja) * 2006-03-10 2007-09-20 Sumco Corp 貼り合わせウェーハ及びその製造方法
US7390702B2 (en) 2004-09-30 2008-06-24 Oki Electric Industry Co., Ltd. Method for manufacturing semiconductor device
JP2010153811A (ja) * 2008-11-28 2010-07-08 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US7781309B2 (en) 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
JP2011029355A (ja) * 2009-07-24 2011-02-10 Sumco Corp レーザマーク付き半導体ウェーハの製造方法
JP2011077506A (ja) * 2009-09-04 2011-04-14 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法およびｓｏｉ基板
JP2014138057A (ja) * 2013-01-16 2014-07-28 Hitachi Metals Ltd 窒化物半導体ウェハのマーキング方法および識別符号付き窒化物半導体ウェハ
JP2014192233A (ja) * 2013-03-26 2014-10-06 Sumitomo Electric Ind Ltd 半導体装置の製造方法及び半導体基板の製造方法
JP2016139642A (ja) * 2015-01-26 2016-08-04 株式会社東芝 半導体装置
JP2019087617A (ja) * 2017-11-06 2019-06-06 信越半導体株式会社 薄膜ｓｏｉ層を有するｓｏｉウェーハの製造方法
JP2021034670A (ja) * 2019-08-29 2021-03-01 富士電機株式会社 炭化珪素エピタキシャル基板および炭化珪素エピタキシャル基板の製造方法
JPWO2021199585A1 (https=) * 2020-04-02 2021-10-07
WO2025094811A1 (ja) * 2023-11-02 2025-05-08 住友電気工業株式会社 半導体基板およびエピタキシャル基板

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005079109A (ja) * 2003-08-29 2005-03-24 Sumitomo Mitsubishi Silicon Corp 貼合せｓｏｉウェーハの製造方法及び該方法により製造された貼合せｓｏｉウェーハ
US7390702B2 (en) 2004-09-30 2008-06-24 Oki Electric Industry Co., Ltd. Method for manufacturing semiconductor device
US7781309B2 (en) 2005-12-22 2010-08-24 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
US7855129B2 (en) 2005-12-22 2010-12-21 Sumco Corporation Method for manufacturing direct bonded SOI wafer and direct bonded SOI wafer manufactured by the method
JP2007243038A (ja) * 2006-03-10 2007-09-20 Sumco Corp 貼り合わせウェーハ及びその製造方法
JP2010153811A (ja) * 2008-11-28 2010-07-08 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2011029355A (ja) * 2009-07-24 2011-02-10 Sumco Corp レーザマーク付き半導体ウェーハの製造方法
JP2011077506A (ja) * 2009-09-04 2011-04-14 Semiconductor Energy Lab Co Ltd Ｓｏｉ基板の作製方法およびｓｏｉ基板
JP2014138057A (ja) * 2013-01-16 2014-07-28 Hitachi Metals Ltd 窒化物半導体ウェハのマーキング方法および識別符号付き窒化物半導体ウェハ
JP2014192233A (ja) * 2013-03-26 2014-10-06 Sumitomo Electric Ind Ltd 半導体装置の製造方法及び半導体基板の製造方法
JP2016139642A (ja) * 2015-01-26 2016-08-04 株式会社東芝 半導体装置
JP2019087617A (ja) * 2017-11-06 2019-06-06 信越半導体株式会社 薄膜ｓｏｉ層を有するｓｏｉウェーハの製造方法
JP2021034670A (ja) * 2019-08-29 2021-03-01 富士電機株式会社 炭化珪素エピタキシャル基板および炭化珪素エピタキシャル基板の製造方法
JP7467843B2 (ja) 2019-08-29 2024-04-16 富士電機株式会社 炭化珪素エピタキシャル基板および炭化珪素エピタキシャル基板の製造方法
JPWO2021199585A1 (https=) * 2020-04-02 2021-10-07
JP7354420B2 (ja) 2020-04-02 2023-10-02 東京エレクトロン株式会社 基板処理方法及び基板処理装置
WO2025094811A1 (ja) * 2023-11-02 2025-05-08 住友電気工業株式会社 半導体基板およびエピタキシャル基板

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