JP2001255559A - Method of manufacturing electro-optic device and electro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and efficiently manufacture an electro-optic device in which single crystal silicon is used as the semiconductor layer of a switching element in a driving circuit region and polysilicon is used as the semiconductor layer of a switching element in a display pixel region and to provide an electro-optic device with high quality. SOLUTION: In the method of manufacturing a TFT array substrate of a liquid crystal device, a single crystal silicon film 210 is formed on a substrate 110, and while a mask 211 is formed on the single crystal silicon film corresponding to the driving circuit region, silicon ions are injected into the single crystal silicon film corresponding to the display pixel region and heat treated. Thereby, in the display pixel region the single crystal silicon film 210c with injected silicon ions is converted into polysilicon to form a polysilicon film 210d. The single crystal silicon film 210 in the driving circuit region becomes a single crystal silicon film 210e with the grown crystal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing an electro-optical device for simultaneously forming a display pixel and a drive circuit on a substrate, and to an electro-optical device. In particular, the present invention relates to a method of manufacturing an electro-optical device and a method of manufacturing an electro-optical device having a structure in which a polysilicon layer is used as a semiconductor layer of a switching element of a display pixel and a single crystal silicon layer is used as a semiconductor layer of a switching element of a driver circuit.

[0002]

2. Description of the Related Art In an electro-optical device, for example, a liquid crystal device, a structure in which a display pixel and a driving circuit are simultaneously formed on the same substrate is used. In such a structure,
While the driving speed of the switching element arranged in the display pixel may be relatively low, the driving of the switching element in the drive circuit requires a high-speed response. For this reason, Japanese Patent Application Laid-Open No. 5-134272 discloses a technique in which single-crystal silicon is used as a semiconductor layer of a switching element of a driving circuit and polysilicon is used as a semiconductor layer of a switching element of a display pixel. As a method for efficiently forming such different semiconductor layers on the same substrate, Japanese Patent Application Laid-Open No. 5-134272 discloses a method of forming a semiconductor layer by growing a silicon film with a silicon nitride film as a nucleus. It is determined whether the silicon film deposited by changing the size of the silicon nitride film to be formed is a polycrystalline silicon film or a single crystal silicon film.

[0003]

However, in the manufacturing method described in the above-mentioned publication, it is difficult to obtain a silicon film having good surface smoothness, and a flattening process such as CMP is required. Further, it is difficult to grow a silicon film from a nucleus, and it is difficult to put the silicon film to practical use. When a silicon nitride film is used as a nucleus, particularly when the channel region is formed of a thin single crystal silicon film, there is a problem that a channel depletion layer is terminated on the side of the nitride film to increase variation in threshold voltage of the device.

According to the present invention, a single crystal silicon is used as a semiconductor layer of a switching element in a drive circuit area by a manufacturing method different from the manufacturing method described in Japanese Patent Application Laid-Open No. 5-134272, and a semiconductor of a switching element in a display pixel area is used. It is an object of the present invention to easily and efficiently manufacture an electro-optical device using polysilicon as a layer and to provide a high-quality electro-optical device.

[0005]

In order to solve the above-mentioned problems, a method for manufacturing an electro-optical device according to the present invention is directed to a method for manufacturing a display pixel, comprising a substrate and a switching element having at least a semiconductor layer made of a polysilicon film. A method of manufacturing an electro-optical device in which a driving circuit in which a switching element having a semiconductor layer made of a single crystal silicon film for driving at least the display pixel is disposed, wherein (a) a single crystal silicon film is formed on the substrate Forming a mask on the single crystal silicon film corresponding to the drive circuit; and (c) implanting silicon ions into the single crystal silicon film through the mask to form a non-monocrystalline silicon film. Forming a crystallized region, (d) converting the region into which the silicon ions have been implanted into polysilicon, and (e) a region into which the silicon ions have been implanted. By patterning the area where the silicon ion is not implanted, characterized by comprising a step of forming a semiconductor layer and each semiconductor layer made of the polysilicon film made of the single crystal silicon film.

According to such a configuration of the present invention, there is an effect that a silicon film having a different film quality such as a polysilicon film and a single crystal silicon film having good film quality can be easily formed on the same substrate. That is, in the technology disclosed in the above-mentioned publication, since the silicon layer having a different film quality is obtained by changing the size of the nucleus, the control of the vertical and horizontal growth when growing from the nucleus is performed. It is difficult to control the thickness and size of the silicon layer,
Further, it was difficult to control the size of the nucleus to make the film quality different. On the other hand, in the present invention, since the single-crystal silicon film is first formed on the entire surface of the substrate, the in-plane thickness uniformity is good. Further, in the present invention, as a method of converting a single crystal silicon film into a polysilicon, a method is employed in which silicon ions are implanted into a single crystal silicon film, and the single crystal silicon film is converted into polysilicon by heating or laser annealing. Therefore, whether a polysilicon film or a single crystal silicon film is formed is determined depending on whether or not silicon ions are implanted, so that a silicon film having a different film quality can be easily formed on the same substrate.

Further, in the step (d), the region into which the silicon ions have been implanted is turned into polysilicon by heat treatment. In this manner, by performing the heat treatment, polysilicon can be formed.
Heating for forming polysilicon may be performed in a range of about 600 to 700 ° C.

Further, after the step (c) and before the step (d), the method further comprises a step (f) of removing the mask. In the step (d), the mask is removed by the heat treatment. The non-single-crystal silicon film in the uncovered region is characterized by being crystal-grown. With such a structure, the process of forming the silicon film in the display pixel region into polysilicon by heat treatment and the process of forming the single crystal silicon film in the drive circuit region can be performed at the same time.

The step (a) includes (g) a step of bonding a single crystal silicon substrate into which hydrogen ions have been implanted on the substrate; and (h) a step of bonding the bonded substrate and the single crystal silicon substrate. Forming the single crystal silicon film on the substrate by heat-treating the substrate. As described above, SOI (Silicon) in which hydrogen ions are implanted into a single crystal silicon substrate is used.
A single crystal silicon film can be formed over a substrate using an on insulator (Insulator) substrate, and a single crystal silicon film with uniform thickness and excellent flatness can be formed in a substrate surface.

[0010] The method may further include (i) forming an oxide film on the surface of the single crystal silicon film after the step (a) and before the step (c).
According to such a configuration, since the oxide film is formed on the surface of the single crystal silicon film before the implantation of the silicon ions, the surface of the single crystal silicon film is protected by the oxide film,
This has the effect of preventing the surface of the silicon film from being roughened by the implantation of silicon ions. As a result, a semiconductor layer made of polysilicon having good surface flatness can be obtained, and a high-quality switching element can be obtained.

Further, the step (i) is performed after the step (b) and before the step (c), and the oxide film is formed by oxidizing a surface of the single crystal silicon film. It is characterized by. With such a structure, the surface oxide film is formed after the mask is formed. Therefore, the mask serves as a mask for forming the oxide film, and the oxide film is efficiently formed only on the surface of the single crystal silicon film corresponding to the display pixel region. Can be formed. Further, since the oxide film is formed by oxidizing the surface of the single crystal silicon film, the thickness of the silicon film in the display pixel is smaller than the thickness of the silicon film in the drive circuit. As a result, a semiconductor layer made of polysilicon having a small thickness is formed in the display pixel, and a semiconductor layer made of single crystal silicon having a large thickness is formed in the drive circuit. In the display pixel, the thickness of the semiconductor layer is small, for example, 30 to 70 nm, preferably 30 to 70 nm.
When light is incident on the electro-optical device by setting the thickness to 50 nm, light leakage in the channel region of the semiconductor layer due to the incident light is reduced, so that the switching element including the semiconductor malfunctions. I will not do it. On the other hand, in the drive circuit, the thickness of the semiconductor layer is increased, for example, to a thickness of 80 to 200 nm,
The drain withstand voltage can be improved. In particular, in the case of using an SOI substrate, since the element capability is extremely high, it is desirable to increase the thickness of the semiconductor layer in order to prevent a decrease in the element breakdown voltage due to the occurrence of parasitic bipolar and to reduce the contact resistance. For example, 50-200n
m, more preferably 100 to 160 nm.

Further, the method further comprises (j) a step of removing the oxide film before the step (d).
With such a structure, the oxide film is removed before the silicon film is converted into polysilicon. Therefore, it is possible to prevent the surface of the silicon film from being roughened by hydrofluoric acid used for removing the oxide film. it can. Here, there are two possible timings for removing the oxide film: after the polysilicon is formed and before the polysilicon is formed. In the case where the oxide film is removed after the formation of the polysilicon, the grain boundary of the polysilicon film is removed by the etchant used for removing the oxide film, and the surface of the polysilicon film becomes rough.
On the other hand, when the oxide film is removed before the polysilicon is formed, the surface of the single crystal silicon film is not roughened by the etching solution used for removing the oxide film. Therefore, it is desirable that the oxide film be removed before the polysilicon conversion step.

The mask is made of a nitride film. With such a structure, the surface of the silicon film can be prevented from being roughened by the etchant used for removing the mask. As an etching solution used for removing a nitride film, for example, a silicon nitride film, there is hot phosphoric acid, which does not roughen the surface of the silicon film.
On the other hand, a resist film made of an organic film can be used as a mask, but when a resist film is used,
The etchant used for removing the resist film tends to roughen the surface of the silicon film. Therefore, it is desirable to use a nitride film as a mask.

An electro-optical device according to the present invention is manufactured by the above-described method of manufacturing an electro-optical device. According to such a configuration, the semiconductor layer of the switching element arranged in the display pixel region is formed of polysilicon,
The semiconductor layer of the switching element arranged in the drive circuit region is formed from single crystal silicon. Accordingly, the lifetime of carriers accumulated in the channel region of the semiconductor layer can be shortened in the display pixel element region, and the driving capability can be maintained high in the drive circuit region. Further, since the thickness of the semiconductor layer is high in each of the display pixel region and the drive circuit region, a plurality of switching elements having stable characteristics can be obtained in the region, and a high-quality electro-optical device can be obtained. Can be.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(Electro-Optical Device in First Embodiment) The structure of a liquid crystal device as an electro-optical device in the first embodiment will be described with reference to FIGS. FIG.
FIG. 3 is a diagram illustrating various elements, equivalent circuits such as wirings, and a drive circuit region in a plurality of pixels formed in a matrix that constitute display pixels of a liquid crystal device. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a data line, a scanning line, a pixel electrode, a light-shielding film, and the like in a display pixel are formed, and FIG. FIG. 3A is a cross-sectional view of the drive circuit region along the line A ′. In each of the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

In FIG. 1, a liquid crystal device 200 includes a display pixel region in which display pixels having scanning lines 3a and data lines 6a intersecting with each other are arranged, and drive signals are applied to these scanning lines 3a and data lines 6a. It is composed of a driving circuit area in which driving circuits such as a scanning line driving circuit 104 and a data line driving circuit 101 for supplying power are arranged.

The display pixel area includes a capacitor line 3b and a scanning line 3a which are arranged in parallel, a data line 6a which intersects with the scanning line 3a, and an intersection of the scanning line 3a and the data line 6a. Pixel electrodes 9a arranged in a matrix
And a thin film transistor (hereinafter, referred to as TFT) 30 as a first switching element for controlling the pixel electrode 9a. Data line 6 to which an image signal is supplied
The source of the TFT 30 is electrically connected to a, and the gate of the TFT 30 is electrically connected to the scanning line 3a to which a scanning signal is supplied. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30 serving as a switching element for a predetermined period, the image signal S1, supplied from the data line 6a,
.., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are held for a certain period between the counter electrodes (described later) formed on the counter substrate (described later). .

On the other hand, the driving circuit area includes the scanning line driving circuit 1.
04, data line driving circuit 101, sampling circuit 30
1. It comprises a precharge circuit 201. The scanning line driving circuit 104 supplies the scanning signals G1, G2,..., Gm to the scanning line 3a at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY, its inverted clock, and the like.
Are applied in a pulse-wise line-sequential manner. Data line drive circuit 10
Reference numeral 1 denotes a data line 6a based on a power supply supplied from an external control circuit, a reference clock CLX, an inverted clock thereof, and the like, in accordance with the timing at which the scanning line driving circuit 104 applies the scanning signals G1, G2,. Transfer signal X from the shift register as a sampling circuit drive signal every time
, Xn are supplied to the sampling circuit 301 at a predetermined timing via the sampling circuit drive signal line 306. The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6a.
, And a precharge circuit drive signal line 206 is connected to the gate electrode of the TFT 202.

The driving circuit TFT serving as the second switching element disposed in the driving circuit region is formed on the same substrate and in the same process as the TFT 30 disposed in the display pixel region.

As will be described later, the liquid crystal device has a counter substrate and a TFT.
A liquid crystal layer is sandwiched between the array substrate and
The TFT array substrate is configured as follows. That is, as shown in FIG. 2, in the TFT array substrate 10,
A plurality of transparent pixel electrodes 9a are provided in a matrix on the glass substrate 60, and data lines 6a, scanning lines 3a, and capacitance lines 3b are provided along respective vertical and horizontal boundaries of the pixel electrodes 9a. The data line 6a is formed in a shape extending in the vertical direction.
Is electrically connected to a later-described source region in the semiconductor layer 1a made of polysilicon (a region surrounded by a wide dotted line). A part of the pixel electrode 9a (a region surrounded by a narrow dotted line 9a ') is
Is electrically connected to a drain region of the semiconductor layer 1a, which will be described later. In addition, the scanning line 3a is arranged so that a part thereof faces the channel region 1a '(the region where the slanting line is inclined downward) in the semiconductor layer 1a.
Function as a gate electrode. The capacitance line 3b has a main line portion extending linearly substantially in parallel along the scanning line 3a,
It has a protruding portion that protrudes along the data line 6a from a location that intersects the data line 6a, and a capacitor electrode 1f that is a part of the semiconductor layer 1 is disposed substantially corresponding to the protruding portion. The first light-shielding film 11a is provided at a position covering the TFT including the channel region of the semiconductor layer 1a in the display pixel region as viewed from the side of the TFT array substrate, and further opposes the main line of the capacitor line 3b. It has a main line portion extending linearly along the scanning line 3a, and a protruding portion protruding from an intersection with the data line 6a toward an adjacent step side (ie, downward in the drawing) along the data line 6a. The tip of the downward protruding portion in each stage (pixel row) of the first light-shielding film 11a overlaps the tip of the upward protruding portion of the capacitor line 3b in the next stage below the data line 6a. A contact hole 13 for electrically connecting the first light-shielding film 11a and the capacitance line 3b to each other is provided in the overlapping portion. That is, in the present embodiment, the first light shielding film 11a is
3 is electrically connected to the preceding or succeeding capacitive line 3b. In addition, the projecting portion of the capacitance line 3b and the capacitance electrode 1f
Means that a storage capacitor is formed using a gate insulating film 2 described later as a dielectric layer.

As shown in FIG. 3, the liquid crystal device 200 includes a liquid crystal layer 50 between the counter substrate 20 and the TFT array substrate 10.
Is configured.

In the TFT array substrate 10, in the display pixel region, a light-shielding film 11a is disposed on, for example, a quartz substrate 110, and a base film 12 made of silicon oxide is disposed so as to cover the light-shielding film 11a. On the base film 12,
A semiconductor layer 1a made of polysilicon is arranged.
A part of the semiconductor layer 1a is a capacitor electrode 1f, and has a semiconductor layer having an LDD structure connected to the capacitor electrode 1f. This LDD (lightly doped
The semiconductor layer having a drain structure is a channel region 1
A low-concentration source region 1b and a low-concentration drain region 1c are arranged on both sides of a ′, and a high-concentration source region 1d and a high-concentration drain region 1e are arranged on both sides of these regions. .

On the semiconductor layer 1a, a gate insulating film 2 partially formed of a silicon oxide film which also functions as a dielectric film for forming a storage capacitor is formed. On the gate insulating film 2, a scanning line 3a and a capacitance line 3b made of polysilicon are formed. Part of the scanning line 3a also serves as a gate electrode, and the gate electrode is arranged corresponding to the channel region 1a '. A first interlayer insulating film 4 is formed on the semiconductor layer 1a including the scanning lines 3a and the capacitance lines 3b.
On the interlayer insulating film 4, a data line 6a made of, for example, aluminum is formed. The data line 6a is electrically connected to the high-concentration source region 1d via a contact hole 5 formed in the first interlayer insulating film 4. further,
On the first interlayer insulating film 4 including the data line 6a, a second interlayer insulating film 7 is formed. On the second interlayer insulating film 7,
Pixel electrode 9a made of ITO (Indium Tin Oxide) film
The pixel electrode 9a is electrically connected to the high-concentration drain region 1e via a contact hole 8 formed in the first interlayer insulating film 4 and the second interlayer insulating film 7. Then, on the second interlayer insulating film 7 including the pixel electrode 9a, an alignment film 16 formed by performing an alignment process on a polyimide film is disposed.

In the drive circuit region of the TFT array substrate 10, a complementary transistor structure or the like is employed. As shown in FIG. 3, the complementary transistor structure includes an N-channel TFT 407 and a P-channel TFT 4
08. As shown in FIG.
A semiconductor layer 401 corresponding to the N-channel type and a P-channel type semiconductor layer 402 are disposed on the base layer 12 disposed on the substrate 0, and the gate insulating film 2 is disposed so as to cover these. The semiconductor layers 401 and 402 are made of single crystal silicon. The semiconductor layer 401 includes a source region 401b and a drain region 40 on both sides of the channel region 401a.
1c is disposed, and the semiconductor 402 is
The structure is such that a source region 402b and a drain region 402c are arranged on both sides of a. On the gate insulating film 2, gate electrodes 403 and 404 are arranged at positions corresponding to the respective channel regions 401a and 402a of the semiconductor layers 401 and 402. Further, the gate electrode 4
03 and 404, a first interlayer insulating film 4 is disposed, and on the first interlayer insulating film 4, source electrodes 405a, 406a,
Drain electrodes 405b and 406b are arranged. The source electrode 405a and the drain electrode 405b are respectively connected to the source region 401b, the drain region 401c and the first region.
Contact holes 420a, 4a formed in the interlayer insulating film
It is electrically connected via the connection 20b. In addition, the source electrode 406a and the drain electrode 406b are formed in contact holes 421a and 421b formed in the source region 402b and the drain region 402c and the first interlayer insulating film, respectively.
Are electrically connected via Further, the source electrode 4
05a, 406a and drain electrodes 405b, 406b
The second interlayer insulating film 7 and the alignment film 16 are sequentially laminated on the first interlayer insulating film 4 including.

On the other hand, the opposing substrate 20 includes, for example, a light-shielding film 23 formed in a matrix on a glass substrate 120 and an opposing electrode 2 made of an ITO film formed sequentially over the light-shielding film 23.
1. An alignment film 22 formed by subjecting a polyimide film to an alignment treatment. In FIG. 3, only the alignment film 16 is formed in the drive circuit region. However, it is sufficient that at least the counter electrode 21 and the alignment film are formed in the display pixel region. There are no particular restrictions on membranes.

Next, a method of manufacturing a TFT array substrate will be described with reference to FIGS. 4 to FIG.
FIG. 4 is a process diagram illustrating a cross-sectional view of each layer in a display pixel region and a drive circuit region on the FT array substrate side, corresponding to FIG. 3.

As shown in step (1) of FIG. 4, first, a quartz substrate 110 is prepared. Here, preferably, an inert gas atmosphere such as N ₂ (nitrogen) and about 850 to 1300 ° C.
More preferably, the TFT array substrate 1 is annealed at a high temperature of 1000 ° C.,
Pre-processing is performed so that distortion generated at 0 is reduced. That is, the quartz substrate 110 is preliminarily heat-treated at the same temperature or a higher temperature in accordance with the highest temperature of the manufacturing process.

A metal such as Ti, Cr, W, Ta, Mo and Pb or a metal alloy film such as metal silicide is deposited on the entire surface of the quartz substrate 110 thus treated by sputtering.
The light-shielding film 11 having a layer thickness of about 00 to 500 nm, here, about 200 nm is formed.

Next, as shown in step (2), a resist film 500 corresponding to the pattern of the first light-shielding film 11a (see FIG. 6) is formed by photolithography.

Next, as shown in step (3), the light shielding layer 11a is formed by etching the light shielding layer 11 via the resist film 500, and the resist film 500 is removed.

Next, as shown in step (4), TEOS (tetra-ethyl-ortho-silicate) is formed on the first light-shielding film 11a by, for example, normal pressure or reduced pressure CVD.
Gas, TEB (tetra ethyl boat rate) gas,
The base film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by using a TMOP (tetramethyl oxyphosphate) gas or the like. The layer thickness of the base film 12 is, for example, about 400 to 1200 nm. Here, the thickness is about 1100 nm.

Next, as shown in step (5), the base film 1
The surface of No. 2 is globally polished and flattened. As a method of planarization by polishing, for example, a CMP (chemical mechanical polishing) method can be used. Thereby, the base film 1
2 was about 600 nm.

Next, as shown in step (6), the substrate 11
And the single crystal silicon substrate 210a.

Single crystal silicon substrate 2 used for bonding
10a has a thickness of 600 μm, and its surface is previously oxidized to 50 to 800 nm, here about 200 nm, to form an oxide film 210b. This is because the single crystal silicon layer 210 and the oxide layer 2
This is because the interface of 10b is formed by thermal oxidation to secure an interface with good electrical characteristics. Further, the single crystal silicon substrate 21
At 0a, hydrogen ions (H ⁺ ) are, for example, at an acceleration voltage of 100
It is implanted at a keV and a dose of 10 × 10 ¹⁶ cm ⁻² , and the implantation depth is about 300 nm from the substrate surface. In the figure, of the single crystal silicon substrate 210a,
Hydrogen ions are implanted into a region below the dotted line.

In the bonding, the base film 1 on the substrate 110 is
2 and the oxide film 210b of the single-crystal silicon substrate 210a are bonded together. For the bonding step, for example, a method of directly bonding two substrates by heat treatment at 300 ° C. for 2 hours can be adopted.

Next, as shown in step (7), the oxide film 210b and the single-crystal silicon film 210 on the side of the bonded single-crystal silicon substrate 210a are left as they are.
Heat treatment for separating the single crystal silicon substrate 210a from the substrate 10 is performed. This separation phenomenon of the substrate occurs because hydrogen bonds introduced into the single-crystal silicon substrate break silicon bonds in a certain layer near the surface of the single-crystal silicon substrate. For example, the heat treatment can be performed by heating the two bonded substrates to 600 ° C. at a rate of 20 ° C./min. By this heat treatment, the bonded single crystal silicon substrate 210a is separated from the substrate 10, and a silicon oxide film 210b having a thickness of about 200 nm and a single crystal silicon film 210 having a thickness of about 70 nm are formed on the surface of the substrate 10. It is formed. Note that the single-crystal silicon film 210 bonded to the substrate 10 has a thickness of 50 nm to 3 nm by changing the acceleration voltage of hydrogen ion implantation performed on the single-crystal silicon substrate 210a described above.
It can be formed in any thickness up to 000 nm. Thereafter, the surface of the single crystal silicon film 210 is touch-polished and smoothed. The thickness of the single crystal silicon film is 5
It is preferably from 0 to 200 nm, and in this embodiment, 55
nm.

In the present embodiment, the uni-bond method of forming a single-crystal silicon film on a substrate is performed by using the Smart Cut method in which a single-crystal silicon substrate into which hydrogen ions have been implanted is separated by heat treatment after bonding.
A single crystal silicon film having high uniformity in film thickness over the entire surface of the substrate can be obtained.

In addition, as a method for obtaining a single-crystal silicon film, a single-crystal silicon substrate into which hydrogen ions are not implanted is bonded to the substrate, and after heat-bonding,
PACE (Plasma Assisted Chem)
silicon etching of the silicon layer 20 by an ionic etching method.
6 may be formed by etching to a thickness of about 0.05 to 0.8 μm. By the PACE process, a single-crystal silicon film having a thickness uniformity of, for example, 100 nm or less is obtained within 10%.

As another method for obtaining a single-crystal silicon film, an ELTRAN (Ep.TM.) is used in which an epitaxial silicon layer formed on porous silicon is transferred onto a bonded substrate by selective etching of the porous silicon layer.
It is also possible to use an axial layer transfer method and does not depend on a film formation method.

Next, after a silicon nitride film is formed to a thickness of 200 nm on the single crystal silicon film 210, as shown in step (8), a mask 211 made of the silicon nitride film remains only in the drive circuit region. As described above, the silicon nitride film formed in the display pixel region is removed by etching. Here, an organic film can be used as a mask in addition to an inorganic film such as a silicon nitride film. However, when an organic film is used as a mask, when the mask is removed, the resist is solidified by silicon implantation described later and peeled off. On the other hand, an inorganic film such as a silicon nitride film does not have the above-described problem, but an inorganic film is preferably used.

Next, as shown in step (8), the mask 2
Through step 11, silicon ions (Si +) are implanted at an acceleration voltage of 40 keV in an amount of 3 × 10 ¹⁵ cm ⁻² . As a result, in the display pixel region, a film 210c in a state in which silicon has been disconnected from each other is formed. On the other hand, in the drive circuit region, the single crystal silicon film 210 in which silicon ions have not been implanted remains.

Next, as shown in step (9), the mask 2
11 is stripped off with hot phosphoric acid. Thereafter, the substrate is heated in a nitrogen atmosphere at a temperature of 600 to 700 ° C., here, at a temperature of 640 ° C. for 6 hours to perform solid phase growth of the non-single-crystal silicon film. By this step, in the display pixel region, the non-single-crystal silicon film 210c is converted to polysilicon to form a polysilicon film 210d. On the other hand, the drive circuit region has a structure in which the single crystal silicon film 210e is formed. Here, laser annealing may be used as a means for forming polysilicon and solid phase growth.

Next, as shown in step (10) of FIG.
In the display pixel region, a semiconductor layer 1a having a predetermined pattern as shown in FIGS. 2 and 3, and a capacitor electrode 1f extending from the semiconductor layer 1a are formed by a photolithography step, an etching step, and the like. Semiconductor layers 401 and 402 are formed in the driver circuit region.

In the present embodiment, the silicon film is patterned after the implantation of silicon ions. However, it is also possible to implant silicon ions after patterning the silicon film and masking the drive circuit region.

Next, as shown in the step (11), the semiconductor layer 1a constituting the pixel switching TFT 30 in the display pixel region, the capacitor electrode 1f, the semiconductor layer 401 constituting the N-type TFT in the drive circuit region, and P Type TFT
Is thermally oxidized at a temperature of about 850 to 1300 ° C., preferably at a temperature of about 1000 ° C. for about 30 minutes to form a relatively thin thermally oxidized silicon film of about 30 nm. Further, a high-temperature silicon oxide film (HT) having a thickness of 30 to 50 nm is formed by a low pressure CVD method or the like.
O) A film is formed, and a gate insulating film 2 composed of two layers of a thermal silicon oxide film and an HTO film is formed. As a result, the thickness of the semiconductor layers 1a, 401, 402 and the first storage capacitor electrode 1f is about 40 nm, and the thickness of the gate insulating film 2 is about 6 nm.
It has a thickness of 0 to 80 nm.

Next, as shown in step (12), in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor layer 1a, the scanning line 3a (gate electrode) on the surface of the substrate 10 is formed.
A resist film 501 is formed in a portion corresponding to the above, and using this as a mask, a dopant of a group V element such as P,
Here, P ions are accelerated at an acceleration voltage of 70 keV, 3e14 /
Doping is performed at a dose of cm 2.

Next, as shown in step (13), the resist film 501 is removed, and the contact hole 13 reaching the light-shielding film 11a is formed in the base film 12 by dry etching such as reactive ion etching or reactive ion beam etching. Or by wet etching. On this occasion,
Opening the contact holes 13 and the like by anisotropic etching such as reactive ion etching or reactive ion beam etching has the advantage that the opening shape can be made almost the same as the mask shape. However, if the dry etching and the wet etching are performed in combination, the contact holes 13 and the like can be tapered, so that there is an advantage that disconnection during wiring connection can be prevented.

Next, as shown in step (14), the pressure
After the polysilicon film 3 is deposited to a thickness of about 350 nm by the VD method or the like, phosphorus (P) is thermally diffused to make the polysilicon film 3 conductive. Alternatively, P ions are added to the polysilicon film 3.
May be used. Thereby, the conductivity of the polysilicon film 3 can be increased.

Next, as shown in step (15), a scanning line 3a having a predetermined pattern as shown in FIG. 2 is formed by a photolithography step using a resist film, an etching step and the like.
Together with this, a capacitance line 3b is formed.

Next, as shown in step (16), a resist film 502 is formed on the entire surface of the substrate except for the semiconductor layer 402 to be a P-channel TFT in the drive circuit region. After that, using the resist film 502 and the gate electrode 404 as a mask, a dopant of a group III element such as B, here BF ₂ ion, is applied to the semiconductor layer 402 at an acceleration voltage of 90 keV,
Doping is performed at a dose of × 10 ¹⁵ cm ⁻² . Thus, a source region 402b and a drain region 402c corresponding to the P-channel TFT in the drive circuit region are formed. After doping, the resist film 502 is removed.

Next, as shown in a step (17), a resist film 503 is formed so as to cover the semiconductor layer 402 serving as a P-channel TFT in the drive circuit region. After that, using the resist film 503, the scanning line (gate electrode) 3a, and the capacitor line 3b as a mask, a P layer is formed on the semiconductor layer 401 and the semiconductor layer 1a.
Group V dopant such as P ions
Doping is performed at an acceleration voltage of 0 keV and a dose of 6 × 10 ¹² cm ⁻² . As a result, in the semiconductor layer 1a of the TFT in the display pixel region, a low-concentration source region 1b and a low-concentration drain region 1c are formed. In the drive circuit region, a source region 401 corresponding to the N-channel TFT is provided.
b and the drain region 401c are formed. After doping,
The resist film 503 is removed.

Subsequently, as shown in step (18), a resist film 504 having a shape wider than the gate electrode 3a and a shape covering the semiconductor layer 402 of the P-channel TFT in the drive circuit region is formed. I do. Thereafter, using the resist film 504 and the gate electrode 403 as a mask, the semiconductor layer 1a and the semiconductor layer 401 are doped with a dopant of a group V element such as P, here P ions, at an accelerating voltage of 70 keV and 4 × 10 ¹⁵ / cm ⁻² . Dope with a dose amount. As a result, a high-concentration source region 1d and a high-concentration drain region 1e are formed in the TFT in the display pixel region. Further, in the N-channel TFT in the drive circuit region, a source region 401b and a drain region 401c with further reduced resistance can be obtained. After doping, resist film 50
4 is removed.

Next, as shown in step (19), for example, normal or reduced pressure CVD, TEOS gas, or the like is used so as to cover the capacitance line 3b and the scanning line 3a together with the scanning line 3a in the pixel switching TFT 30. And NSG, PS
A first interlayer insulating film 4 made of a silicate glass film such as G, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The layer thickness of the first interlayer insulating film 4 is about 500 to
1500 nm is preferable, and 800 nm is more preferable.

Thereafter, an annealing process at about 850 ° C. is performed to activate the impurity ions doped into the semiconductor layer.
Perform for about 0 minutes.

Next, as shown in step (20), a contact hole 5 for the data line 6a is formed in the display pixel region, and a source electrode 405 is formed in the drive circuit region.
a, 406a and contact holes 420a, 421 corresponding to the drain electrodes 405b, 406b, respectively.
a, 420b, 421b are subjected to reactive ion etching,
The first interlayer insulating film 4 is formed by dry or wet etching such as reactive ion beam etching.

Next, as shown in step (21) of FIG.
On the first interlayer insulating film 4, a low-resistance metal such as Al or a metal silicide having a light-shielding property is formed by sputtering or the like.
About 100-700 nm in thickness, preferably about 3
Deposit to 50 nm.

Next, the metal film 6 is patterned by a photolithography step, an etching step, etc.
As shown in 2), the data line 6a and the source electrode 405
a, 406a and drain electrodes 405b, 406b are formed.

Next, as shown in step (23), the normal or reduced pressure CVD method is applied on the first interlayer insulating film 4 including the data lines 6a, the source electrodes 405a and 406a, and the drain electrodes 405b and 406b. Using TEOS gas etc.
A second interlayer insulating film 7 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the second interlayer insulating film 7 is preferably about 500 to 1500 nm, and more preferably 800 nm.
m is more preferred.

Next, as shown in step (24) of FIG.
In the pixel switching TFT 30, the pixel electrode 9a
A contact hole 8 for electrically connecting to the high-concentration drain region 1e is formed by dry etching such as reactive ion etching or reactive ion beam etching.

Next, as shown in step (25), a transparent conductive thin film 9 such as an ITO film is deposited on the second interlayer insulating film 7 by sputtering or the like to a thickness of about 50 to 200 nm. Then, as shown in step (26), a pixel electrode 9a is formed by a photolithography step, an etching step, or the like.

Subsequently, a coating liquid for a polyimide-based alignment film is applied on the pixel electrode 9a, and then a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 3) is formed.

On the other hand, as for the counter substrate 20 shown in FIG. 7, a glass substrate 120 and the like are first prepared. After sputtering metal chromium, for example, on this glass substrate 120,
After a photolithography step and an etching step, a matrix-shaped light-shielding film 23 is formed. The light shielding film 23
May be formed from a material such as resin black in which carbon or Ti is dispersed in a photoresist, in addition to a metal material such as Cr, Ni, or Al.

Thereafter, a transparent conductive thin film such as ITO is applied to the entire surface of the
The counter electrode 21 is formed by depositing it to a thickness of 0 nm. Furthermore, after applying a coating liquid for a polyimide-based alignment film to the entire surface of the counter electrode 21, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction, so that the alignment film 22 (see FIG. 3) is formed. It is formed.

Finally, as described above, the T
The FT array substrate 10 and the counter substrate 20 are bonded together by a sealing material (not shown) so that the alignment films 16 and 22 face each other, and a plurality of types of nematic liquid crystals are mixed in a space between the two substrates by vacuum suction or the like. The liquid crystal thus formed is sucked to form a liquid crystal layer 50 having a predetermined thickness.

(Electro-Optical Device in Second Embodiment) Next, a liquid crystal device in the second embodiment will be described.
The manufacturing method of the TFT array substrate is partially different from that of the first embodiment, and only different points will be described below, and the description of the same structure and manufacturing method will be omitted.

The method of manufacturing a TFT array substrate according to the second embodiment differs from the first embodiment in that silicon ions are implanted in a state where an oxide film is formed on the surface of a single crystal silicon film corresponding to a display pixel region. The difference will be described with reference to FIG.

First, FIG. 4A described in the first embodiment.
Through the same steps as the steps (7) to (7), a substrate on which the light shielding film 11a, the base film 12, the oxide film 210b, and the single crystal silicon film 210 are sequentially formed on the substrate 110 is formed. Here, the thickness of the single crystal silicon film was 67 nm.

Next, as shown in FIG. 12A, after a silicon nitride film is formed to a thickness of 200 nm on the single crystal silicon film 210, a mask 211 made of the silicon nitride film is formed only in the drive circuit region. The silicon nitride film formed in the display pixel region is removed by etching so as to remain.

Next, as shown in FIG. 12B, the surface of the single crystal silicon film 210 corresponding to the display pixel region is oxidized to form an oxide film 600 having a thickness of about 24 nm. At this time, the thickness of the single crystal silicon film is about 40 nm. After that, silicon ions are implanted into the single crystal silicon film 210 through the oxide film 600 and the mask 211 at an acceleration voltage of 60 keV and in an amount of 3 × 10 ¹⁵ cm ⁻² . Here, since the mask 211 is formed of a nitride film, silicon ions are not implanted into the single crystal silicon film 210. Further, silicon ions pass through oxide film 600 and are implanted into single crystal silicon film 210. Here, the oxide film 600 functions as a protective film for the film 210c,
The surface of the film 210c is prevented from being roughened by implantation of silicon ions. Thereafter, the nitride film 211 is removed with hot phosphoric acid. Further, the oxide film 600 is removed with hydrofluoric acid. Although a step of removing the oxide film may be provided after the polysilicon conversion step described below, it is desirable to provide a step of removing the oxide film before the polysilicon conversion. This is because, when the oxide film is peeled in the state of polysilicon, the surface of the polysilicon film is roughened by hydrofluoric acid used for the peeling.

Next, heating is performed in a nitrogen atmosphere at a temperature of 640 ° C. for 6 hours to perform solid phase growth of a non-single-crystal silicon film. By this step, in the display pixel area, the film 21
0c is converted to polysilicon to form a polysilicon film. On the other hand, the driving circuit region has a structure in which the single crystal silicon film 210 is formed. After that, the oxide film 600
Is removed by wet etching.

In the subsequent steps, FIG.
Steps (10) to (8) The same processes as those described in the step (26) are performed.

In the second embodiment, since silicon ions are implanted into a single crystal silicon film via oxide film 600,
Roughness of the surface of the single crystal silicon film can be prevented, and a high-quality semiconductor layer 1a can be obtained.

(Electro-Optical Device in Third Embodiment) Next, a liquid crystal device in the third embodiment will be described.
In the first embodiment, the thickness of the semiconductor layer 1a corresponding to the pixel switching TFT in the display pixel region is different from the thickness of the semiconductor layers 401 and 40 of the TFT in the drive circuit region.
The structure differs in that it is thinner than the film thickness of No. 2. The manufacturing method according to the third embodiment is partially different from the manufacturing method according to the first embodiment in order to make the thickness of the semiconductor layer disposed in each of the display pixel region and the drive circuit region different. Hereinafter, only the portions different from the manufacturing method of the first embodiment will be described, and the description of the same manufacturing method will be omitted.

In the method of manufacturing the TFT array substrate according to the third embodiment, the surface of the single-crystal silicon film corresponding to the display pixel region is oxidized to form a surface oxide film, so that the surface is formed in each of the display pixel region and the drive circuit region. This is different from the first embodiment in that the thickness of the semiconductor layer to be formed is different.
The removal of the surface oxide film is performed before the polysilicon conversion step, and will be described below with reference to FIG.

First, FIG. 4A described in the first embodiment
Through the same steps as the steps (7) to (7), a substrate on which the light shielding film 11a, the base film 12, the oxide film 210b, and the single crystal silicon film 210 are sequentially formed on the substrate 110 is formed.

Next, as shown in FIG. 13A, after a silicon nitride film is formed to a thickness of 200 nm on the single crystal silicon film 210, a mask 211 made of the silicon nitride film is formed only in the drive circuit region. The silicon nitride film formed in the display pixel region is removed by etching so as to remain.

Next, as shown in FIG. 13B, the surface of the single crystal silicon film 210 corresponding to the display pixel region is oxidized to form an oxide film 601 having a thickness of about 280 nm. Thereby, the remaining film thickness of silicon of the display pixel is 55 n
m.

Next, as shown in FIG. 13C, the oxide film 601 is removed by wet etching. Thus, a single-crystal silicon film 210 having a thickness of about 40 nm is formed in the display pixel region, and a single-crystal silicon film 210 having a thickness of approximately 100 nm is formed in the drive circuit region.
Thereafter, the single-crystal silicon film 210 is
Then, silicon ions are accelerated to 3 × 10 ¹⁵ at an acceleration voltage of 30 keV.
Inject in an amount of cm ^-2 . Here, since the mask 211 is formed of a nitride film, silicon ions are not implanted into the single crystal silicon film 210 in a region covered with the mask. Thereafter, the nitride film 211 is removed with hot phosphoric acid.

Next, heating is performed in a nitrogen atmosphere at a temperature of 640 ° C. for 6 hours to perform solid phase growth of a non-single-crystal silicon film. By this step, in the display pixel area, the film 21
0c is converted to polysilicon to form a 55-nm-thick polysilicon film. On the other hand, the driving circuit region has a structure in which the single crystal silicon film 210 is formed. In this embodiment, the polysilicon is formed by heating after the removal of the oxide film 601; however, the oxide film 601 may be removed after the formation of polysilicon by heating. However, if the oxide film 601 is removed after the formation of the polysilicon film, the surface of the polysilicon film may be roughened by an etching solution used for removing the oxide film. It is better to do.

In the subsequent steps, FIG.
Steps (10) to (8) The same processes as those described in the step (26) are performed.

Here, since light enters the display pixel region when the liquid crystal device is used, a semiconductor layer made of polysilicon is formed in order to prevent light leakage in the channel region of the semiconductor layer due to the incident light. Film thickness of 30 to 70
nm, more preferably 30 to 50 nm. On the other hand, TF arranged in the drive circuit area
In a semiconductor layer made of T single crystal silicon, the thickness of the semiconductor layer is set to 50 to 20 n in order to increase drain withstand voltage.
m, more preferably 100 to 160 nm. In particular, in the case of a manufacturing method using an SOI substrate, since the device capability of the peripheral circuit region is extremely high, the semiconductor device in the peripheral circuit region is prevented in order to prevent a decrease in device breakdown voltage due to the occurrence of parasitic bipolar and to reduce contact resistance. It is desirable to increase the thickness of the film. In the third embodiment, the thickness of the semiconductor layer made of polysilicon corresponding to the TFT arranged in the display pixel region is larger than the thickness of the semiconductor layer made of single crystal silicon corresponding to the TFT arranged in the drive circuit region. Since the structure is thin, the drain withstand voltage in the drive circuit region can be increased while solving the problem of light leakage in the display pixel region.

(Overall Configuration of Liquid Crystal Device) The overall configuration of each embodiment of the liquid crystal device configured as described above will be described with reference to FIGS. 9 and 10. FIG. FIG. 9 is a plan view of the TFT array substrate 10 together with the components formed thereon as viewed from the counter substrate 20, and FIG.
FIG. 10 is a sectional view taken along the line HH ′ of FIG.

In FIG. 9, a sealing material 52 is provided on the TFT array substrate 10 along its edge.
The data line driving circuit 10 is provided in a region outside the sealing material 52.
1 and the external circuit connection terminal 102 are the TFT array substrate 10
Are provided along one side of the scanning line driving circuit 104.
Are provided along two sides adjacent to this one side.
If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, the data line driving circuits 101 may be arranged on both sides along the side of the pixel display area. For example, the odd-numbered data lines 6a supply image signals from a data line driving circuit disposed along one side of the pixel display area, and the even-numbered data lines extend along the opposite side of the pixel display area. The image signal may be supplied from a data line driving circuit disposed in the same manner. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on one remaining side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the pixel display area are provided. A precharge circuit may be provided hidden under 53. In at least one of the corners of the opposing substrate 20,
A conductive material 106 for providing electrical continuity between the TFT array substrate 10 and the counter substrate 20 is provided. Then, as shown in FIG. 10, the opposite substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 9 is fixed to the TFT array substrate 10 by the sealing material 52.

(Configuration of Electronic Apparatus) As an example of an electronic apparatus using the above-described liquid crystal device, a configuration of a projection display device will be described with reference to FIG. In FIG. 11, a projection display device 1100 has three liquid crystal devices described above, and each of the liquid crystal devices 962R, 962G, and 9 for RGB.
FIG. 3 shows a schematic configuration diagram of an optical system of a projection type liquid crystal device used as 62B. The light source device 920 and the uniform illumination optical system 923 described above are adopted as the optical system of the projection display device of this example. Then, the projection display device converts the light beam W emitted from the uniform illumination optical system 923 into red (R), green (G),
Color separation optical system 9 as color separation means for separating into blue (B)
24, and three light valves 925R, 925G, and 925B as modulating means for modulating the color light fluxes R, G, and B.
And a color synthesizing prism 910 as color synthesizing means for re-synthesizing the modulated color light flux, and a projection lens unit 906 as a projection means for enlarging and projecting the synthesized light flux onto the surface of the projection surface 100. . Further, a light guide system 927 for guiding the blue light flux B to the corresponding light valve 925B is also provided.

The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931. The two lens plates 921 and 922 are arranged so as to be orthogonal to each other with the reflection mirror 931 interposed therebetween. Uniform illumination optical system 923
The two lens plates 921 and 922 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is transmitted to the first lens plate 92.
The light is split into a plurality of partial light beams by one rectangular lens.
Then, these partial light beams are divided into three light valves 925R and 925R by the rectangular lens of the second lens plate 922.
Superimposed around 5G and 925B. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has an uneven illuminance distribution in the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B are used.
Can be illuminated with uniform illumination light.

Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B and the green light beam G included in the light beam W are reflected at right angles, and head toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflection mirror 943, and is emitted from the emission unit 944 of the red light beam R to the prism unit 910 side.

Next, the green reflection dichroic mirror 942
Of the blue and green light fluxes B and G reflected by the blue-green reflection dichroic mirror 941,
Only the green light beam G is reflected at a right angle, and is emitted from the emission unit 945 of the green light beam G to the color combining optical system side. The blue light flux B that has passed through the green reflection dichroic mirror 942 is emitted from the emission section 946 of the blue light flux B to the light guide system 927 side. In this example, the emission portions 944 and 94 of the color light beams in the color separation optical system 924 from the emission portion of the light beam W of the uniform illumination optical element.
The distances to 5,946 are set to be substantially equal.

The red and green luminous flux R of the color separation optical system 924
Condensing lenses 951 and 952 are arranged on the emission sides of the G emission sections 944 and 945, respectively. Therefore,
The red and green luminous fluxes R and G emitted from the respective emission sections are incident on these condenser lenses 951 and 952 and are parallelized.

The red and green luminous fluxes R and G thus collimated enter the light valves 925R and 925G and are modulated to add image information corresponding to each color light. That is, the switching of these liquid crystal devices is controlled by driving means (not shown) in accordance with the image information, whereby each color light passing therethrough is modulated. On the other hand, the blue light flux B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to image information. In addition, the light valve 925 of this example
R, 925G, and 925B further include a liquid crystal light further including incident-side polarization units 960R, 960G, and 960B, emission-side polarization units 961R, 961G, and 961B, and liquid crystal devices 962R, 962G, and 962B disposed therebetween. It is a valve.

The light guide system 927 is a light emitting section 94 for the blue light flux B.
No. 6, a condenser lens 954 disposed on the exit side, an incident-side reflection mirror 971, an exit-side reflection mirror 972, an intermediate lens 973 disposed between these reflection mirrors, and a front side of the light valve 925B. And a condenser lens 953. The blue light flux B emitted from the condenser lens 946 is transmitted through the light guide system 927 to the liquid crystal device 962B.
And modulated. The optical path length of each color beam, that is,
Each liquid crystal device 962R, 962G, 9
The distance to 62B is the longest for the blue luminous flux B, and therefore the loss of light quantity of the blue luminous flux is the largest. However, by interposing the light guide system 927, the loss of light amount can be suppressed.

Each light valve 925R, 925G, 92
The color light fluxes R, G, and B modulated through 5B are incident on a color combining prism 910, where they are combined. The light combined by the color combining prism 910 is enlarged and projected on the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.

[Brief description of the drawings]

FIG. 1 illustrates various elements, wirings, and the like provided in a plurality of pixels in a matrix forming a display pixel region in a liquid crystal device.
FIG. 3 is an equivalent circuit diagram of a drive circuit area.

FIG. 2 is a plan view of a display pixel region of a TFT array substrate on which a data line, a scanning line, a pixel electrode, a TFT, and the like are formed in the liquid crystal device.

FIG. 3 is a sectional view taken along line A-A 'of FIG. 2;

FIG. 4 is a process diagram (part 1) for sequentially illustrating the steps of manufacturing the TFT array substrate of the liquid crystal device according to the first embodiment.

FIG. 5 is a process chart (part 2) for sequentially illustrating the steps of manufacturing the TFT array substrate of the liquid crystal device according to the first embodiment.

FIG. 6 is a process chart (part 3) for sequentially illustrating the steps of manufacturing the TFT array substrate of the liquid crystal device according to the first embodiment.

FIG. 7 is a process view (part 4) for sequentially illustrating the steps of manufacturing the TFT array substrate of the liquid crystal device in the first embodiment.

FIG. 8 is a process chart (part 5) for sequentially illustrating the steps of manufacturing the TFT array substrate of the liquid crystal device according to the first embodiment.

FIG. 9 is a plan view of the TFT array substrate in each embodiment of the liquid crystal device together with the components formed thereon as viewed from the counter substrate side.

FIG. 10 is a sectional view taken along line H-H ′ of FIG. 9;

FIG. 11 is a configuration diagram of a projection display device which is an example of an electronic device using a liquid crystal device.

FIG. 12 is a process diagram illustrating a manufacturing process of a TFT array substrate of a liquid crystal device according to the second embodiment.

FIG. 13 is a process chart showing a manufacturing process of a TFT array substrate of the liquid crystal device according to the third embodiment.

[Explanation of symbols]

1a: Semiconductor layer made of polysilicon 110: Quartz substrate 200: Liquid crystal device 210: Single crystal silicon film 210a: Single crystal silicon substrate 210b: Oxide film 210c: Film in which silicon ions are implanted into single crystal silicon film 210d: Polysilicon Film 210e: Crystal-grown single-crystal silicon film 211: Mask made of nitride film 401, 402: Semiconductor layer made of single-crystal silicon 600, 601: Oxide film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 29/78 627D 627G F-term (Reference) 2H092 JA28 JB52 JB58 KA03 KA05 MA05 MA13 MA17 MA23 MA26 MA27 MA30 MA37 NA27 RA05 5C094 AA13 AA21 AA43 AA48 AA49 AA53 AA56 BA03 BA16 BA43 CA19 CA24 DA09 DA13 DB01 DB04 EA04 EA05 EB02 ED03 ED15 FA01 FA02 FB02 FB12 FB14 FB15 GB10 5F052 AA02 AA01 AB01 A02 AA04 AA01 AA04 AA01 AA04 AA01 AA04 AA11 DD12 DD13 DD14 DD25 EE09 EE45 FF02 FF09 FF23 FF32 GG02 GG12 GG13 GG25 HJ01 HJ04 HJ23 HL03 HL05 HL07 HL23 HM15 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN35 NN44 NN46 NN16 PPN NN46 EE32 EE37 FF13 HH12 HH13 HH14 KK05 KK09

Claims (9)

[Claims] 1. A display pixel on which a switching element having at least a semiconductor layer made of a polysilicon film is disposed on a substrate, and a switching element having at least a semiconductor layer made of a single crystal silicon film for driving the display pixel is disposed. And (b) forming a single-crystal silicon film on the substrate; and (b) forming a single-crystal silicon film on the substrate. Forming a mask; (c) implanting silicon ions into a region of the single-crystal silicon film where the mask is not formed to form a non-single-crystal film; and (d) forming the non-single-crystal film in poly. (E) patterning the region into which the silicon ions have been implanted and the region into which the silicon ions have not been implanted; Forming a semiconductor layer made of a single-crystal silicon film and a semiconductor layer made of the single-crystal silicon film. 2. The method according to claim 1, wherein in the step (d), the region into which the silicon ions have been implanted is converted into polysilicon by heat treatment.
The manufacturing method of the electro-optical device according to the above. 3. The method further comprises: (f) removing the mask after the step (c) and before the step (d). In the step (d), the mask is removed by the heat treatment. 3. The method according to claim 2, wherein the non-single-crystal silicon film in an uncovered region is crystal-grown. 4. The step (a) includes: (g) bonding a single crystal silicon substrate into which hydrogen ions have been implanted, on the substrate; and (h) bonding the bonded substrate and the single crystal silicon substrate. 4. The method of manufacturing an electro-optical device according to claim 1, further comprising the steps of: separating the single crystal silicon film by heat treatment to form the single crystal silicon film on the substrate. 5. The method according to claim 1, further comprising: (i) forming an oxide film on the surface of the single crystal silicon film after the step (a) and before the step (c). A method for manufacturing an electro-optical device according to any one of claims 1 to 4. 6. The method according to claim 1, wherein the step (i) is performed after the step (b) and before the step (c), and the oxide film is formed by oxidizing a surface of the single crystal silicon film. The method for manufacturing an electro-optical device according to claim 5, wherein: 7. The method according to claim 5, further comprising: (j) removing the oxide film before the step (d). 8. The method of manufacturing an electro-optical device according to claim 1, wherein the mask is made of a nitride film. 9. An electro-optical device manufactured by the method for manufacturing an electro-optical device according to claim 1. Description: