JP2001255544A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device, capable of preventing defective pixels from occurring. SOLUTION: A liquid crystal is arranged between an array substrate 21 and a counter posing substrate facing the array substrate 21. Plural scanning lines 24 and signal lines 25 are arranged in an insulated state and orthogonal to each other on one main surface of an insulating substrate 22, having transparency of the array substrate 21. Lead-out electrodes 36a, 36b, which are led outside on the opposite side of an auxiliary electrode 32 arranged on the insulating substrate 22, are arranged, respectively. Auxiliary capacitance 35 is formed of an auxiliary capacitance part 33 on the auxiliary electrode 32, an auxiliary capacitance line 34 on the auxiliary capacitance part 33, and an auxiliary capacitance line 24 on the auxiliary capacitance part 33. Even when an interfacial level between the auxiliary capacitance part 32 and the auxiliary capacitance line 34 is large, high-frequency characteristic of the auxiliary capacitance part 33 will not be impaired. Consequently, the liquid crystal display device can prevent pixel defects from arising and can be produced in with satisfactory yield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device using a thin film transistor as a switching element.

[0002]

2. Description of the Related Art Conventionally, as this type of liquid crystal display device,
For example, a configuration shown in FIG. 4 is known.

The liquid crystal display device shown in FIG. 4 is of an active matrix type, and has an array substrate 1 and a counter substrate (not shown) facing the array substrate 1 and having counter electrodes (not shown). A liquid crystal of a liquid crystal composition (not shown) is provided between the array substrate 1 and the counter substrate.

In the array substrate 1, a plurality of scanning lines 3 and signal lines 4 formed of a conductive layer are formed on one main surface of an insulating substrate 2 having a light-transmitting property in parallel and orthogonal to each other. Insulated by an interlayer insulating film (not shown). At positions corresponding to intersections of the scanning lines 3 and the signal lines 4, thin film transistors (Thin Film Transistors) are provided.
tor) 5 is formed.

In this thin film transistor 5, an active layer 6 as a semiconductor layer is provided on an insulating substrate 2, and these active layers 6
A gate insulating film (not shown) formed of an insulating layer is provided on an insulating substrate 2 including
Are formed so as to be electrically connected to the scanning lines 3.

An auxiliary electrode 8 is formed on the insulating substrate 2 by a semiconductor layer forming the active layer 6, and an auxiliary capacitance section is formed on the auxiliary electrode 8 by an insulating layer forming a gate insulating film. 9 are formed. Further, on the auxiliary capacitance section 9, an auxiliary capacitance line 10 is formed of a conductive layer forming the scanning line 3. The auxiliary electrode 8 and the auxiliary capacitance unit 9
A storage capacitor 11 is formed by the storage capacitor line 10.

Further, the auxiliary electrode 8 is provided with one extraction electrode 12 extending to the outside. The thin film transistor 5 has a transparent conductor layer controlled by the thin film transistor 5 and arranged in a matrix. (Not shown) are electrically connected.

When the thin film transistor 5 is sequentially driven by the potential of the scanning line 3, the voltage applied to the signal line 4 is changed to change the pixel at the intersection between the scanning line 3 and each signal line 4. Is controlled, the state of the liquid crystal changes, and an image is displayed.

Further, when driving the liquid crystal display device shown in FIG. 4, if the frequency response characteristic of the auxiliary capacitor 11 of the pixel is poor, the auxiliary capacitor 9 of the auxiliary capacitor 11 cannot hold a predetermined capacitance. This may cause a pixel defect. When a semiconductor such as polysilicon or amorphous silicon is used as the active layer 6 for the auxiliary electrode 8 of the auxiliary capacitor 11, the active layer 6 is affected by the interface state between the auxiliary electrode 8 and the auxiliary capacitance line 10. In addition, the response characteristics at high frequencies are likely to deteriorate.

The deterioration of the response characteristic is also caused by the shape of the auxiliary electrode 8. Therefore, the farther from the extraction electrode 12 of the auxiliary electrode 8, which is reduced in resistance due to the contact, the higher the high-frequency response characteristic. Easy to deteriorate.

Since the writing time per pixel becomes shorter as the number of pixel electrodes increases, the frequency of the auxiliary capacitance section 9 of the auxiliary capacitance 11 increases, that is, the higher the definition of the array substrate 1 becomes, the higher the frequency becomes. The degradation of the response characteristics of the device will appear remarkably.

[0012]

As described above, in the liquid crystal display device shown in FIG. 4 described above, since the auxiliary electrode 11 extends from the auxiliary electrode 8 at one location, the auxiliary electrode 8 and the auxiliary capacitance line 10 is large, and the lead electrode 12 of the auxiliary electrode 8 has a low resistance for contact.
There is a problem that the high frequency characteristics of the auxiliary capacitance 11 are poor at a location far from the storage capacitor 11 and may cause a pixel defect.

The present invention has been made in view of the above points, and has as its object to provide a liquid crystal display device capable of preventing occurrence of pixel defects.

[0014]

SUMMARY OF THE INVENTION The present invention is directed to an insulating substrate having a light-transmitting property, and a plurality of insulating substrates disposed on one main surface of the insulating substrate so as to cross each other and formed of conductive layers and insulated from each other. A signal line and a scanning line, an active layer formed of a semiconductor layer provided on the insulating substrate, a gate electrode provided on the insulating substrate and electrically connected to the scanning line, and the gate electrode and the active layer. A thin film transistor having a gate insulating film formed of an insulating layer located between the layers, the thin film transistor disposed corresponding to the intersection of the signal line and the scanning line, and an auxiliary formed of a conductive layer forming the scanning line An auxiliary having an auxiliary electrode formed of a capacitance line and a semiconductor layer forming the active layer, and an auxiliary capacitance portion formed between the auxiliary capacitance line and the auxiliary electrode and formed of an insulating layer forming the gate insulating film. Capacity, said thin An array substrate including a pixel electrode that is a transparent conductor layer controlled by a transistor and arranged in a matrix, and a plurality of extraction electrodes provided on each of opposite sides of the auxiliary electrode and extracted to the outside; , And a liquid crystal disposed between the array substrate and the counter substrate.

In this configuration, a plurality of extraction electrodes are extracted from the opposite sides of the auxiliary electrode of the auxiliary capacitance of the array substrate, so that the auxiliary electrode formed of the semiconductor layer forming the active layer and the scanning line are connected. Even when the interface state between the auxiliary capacitance line formed by the conductor layer to be formed and the auxiliary capacitance line is large, the high-frequency characteristics of the auxiliary capacitance having the auxiliary capacitance portion located between the auxiliary capacitance line and the auxiliary electrode are not impaired. . Therefore, the occurrence of pixel defects is prevented, and the yield is improved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the liquid crystal display device of the present invention will be described below with reference to FIGS.

The liquid crystal display device shown in FIGS. 1 to 3 is an active matrix type TFT liquid crystal display device, and has an array substrate 21. A counter substrate (not shown) is provided opposite to the array substrate 21, and a liquid crystal of a liquid crystal composition (not shown) is provided between the array substrate 21 and the counter substrate.

The array substrate 21 includes an insulating substrate 22 having a light-transmitting property. An under surface for preventing diffusion of impurities from the insulating substrate 22 is provided on one main surface of the insulating substrate 22. A coat film 23 is formed.

Further, on the undercoat film 23,
A plurality of scanning lines 24 and signal lines 25 formed of a conductive layer are arranged in parallel and orthogonal to each other and insulated by an interlayer insulating film 26. And these scanning lines 24 and signal lines
At a position corresponding to the intersection with 25, a thin film transistor (Thin Film Transistor) 27 as a switching element is formed.

On the undercoat film 23, a substantially flat rectangular island-like active layer 28 made of a semiconductor layer such as polysilicon as polycrystalline silicon is formed. On the insulating substrate 22 including these active layers 28, a gate insulating film 29 is provided as an insulating layer such as a SiO ₂ film.

Further, on the gate insulating film 29, a gate electrode 31 orthogonal to the scanning line 24 is formed so as to be electrically connected to the gate region of the thin film transistor 27, that is, protrude orthogonal to the scanning line 24. It is formed so as to be electrically connected to the scanning line 24. The active layer 28, the gate insulating film 29 and the gate electrode 31 form a thin film transistor.
27 are formed.

On the undercoat film 23, an active layer
An island-shaped auxiliary electrode 32 is formed of polysilicon, which is a semiconductor layer forming 28. Further, on the auxiliary electrode 32, an auxiliary capacitance portion 33 is formed of a SiO ₂ film which is an insulating layer for forming the gate insulating film 29.

A scanning line is provided on the auxiliary capacitance section 33.
The storage capacitor line 34 is formed of a conductive layer forming 24.
An auxiliary capacitance 35 is formed by the auxiliary electrode 32, the auxiliary capacitance portion 33, and the auxiliary capacitance line.

Further, on opposite sides in the longitudinal direction of the auxiliary electrode 32, that is, on opposite sides, two extraction electrodes 36a and 36b are formed, one each from the opposite side. At the base ends of these extraction electrodes 36a and 36b,
Leader electrode regions connected to the sides of the active layer 28 respectively
37a and 37b are formed respectively.

An interlayer insulating film 26 is formed over substantially the entire surface of the insulating substrate 22. The interlayer insulating film 26
Contact holes communicating with the extraction electrode areas 37a and 37b
38a and 38b are open.

A metal film (not shown) such as aluminum (Al) is formed almost all over the interlayer insulating film 26. The metal film forms the signal line 25 and forms the thin film transistor 27 (not shown). One of a source region and a drain region is formed, and is electrically connected to the signal line 25 to form an electrode.

Further, one of the source region and the drain region of the thin film transistor 27 has an insulating substrate
Pixel electrodes (not shown), which are transparent conductor layers arranged in a matrix, are electrically connected to each other.

Next, the manufacturing process of the embodiment will be described.

First, the undercoat film 23 is formed on the insulating substrate 22.
Is formed. The undercoat film 23 is formed by a chemical vapor reaction.
Formed by sputtering or sputtering₂Used by
Have been. The undercoat film 23 is made of SiO.
₂Besides, Si₃N₄And Si ₃N₄And SiO₂And two layers
It may be formed by a thin film or the like.

Next, an active layer 28 and an auxiliary electrode 32 are formed on the undercoat film 23. The active layer 28 and the auxiliary electrode 32 are formed by, for example, a plasma CVD method, an LPCV
After an amorphous silicon film is formed by a film forming method such as a method D or a sputtering method, the amorphous silicon film is subjected to laser annealing to be polycrystallized.

The active layer 28 and the auxiliary electrode 32
May be formed by, for example, a method of forming the seed from amorphous silicon by solid phase growth, or a method of directly forming by a plasma CVD method using SiO ₄ , SiF ₄ , B ₂ or the like as a source gas. In addition, the active layer 28 and the auxiliary electrode 32 may be made of amorphous silicon or the like instead of polysilicon. Then, this amorphous silicon is formed, for example, by plasma CVD, LPCVD.
The film is formed by a sputtering method, a sputtering method, or the like.

Further, the active layer 28 and the auxiliary electrode 32
Are formed in an island shape by etching. The etching of the active layer 28 and the auxiliary electrode 32 is performed, for example, by using CF ₄ .O.
_This is performed by chemical dry etching (CDE) using _two gases. Here, this chemical dry etching (CD
The etching conditions at the time E) are as follows: the flow rate ratio of O ₂ / CF ₄ is 4, the etching pressure is 40 Pa, the microwave power supply is 800 W, and the substrate temperature is 60 ° C.

Then, extraction electrodes 36a and 36b are formed on both sides of the auxiliary electrode 32 in the longitudinal direction, that is, on opposite sides.

Next, a gate insulating film 29 is formed on the active layer 28 and an auxiliary capacitance section 33 is formed on the auxiliary electrode 32. The gate insulating film 29 and the auxiliary capacitance portion 33 are formed by a plasma CVD method using tetraethylorthosilicate (TEOS) .O ₂ as a source gas.

The gate insulating film 29 and the auxiliary capacitance portion 33 are formed by a normal pressure CVD method,
It can also be formed by another CVD method such as a PCVD method, an ECR plasma CVD method, a remote plasma CVD method, or a method such as a sputtering method. Further, the gate insulating film 29 and the auxiliary capacitance portion 33 can be formed by using a SiH ₄ .O ₂ gas other than the (TEOS) .O ₂ gas as a source gas.

Further, when the film quality of the gate insulating film 29 and the auxiliary capacitance portion 33 is further improved after the formation of the gate insulating film 29 and the auxiliary capacitance portion 33, for example, at 600 ° C. in a nitrogen atmosphere, The gate insulating film 29 and the auxiliary capacitance portion 33 are annealed for 5 hours.

The gate electrode 31 is formed on the gate insulating film 29.
Is formed, and an auxiliary capacitance line 34 is formed on the auxiliary capacitance section 33. The gate electrode 31 and the auxiliary capacitance line 34
Molybdenum-tungsten alloy (MoW) and aluminum
It is made of low resistance metal such as (Al) or polycrystalline silicon into which impurities are introduced.

Further, the gate electrode 31 and the auxiliary capacitance line 34 are self-aligned as a mask after being patterned into a predetermined shape.

Next, phosphorus (P), which is an n-type impurity, is ion-implanted into the extraction electrode regions 37a and 37b of the extraction electrodes 36a and 36b, for example, under the condition of 5e ¹⁶ / cm ² so that a contact can be made. Each lowers the resistance. At this time, the phosphorus introduced by the ion implantation is activated by annealing such as laser annealing or thermal annealing.

Thereafter, when the storage capacitor 35 is made to be P-type, a p-type impurity such as boron (B) is extracted from the extraction electrode region 37.
Ions are implanted into each of a and 37b.

Then, an interlayer insulating film 26 is formed over substantially the entire surface of the insulating substrate 22. At this time, contact holes 38 communicating with the lead electrode regions 37a and 37b are formed in the interlayer insulating film 26.
Open a and 38b.

Further, a metal film is formed substantially all over the interlayer insulating film 26. This metal film is patterned and electrically connected to the source region.

Next, the operation of the above embodiment will be described.

First, an undercoat film 23 is formed on one main surface of the insulating substrate 22.

Next, after forming the active layer 28 and the auxiliary electrode 32 on the undercoat film 23,
And the auxiliary electrode 32 is etched.

Further, lead electrodes 36a and 36b are formed on opposite sides of the auxiliary electrode 32, respectively.

Thereafter, the leading electrodes 36a and 36b are pulled out to the outside so that the leading electrodes 36a and 36b are pulled out to the outside.
a, 36b, the respective lead electrode regions 37a, 37b, the active layer 28
And a gate insulating film 29 and an auxiliary capacitor on the auxiliary electrode 32
Form 33.

Next, a gate electrode 31 and an auxiliary capacitance line 34 are formed on the gate insulating film 29 and the auxiliary capacitance part 33.

Further, an interlayer insulating film 26 is formed substantially all over the insulating substrate 22, and a metal film is formed substantially entirely over the interlayer insulating film 26.

As described above, according to the above-described embodiment, a total of two extraction electrodes are provided, one each from the opposite side of the auxiliary electrode 32 forming the auxiliary capacitance 35 of the array substrate 21.
When the opposite side of the auxiliary electrode 32 is long due to the extraction of 36a and 36b, or when the interface level between the auxiliary electrode 32 and the auxiliary capacitance line 34 is large as a result of using polysilicon for the auxiliary electrode 32, Even if it does, it is possible to prevent the response characteristic of the auxiliary capacitance portion 33 of the auxiliary capacitance 35 at high frequency from deteriorating. Therefore, a predetermined capacity can be held in the auxiliary capacity section 33 of the auxiliary capacity 35.

Here, the deterioration of the response characteristic of the auxiliary capacitor 35 at a high frequency is caused by the shape of the auxiliary electrode 32. The higher the distance from the extraction electrodes 36a and 36b formed on the auxiliary electrode 32, the higher the response of the high frequency response. Although the characteristics are apt to deteriorate, this auxiliary electrode
By forming the extraction electrodes 36a and 36b on the opposite sides of 32, deterioration of the response characteristics of the auxiliary capacitance portion 33 of the auxiliary capacitance 35 at high frequencies can be prevented.

Therefore, when sequentially driving the thin film transistors 27 according to the potential of the scanning line 24, the voltage applied to the signal line 25 is changed, and the potential of the pixel at the intersection between the scanning line 24 and each signal line 25 is changed. It is possible to prevent the occurrence of pixel defects that occur when control is performed. As a result, since the array substrate 21 can be manufactured with a high yield, the manufacturing cost can be reduced, and further, the reliability for consumers can be improved.

Further, although the writing time per pixel becomes shorter as the number of pixel electrodes increases, the frequency of the auxiliary capacitance 32 is increased by forming the extraction electrodes 36a and 36b on the opposite sides of the auxiliary electrode 32, respectively. However, the resolution can be further improved.

In the above embodiment, the auxiliary electrode 32
Although the configuration in which the extraction electrodes 36a and 36b are extracted one by one from the opposite sides of the auxiliary electrode 32 has been described, the present invention is not limited to such a configuration, and at least one or more extraction electrodes 36a and 36b With the configuration in which 36a, 36b,... Are formed, the same operation and effect as in the above-described embodiment can be obtained.

[0055]

According to the present invention, since a plurality of extraction electrodes are extracted from each of the opposite sides of the auxiliary electrode of the auxiliary capacitance, even if the interface state between the auxiliary electrode and the auxiliary capacitance line is large, the auxiliary capacitance is reduced. Since the high-frequency characteristics of the portion are not impaired, the occurrence of pixel defects can be prevented and the production can be performed with high yield.

[Brief description of the drawings]

FIG. 1 is a plan view showing a part of one embodiment of a liquid crystal display device of the present invention.

FIG. 2 is an aa cross-sectional view of an array substrate of the liquid crystal display device.

FIG. 3 is a sectional view of the array substrate, taken along line bb.

FIG. 4 is a plan view showing a part of a conventional liquid crystal display device.

[Explanation of symbols]

 21 Array substrate 22 Insulating substrate 24 Scan line 25 Signal line 27 Thin film transistor 28 Active layer 29 Gate insulating film 31 Gate electrode 32 Auxiliary electrode 33 Auxiliary capacitance part 34 Auxiliary capacitance line 35 Auxiliary capacitance 36a, 36b Leader electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA24 HA06 HA28 JA24 JA28 JB57 JB63 JB64 JB65 JB68 JB69 KA04 KA05 KA12 MA08 MA18 MA19 NA23 NA29 NA30 5C094 AA31 AA42 BA03 BA43 CA19 DB02 EA04 EA07 FB12 AFB13 DD5 DD17 EE03 EE06 EE09 FF02 FF28 FF29 FF30 FF31 FF32 FF36 GG02 GG13 GG15 GG43 GG45 GG47 HL03 NN73 PP03

Claims (1)

[Claims] An insulating substrate having a light-transmitting property; a plurality of signal lines and scanning lines which are disposed on one main surface of the insulating substrate so as to cross each other, are formed of conductive layers, and are insulated from each other; An active layer formed of a semiconductor layer provided on a substrate, a gate electrode provided on the insulating substrate and electrically connected to the scanning line, and an insulating layer located between the gate electrode and the active layer Forming a thin film transistor having a gate insulating film formed at a position corresponding to an intersection of the signal line and the scanning line, forming an auxiliary capacitance line formed of a conductive layer forming the scanning line, and forming the active layer A storage capacitor having an auxiliary electrode formed of a semiconductor layer to be formed and an auxiliary capacitance portion formed between the auxiliary capacitance line and the auxiliary electrode and formed of an insulating layer forming the gate insulating film; An array substrate including a pixel electrode, which is a transparent conductor layer arranged in a matrix, and a plurality of extraction electrodes provided on each of opposite sides of the auxiliary electrode and extending to the outside; A liquid crystal display device comprising: a counter substrate; and a liquid crystal disposed between the array substrate and the counter substrate.