JP2001245013A - Digital quadrature modulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale by composing an interpolation filter and a quadrature modulation part in with digital circuits. SOLUTION: This quadrature modulation system related to digitization can make the sampling frequency of data after digital quadrature modulation half, can also perform signal transmission with the same amount of information and at the same information rate as in the conventional technique and can further make a data interpolation circuit simpler than in the conventional system by using two sets each from discrete data streams consisting of an in-phase component and a quadrature component to perform digital quadrature modulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulator and a modulation method thereof, and more particularly, to a modulator capable of reducing the circuit scale without deteriorating performance by forming an interpolation filter (half-band filter) and a quadrature modulator with a digital circuit. It relates to the modulation method.

[0002]

2. Description of the Related Art In recent years, regarding the digitization of a quadrature modulation system, Japanese Patent Application Laid-Open Nos. Hei 6-244883 and Hei 10-3040 have been proposed.
No. 01 and many others have been proposed. According to the above proposal, the digital quadrature modulation method uses the sampling frequency F
I component and Q input at a frequency of s / 4 or less
Interpolation operation is performed on each discrete point of the component, or without interpolation operation, I and Q are each multiplied by -1;
This is a method of outputting the generated four types of data strings (I, -Q, -I, Q) at a sampling frequency Fs by a parallel / serial conversion operation.

FIG. 4 shows an example of a conventional digital quadrature modulator. As a precondition, data of N discrete points for each of I and Q per unit time is sampled at a sampling frequency Fs / 4.
The I component from one input 1 and the Q component from the other input 2 are input to flip-flop (FF) circuits 41A and 41B for input sampling, respectively.

The input 1 is used as an interpolation filter 1 (43A).
Then, the input 2 is supplied to an interpolation filter 2 (43B), and the interpolation data (4
(Double up-sampling data). At this time, the sampling frequency is Fs.

A multiplier 47A multiplies the output of the interpolation filter 1 (43A) and the cosine data of the cosine table 46A in which one cycle is represented by four discrete data of 1, 0, -1, 0 by one discrete point. At this time, the data of the I component corresponding to the first 1 exists and is supplied to the multiplier 47A, but the data of the I component corresponding to −1 does not exist.
The interpolation data is interpolated by the interpolation filter 1 and the multiplier 47 is generated.
A.

Similarly, the output of the interpolation filter 2 (43B) and the negative sine data of the sine table 46B in which one cycle is represented by four discrete data of 0, -1, 0, 1 are represented by 1
Multiplication is performed by the multiplier 47B for each discrete point. At this time, -1,
Since the Q component data corresponding to 1 does not exist and is not supplied to the multiplier 47A, the interpolation data is interpolated by the interpolation filter 2 and is supplied to the multiplier 47B.

The outputs of the multipliers 47A and 47B are added at a discrete point by a multiplexer 49, which is an adder, and are output to obtain digital orthogonal modulation data. FIG. 6 shows an example of the waveform of the digital quadrature modulation data output from the multiplexer 49.

In the above conventional example, when sine and cosine data having four points per cycle are represented, they can be represented by ± 1 and 0, and when one of the sine data or cosine data is 1 or −1, it is no longer possible. Since one cosine data or sine data has a feature of becoming zero, there is another conventional example as shown in FIG. As a prerequisite, it is assumed that data at N discrete points for each of I and Q are supplied at a sampling frequency Fs / 4, and an I component is supplied from an input 1 and a Q component is supplied from an input 2 per unit time.

The input 1 is input to the interpolation filter 1 (43A), the input 2 is input to the interpolation filter 2 (43B), and the interpolation filter 1 (43A) generates data having phases of 0 and π. 2 (43B), the phase becomes π /
It generates data of 2π and 3π / 2, and outputs interpolation data whose discrete points are each 2N.

In this case, the sampling frequency is Fs /
It becomes 2. The output of the interpolation filter 1 (43A) is multiplied by one discrete point at a multiplier 47A with the phase 0 and the value of π of the cosine data of the cosine table 75A, 1 and −1, and similarly, the interpolation filter 2 ( 43B) and the phase π / of the negative sine data of the sine table 46B.
The values of −1 and 1, which are the values of 2 and 3π / 2, are multiplied by one discrete point in the multiplier 47B.

When the outputs of the multipliers 47A and 47B are output from the adder 49C, which is a 2: 1 multiplexer, at the sampling frequency Fs, the output of the multiplier 47A and the output of the multiplier 47B are output one discrete point at a time. Get the data. At this time, the frequency component of the digital quadrature modulation data is center frequency Fc = Fs / 4.

[0012]

As described above, in order to obtain a digital quadrature modulation signal having a sampling frequency Fs, data of the I and Q components is read out at a frequency lower than Fs and digital signal processing is performed. When performing signal transfer with a high information rate, it is necessary to increase the sampling frequency. Therefore, logic operation ICs, ROMs, RAMs, and the like that can support high frequencies are required.
Further, there is a problem that it is necessary to reduce an error in the wiring length on the substrate as much as possible.

It is an object of the present invention to provide an apparatus and a method for generating a signal capable of digital orthogonal modulation of a conventional information amount at half the sampling frequency and transmitting the signal.

[0014]

According to the first aspect of the present invention, the above object is achieved by defining the sampling frequency Fs = Fs, the center frequency Fc = 0, and the occupied bandwidth 2Fb (2Fb <Fs). A digital quadrature modulation system having a frequency characteristic of a pass band center frequency Fo (= Fs / 2) with respect to multicarrier data, and having a sampling frequency of 2 Fs, is provided. The invention of the second aspect is a digital quadrature modulation system in which an in-phase component (hereinafter, I component) and a quadrature component (hereinafter, Q component) of N discrete points (N is an integer of 1 or more) are input and output in parallel by digital signal processing. An interpolation filter for calculating interpolation data (hereinafter, Q ′) located at the center between the discrete points of the Q component, a demultiplexer for dividing the I component into even columns and odd columns, respectively, A demultiplexer that divides the components into even columns and odd columns, a multiplying circuit for multiplying the odd-numbered I component output from the demultiplexer by −1, and an even-numbered Q ′ component output from the demultiplexer And an even-numbered I component [I (2
n)] and the even-numbered Q ′ component multiplied by −1 [-Q ′ (2n)]
And the odd-numbered I component [−I (2n + 1)] multiplied by −1, and the odd-numbered Q ′ component [Q ′] output from the multiplexer.
(2n + 1)] and I (2n), -Q '(2n), -I (2n +
2. A digital quadrature modulation system according to claim 1, wherein the digital quadrature modulation system comprises a parallel / serial converter that outputs 1) and Q '(2n + 1) in order, and outputs 2N digital quadrature modulation data. The invention according to claim 3 is characterized in that the discrete points N points (N
Is a digital quadrature modulation system in which an in-phase component (hereinafter, referred to as an I component) and a quadrature component (hereinafter, referred to as a Q component) of one or more integers are input and output in parallel by digital signal processing. , An interpolating filter for calculating interpolation data (hereinafter referred to as I ′) located at the center of the matrix, a demultiplexer for dividing the I ′ component into even columns and odd columns, respectively, and the Q component into even columns and odd columns, respectively. A demultiplexer for splitting, a multiplying circuit for multiplying an odd-numbered I ′ component output from the demultiplexer by −1, and an even-numbered Q output from the demultiplexer.
A multiplication circuit for multiplying the component by -1; an even-numbered I 'component [I' (2n)] output from the demultiplexer; and an even-numbered Q component [-Q (2n)] multiplied by -1 And the odd-numbered I ′ component [−I ′ (2n + 1)] multiplied by −1 and the odd-numbered Q component [Q (2n + 1)] output from the multiplexer in parallel, I '(2n), -Q (2n), -I' (2n + 1), Q (2n + 1)
And a parallel / serial converter that outputs in the order of
2. A digital quadrature modulation system according to claim 1, wherein 2N points of digital quadrature modulation data are output, and the invention according to claim 4 uses a half-band filter as said interpolation filter. It is an object of the present invention to provide a digital quadrature modulation system according to the second or third aspect.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention has been applied to a system in which four or more digital quadrature modulations are conventionally performed on N discrete point data using one set of discrete point data.
By performing digital quadrature modulation of 4 points using continuous two sets of discrete point data and outputting 2N points of discrete point data, half of the conventional sampling frequency Fs is obtained. This makes it possible to output a digital quadrature modulation data string having the same information rate.

The present invention also relates to the data interpolation performed by passing each of I and Q through an interpolation filter according to the present invention.
Or Q, but only for I,
This makes it possible to compensate for a timing error occurring between Qs.

One embodiment of an apparatus to which the digital quadrature modulation system of the present invention is applied will be described below with reference to the drawings. One embodiment of the apparatus to which the digital quadrature modulation system of the present invention shown in FIG. 1 is applied is a flip-flop circuit (FF) 11A, 11B, 15A1, 15A2, 15B.
1, 15B2, 1/4 frequency divider 12, interpolation filter 13,
1/2 demultiplexers 14A and 14B, multiplier 17
A, 17B, 1/8 frequency divider 18, 4/1 multiplexer 19, and 1/2 frequency divider 20.

As a precondition, I, Q per unit time
Each of the data at N discrete points is a sampling frequency Fs / 4 of the output of the 1/4 frequency divider 12 which is the same as the conventional example, and the I component from the input 1 and the Q component from the input 2 are each used as a flip-flop circuit for input sampling. FF) 11A, 1
1B.

The I component data of input 1 is supplied directly to a 1/2 demultiplexer 14A via a flip-flop circuit (FF) 11A. 1/2 demultiplexer 14
In A, it is divided into an even-numbered I component [I (2n)] and an odd-numbered I component [I (2n + 1)].

At this time, since two discrete data are output simultaneously, the sampling frequency of the output data is Fs / 8
Is supplied from the ８ frequency divider 18.

Among the outputs of the 1/2 demultiplexer 14A, the odd-numbered I component [I (2n + 1)] corresponding to the phase π of the cosine data by the multiplier 17A via the flip-flop circuit (FF) 15A2. Is multiplied by -1.

The Q component data of input 2 is supplied to an interpolation filter (half-band filter) 13 via a flip-flop circuit (FF) 11B. The interpolation filter (half-band filter) 13 generates interpolation data (double up-sampling data) having 2N discrete points and generates a data sequence of N points (hereinafter referred to as Q ′) from which original data has been removed. I do.

Q 'is input to the 1/2 demultiplexer 14B, and the even-numbered Q' component [Q '(2n) and the odd-numbered Q'
The component is divided into [Q '(2n + 1)]. At this time, in order to output two discrete data at the same time, the sampling frequency of the output data is supplied from the ８ frequency divider 18 at Fs / 8.

Of the output of the 1/2 demultiplexer 14B, the even-numbered Q 'component [Q' (2n)] is converted into negative sine data by a multiplier 17B through a flip-flop circuit (FF) 15B1 with a phase of π /. The value corresponding to 2 is multiplied by -1.

In the 4/1 multiplexer 19, the I (2n),-
Input I (2n + 1), -Q '(2n) and Q' (2n + 1), and
I (2n), -Q '(2 at sampling frequency of Fs / 2
By performing n), -I (2n + 1), and Q '(2n + 1), digital quadrature modulation data can be obtained.

This enables a digital quadrature modulation system at the same data rate as the conventional one at a sampling frequency which is half the sampling frequency in the conventional digital quadrature modulation system.

FIG. 3 shows an example in which the quadrature modulation waveform of the digital quadrature modulation system of the present invention is compared with the modulation waveform of the conventional digital quadrature modulation system. As for the Q component shown on the right side of FIG. 3, the Q component data corresponding to the discrete data of sine 1 and -1 shown by black squares is that of the digital quadrature modulation system of the present invention (Fs / 2 waveform). Since there is no direct counterpart to the conventional one (the waveform of Fs), it is created by interpolation with an interpolation filter.

On the other hand, as for the I component shown on the left side of FIG. 3, the I component data corresponding to the discrete data of the cosine 1 and -1 shown by the black and white circles directly corresponds to the I component, but does not partially exist. Therefore, this is similarly created by interpolating with an interpolation filter.

However, in the digital quadrature modulation system of the present invention (the waveform of Fs / 2), all I component data directly corresponding to the discrete data of cosine 1 and -1 shown by the black and white circles are present. There is no need for any interpolation in the interpolation filter. Therefore, in the digital quadrature modulation system of the present invention (Fs / 2 waveform), it is necessary to interpolate the Q component with an interpolation filter. In the conventional device (Fs waveform), both the I and Q components are interpolated by the interpolation filter. Will need to be done.

Here, the reason why the sampling frequency in FIG. 2 is set to the same Fs as in the conventional case is to facilitate comparison with the sampling frequency of the digital quadrature modulation signal obtained in the conventional example. In practice, the sampling frequency to be applied is set to half that of the conventional one, and is applied.

FIG. 2 shows the sampling frequency Fs shown in FIG.
This is another embodiment in the case where the frequency of the laser beam is reduced to 1/2 in advance. For example, when digital orthogonal modulation is performed on 1024 discrete data at a symbol rate of 20 μs, the sampling frequency Fs in the first conventional example needs to be 1 / (20 ⁻⁶ /(1024×4))=204.8 MHz. On the other hand, when the method of the present invention is used, digital quadrature modulation can be performed at a sampling frequency Fs of 1 / (20 ⁻⁶ /(1024×2))=102.4 MHz.

[0032]

According to the digital quadrature modulation system of the present invention,
By reducing the clock of the output signal to half the conventional one, there is an effect that the problem of speeding up the digital signal processing after the digital quadrature modulation can be reduced.

Further, since an interpolation filter for compensating for a phase error generated between the I component and the Q component only needs to be added to either I or Q, the circuit scale can be reduced and the cost can be reduced. Greatly contributes to the

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an apparatus to which a digital quadrature modulation system of the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of an apparatus to which the digital quadrature modulation system of the present invention is applied.

FIG. 3 is a diagram showing a comparison between respective modulation waveforms of the present invention and a conventional digital quadrature modulation method.

FIG. 4 is a block diagram showing an example of a conventional digital quadrature modulation system.

FIG. 5 is a block diagram showing another example of the conventional digital quadrature modulation system.

FIG. 6 is a diagram showing a modulation waveform of a conventional digital quadrature modulation method.

[Explanation of symbols]

10A I component input terminal 10B Q component input terminal 10C Sampling clock input terminal 11A, 11B Flip flop circuit (FF) 12, 12C 1/4 frequency divider 13 Interpolation filter (half band filter) 14A, 14B 1/2 demultiplexer 15A1, 15A2, 15B1, 15B2 Flip-flop circuit (FF) 17A, 17B Multiplier 18, 18C 1/8 frequency divider 19 4/1 multiplexer 20 1/2 frequency divider 21 Modulation data output terminal N Discrete number (N is 1 or more) Integer) Fb Occupied bandwidth Fc Center frequency Fo Passband center frequency Fs Sampling frequency

Claims (4)

[Claims] 1. A sampling frequency Fs = Fs and a center frequency Fc.
= 0, and has a frequency characteristic of a pass band center frequency Fo (= Fs / 2) with respect to the multi-carrier data defined so that the occupied bandwidth 2Fb (2Fb <Fs), and the sampling frequency is 2Fs. A digital quadrature modulation method characterized by: 2. A digital quadrature modulation system in which in-phase components (hereinafter, I components) and quadrature components (hereinafter, Q components) of N discrete points (N is an integer of 1 or more) are input and output in parallel by digital signal processing. An interpolation filter for calculating interpolation data (hereinafter, Q ′) located at the center between the discrete points of the Q component; a demultiplexer for dividing the I component into even columns and odd columns, respectively; A demultiplexer that divides the Q ′ component into even columns and odd columns, a multiplying circuit for multiplying the odd-numbered I component output from the demultiplexer by −1, and an even-numbered Q ′ output from the demultiplexer A multiplication circuit for multiplying the component by -1 and an even-numbered I component [I
(2n)] and the even-numbered Q ′ component multiplied by −1 [-Q ′ (2n)]
And the odd-numbered I component [−I (2n + 1)] multiplied by −1, and the odd-numbered Q ′ component [Q ′] output from the multiplexer.
(2n + 1)] and I (2n), -Q '(2n), -I (2n +
2. A digital quadrature modulation system according to claim 1, wherein the digital quadrature modulation system comprises a parallel / serial converter that outputs 1) and Q '(2n + 1) in order, and outputs 2N points of digital quadrature modulation data. 3. A digital quadrature modulation system in which in-phase components (hereinafter, I components) and quadrature components (hereinafter, Q components) of N discrete points (N is an integer of 1 or more) are input and output in parallel by digital signal processing. An interpolation filter for calculating interpolation data (hereinafter, I ′) located at the center between the discrete points of the I component; a demultiplexer for dividing the I ′ component into even columns and odd columns, respectively; A demultiplexer that divides the Q component into even columns and odd columns, a multiplying circuit for multiplying the odd-numbered I ′ component output from the demultiplexer by −1, and an even-numbered Q output from the demultiplexer A multiplication circuit for multiplying the component by −1, and an even-numbered I ′ component output from the demultiplexer
[I ′ (2n)] and the even-numbered Q component multiplied by −1 [-Q (2n)]
And the odd-numbered I 'component [-I' (2n + 1)] multiplied by -1.
And the odd-numbered Q component [Q (2n + 1)] output from the multiplexer in parallel, and I '(2n), -Q (2n), -I'
2. A digital quadrature modulation system according to claim 1, comprising a parallel / serial converter that outputs (2n + 1) and Q (2n + 1) in this order, and outputs 2N points of digital quadrature modulation data. . 4. The apparatus according to claim 2, wherein a half-band filter is used as said interpolation filter.
Digital quadrature modulation system as described.