JPH09181786A - Digital quadrature modulator and digital quadrature demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the circuit configuration not requiring an arithmetic circuit executing multiplication of exp(jωst) required for digital quadrature modulation/ demodulation. SOLUTION: A 2K-th tap of a roll off filter coefficient of a (4N-1)-tap designed on the basis of 4fs is assigned to an acyclic digital filter 3 and a (2K+1)-th tap is assigned to an acyclic digital filter 4 and a sign of the tap coefficients of the digital filters 3, 4 is inverted at an interval of one. A multiplexer circuit applies time division multiplex to outputs of the digital filters 3, 4 alternately to provide an output of the result. Thus, the arithmetic operation of convolution of the digital filters is executed simultaneously at the arithmetic operation for modulation and demodulation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to QAM (Quadra
ture Amplitude Modulation), VSB (Vestigial SideBa)
The present invention relates to a digital quadrature modulator and a digital quadrature demodulator used for digital transmission using quadrature modulation such as nd).

[0002]

2. Description of the Related Art In recent years, digital transmission using quadrature modulation such as 64QAM and 8VSB has begun to spread widely, and a digital quadrature modulator / demodulator that performs highly accurate quadrature modulation / demodulation by digital signal processing has become an indispensable technique. There is. An example of the above-described conventional quadrature modulator will be described below with reference to the drawings.

7 and 8 are block diagrams of conventional digital quadrature modulators. 7 and 8,
1 and 2 are sampling frequency converters, 12, 13,
3, 4 are non-recursive digital filters, 14, 15, 1
9, 20 are multipliers, 16, 17, 21, 22 are oscillators,
18 is an adder, 9 is a multiplex circuit, 11 is a register, 30,
Reference numeral 31 is a baseband signal input terminal, and 32 is a modulation signal output terminal.

The operation of the digital quadrature modulator having the above structure will be described below. For example, in 64QAM, a constant symbol rate (frequency fs
) Transmits any one of the 64 points arranged on the square at equal intervals. When this is decomposed into two axes, the I axis and the Q axis, which are orthogonal to each other, each becomes an 8-level signal. Input terminal 3
0 is an I-axis 8-level signal (R0, R1, ...)
However, the input terminal 31 has a Q-axis 8-level signal (I0, I
, 1) are input as digital values at a cycle of 1 / fs. Normally, these 8 levels are 8-10.
It is set in the bit space.

In the sampling frequency converters 1 and 2, the signals input from the input terminals 30 and 31 are oversampled four times. Specifically, three 0's are inserted for each piece of data, and a signal with a cycle of 1 / fs is cycled with 1 / cycle.
Output a 4fs signal. Therefore, the output of the sampling frequency converter 1 is 0,0,0, R0,0,0,
0, R1, ..., Sampling frequency converter 2
Output is 0,0,0, I0,0,0,0, I1, ...
・ It becomes.

The filter tap coefficients of the non-recursive digital filters 12 and 13 are the time-axis impulse response waveforms of the roll-off filter characteristics that are route-distributed to the demodulation side.
It is sampled at a time interval of / 4 fs. Q
Since the spectrum of the AM signal is line-symmetric with respect to the carrier, the time-axis impulse response of the roll-off filter characteristic is a real number, and the non-recursive digital filter 12, 1
The filter tap coefficients of 3 are the same. In the following description, the number of taps is 7 taps for simplicity, the filter tap coefficient on the output terminal side of the acyclic digital filter is C0 (0th), and the filter tap coefficient on the input terminal side is C6 (6th). And

The output of the acyclic digital filter 12 is multiplied by the output COSωs t of the oscillator 16 in the multiplier 14. On the other hand, the output of the acyclic digital filter 13 is multiplied by the output SINωs t of the oscillator 17 in the multiplier 15. The outputs of the multipliers 14 and 15 are added by an adder 18, and a QAM modulation signal (Y0, Y1, Y2, ...) Using the symbol rate fs as a carrier wave is output to the output terminal 32 at a cycle of 1 / 4fs. . Mathematically expressing this quadrature modulation process, the real part Re [(α + jβ) e of the product of the baseband signal (α + jβ) and the carrier wave exp (jωst) is expressed.
xp (jωs t)] becomes the modulation signal.

Here, the oscillators 16 and 17 have a cycle of 1 / fs
Since the SIN wave and the COS wave of are sampled at 4 fs, 0, 1, 0, -1 is repeated,
Can be easily realized. The multipliers 14 and 15 are also 0, 1,-
Since it is multiplication with 1, it can be easily realized. When the signal string obtained at the output terminal 32 is expressed, it becomes (Equation 1).

[0009]

[Equation 1]

[0010] When formula (1) is arranged, formula (2) is obtained.

[0011]

[Equation 2]

When the configuration of FIG. 7 is simplified based on (Equation 2), the block diagram of FIG. 8 is obtained. The sampling frequency converters 1 and 2 have a function of oversampling the signals input from the input terminals 30 and 31 by a factor of two. Specifically, one 0 is inserted for each data, and the cycle 1
A signal having a period of 1/2 fs is output from the signal of / fs. Therefore, the output of the sampling frequency converter 1 is 0,
R0,0, R1, ... and the output of the sampling frequency converter 2 becomes 0, I0,0, I1 ,.

Here, concrete configurations of the non-recursive digital filters 12 and 13 in FIG. 7 and the non-recursive digital filters 3 and 4 in FIG. 8 are shown in FIGS. FIG. 12 shows the non-recursive digital filters 12, 13
The configuration (same configuration) is shown. In FIG. 12, 1
Reference numeral 01 is an input terminal, 102 is an output terminal, 103 to 108 are registers that constitute a 1-clock delay circuit, 10
9 to 115 are constants C6, C5 for the input to the input terminal 101 and the outputs of the registers 103 to 108, respectively.
A multiplier for multiplying C4, C3, C2, C1, C0, and an adder 116 for adding the outputs of the multipliers 109 to 115.

FIG. 13 shows the configuration of the non-recursive digital filter 3. In FIG. 13, reference numeral 121 is an input terminal, 122 is an output terminal, 123 to 125 are registers constituting a one-clock delay circuit, 126 to 129 are inputs to the input terminal 121 and a register 123, respectively.
A multiplier for multiplying the outputs of .about.125 by constants C6, C4, C2, C0, and 130 is a multiplier 12
It is an adder that adds the outputs of 6 to 129.

FIG. 14 shows the configuration of the non-recursive digital filter 4. In FIG. 14, 131 is an input terminal, 132 is an output terminal, 133 and 134 are registers constituting a 1-clock delay circuit, 135-137 are inputs to the input terminal 131 and the register 13 respectively.
A multiplier 138 that multiplies the outputs to 3,134 by constants C5, C3, and C1 is an adder that adds the outputs of the multipliers 135 to 137.

The total number of filter tap coefficients of the acyclic digital filters 3 and 4 is (4N-1) (where N is an integer of 2 or more, and in the case of FIGS. 7 and 8, N = 2). Then, the time-axis impulse response waveform of the roll-off filter characteristic distributed to the demodulation side was sampled at a time interval of 1 / 4fs, but 2Kth (K =
0, 1, ..., (2N−1)) is assigned to the acyclic digital filter 3 and the (2K + 1) th (where K =
0, 1, ..., (2N−2)) are assigned to the non-recursive digital filter 4. Therefore, the interval of the filter tap coefficients of the non-recursive digital filters 3 and 4 on the time axis is 1/2 fs, and the operation cycle of the non-recursive digital filter is 1/2 fs. The register 11 is 2
This register operates with a clock of fs and is arranged to eliminate the delay difference in filter output due to the difference in the number of taps of the non-recursive digital filters 3 and 4. The numbers in the filter tap coefficient correspond to the numbers, and the filter tap coefficient starts from 0.

The multiplier 19 and the oscillator 21 perform the modulation by COSωs t, and the multiplier 20 and the oscillator 22 perform the modulation by SINωs t. It's simplified. Therefore, the cycle of this calculation is 1/2 fs. The multiplexing circuit 9 alternately selects the output of the multiplier 20 and the output of the multiplier 19 in this order to perform time-axis multiplexed output. By this operation,
The same signal as the QAM modulation signal (Y0, Y1, Y2, ...) With a period of 1/4 fs obtained by the above configuration can be obtained (for example, HSP43216 data sheet: HARRI).
S SEMICONDUCTOR).

In this quadrature modulator, the real part of the tap coefficient of the complex filter that realizes the VSB spectrum is the digital filter 12, and the imaginary part is the digital filter 1.
If the input is assigned to 3 and the input is the negative axis (only the input terminal 30), the same configuration can be used for VSB. An example of a conventional quadrature demodulator for QAM will be described below with reference to the drawings.

9 and 10 are block diagrams of a conventional digital quadrature demodulator for QAM transmission. 9 and 10, 55 and 56 are sampling frequency converters, 61, 62, 67 and 68 are acyclic digital filters, 65, 66, 71 and 72 are multipliers and 63,
64, 69, 70 are oscillators, 57, 58, 59, 60 are registers, 90 is an input terminal for a modulation signal, and 91 and 92.
Is a baseband signal output terminal.

The operation of the digital quadrature demodulator configured as described above will be described below. A QAM signal (X0, X) having a carrier frequency fs sampled at a period of 1 / 4fs input from the modulation signal input terminal 90.
, X2, ...) Are input to the multipliers 65 and 66 as they are.

In the multiplier 65, the C generated by the oscillator 63 is generated.
Multiplication with OS (−ωs t) is performed, and the multiplier 66
The multiplication with the SIN (−ωs t) generated by the oscillator 64 is performed. By this operation, quadrature demodulation is performed, and the I-axis and Q-axis baseband signals are extracted and input to the non-recursive digital filters 61 and 62, respectively. Mathematically expressing this quadrature demodulation process, the modulated signal (α + j
β) exp (jωs t) and reproduced carrier exp (−jωs
The product (α + jβ) of t) becomes the demodulated baseband signal.

Here, the oscillators 63 and 64 have a cycle of 1 / fs
Since the SIN wave and the COS wave are sampled at 1/4 fs, 0, 1, 0, -1 are repeated, which can be easily realized. Also, the multipliers 65 and 66 are 0,
Since it is a multiplication with 1 and -1, it can be easily realized. The filter tap coefficients of the non-recursive digital filters 61 and 62 are obtained by sampling the time-axis impulse response waveform of the roll-off filter characteristic that is route-distributed with the modulation side at a time interval of 1/4 fs. Since the spectrum of the QAM signal is line-symmetric with respect to the carrier wave, the time-axis impulse response of the roll-off filter characteristic is a real number, and the non-recursive digital filters 61 and 62 have the same filter tap coefficient. In the following description, for simplicity, the number of taps is 7, the filter tap coefficient on the output terminal side of the non-recursive digital filters 61 and 62 is C0 (0th), and the filter tap coefficient on the input terminal side is C.
6 (6th).

All the processes up to this point are performed in a cycle of 1/4 fs. As described in the processing on the modulation side, since four times oversampling is performed on one symbol in the transmission path, the final output is the non-recursive digital filter 6
Outputs 1, 62 are sub-sampled and one sample is selected from four samples to obtain a signal of symbol rate fs. In the demodulator, the symbol rate fs on the modulation side is regenerated by the clock regenerating circuit, so which one sample is selected is uniquely determined. The sampling frequency converters 55 and 56 perform this processing. The sub-sampled output is (R0, R4, ...
.), Q axis side becomes (I0, I4, ...) And is output from the baseband signal output terminals 91 and 92, respectively.

The signal sequence obtained at the baseband signal output terminals 91 and 92 is expressed by (Equation 3).

[0025]

(Equation 3)

When Formula 3 is rearranged, Formula 4 is obtained.

[0027]

(Equation 4)

If the configuration of FIG. 9 is simplified based on (Equation 4), the block diagram of FIG. 10 is obtained. A QAM signal (X0, X1, X2, which is input from the modulation signal input terminal 90 and has a carrier frequency fs sampled at a period of 1 / 4fs is sampled.
..) is delayed by one clock by the register 57 operating with a clock having a period of 1/4 fs. Registers 58 and 59
Since it is latched at clock 2fs, register 5
The output of 8 is (X0, X2, X4, ...), Register 5
The output of 9 is (X1, X3, X5, ...), and both become a signal train with a period of 1/2 fs.

The multiplier 71 and the oscillator 69 are COS (-ωs
When the detection by t) is performed, the multiplier 72 and the oscillator 70
Although the detection is performed by (-ωst), the calculation for multiplying by 0 is omitted and the calculation is further simplified as compared with FIG. Therefore, the cycle of this calculation is 1/2 fs. The total number of filter tap coefficients of the non-recursive digital filters 67 and 68 is (4N-1), and the time axis impulse response waveform of the roll-off filter characteristic that is route-distributed to the modulation side is sampled at a time interval of 1 / 4fs. The 2K-th of these are allocated to the non-recursive digital filter 67, and the (2K + 1) -th is allocated to the non-recursive digital filter 6
Assign to 8. Therefore, the interval of the filter tap coefficients of the non-recursive digital filters 67 and 68 on the time axis is 1/2 fs. Therefore, the operation cycle of the non-recursive digital filters 67 and 68 is 1/2 fs. The register 60 is a register which operates with a clock having a period of 1/2 fs and is arranged to eliminate a delay difference in filter output due to a difference in the number of taps of the acyclic digital filters 67 and 68.

Since the outputs of the non-recursive digital filters 67 and 68 form a signal train having a period of 1/2 fs, the function of the sampling frequency converters 55 and 56 is from 2 samples to 1
The function changes to select and output a sample. By this operation, the QAM demodulated signals (R0, R4, ...) And (I0, I4, ...) Of the period 1 / fs obtained in the configuration of FIG. 9 are obtained.
..) is obtained (for example, HSP432
16 DATA SHEET: HARRIS SEMICONDU
CTOR).

Next, an example of a conventional digital quadrature demodulator for VSB will be described with reference to the drawings. FIG. 11 is a block diagram of a conventional digital quadrature demodulator for VSB transmission. In FIG. 11, 55 and 56 are sampling frequency converters, 73, 74, 75,
76 is a non-recursive digital filter, 65 and 66 are multipliers, 63 and 64 are oscillators, and 77 and 78 are adders. Reference numeral 90 is an input terminal for the modulated signal, and 91 and 92 are output terminals for the baseband signal.

The operation of the digital quadrature demodulator configured as described above will be described below. A VSB signal (X0, X) input from the modulation signal input terminal 90 and sampled at a period of 1/4 fs and having a carrier frequency fs.
, X2, ...) are multipliers 65 and 66 and an oscillator 6
Quadrature detection is performed at 3,64.

Non-recursive digital filters 73, 74,
75 and 76 and adders 77 and 78 form a complex acyclic digital filter. Since the spectrum of the VSB signal is asymmetric with respect to the carrier, the time-axis impulse response of the roll-off filter characteristic is a complex number, and a complex acyclic digital filter is required. The non-recursive digital filters 73 and 76 use the real part of the time-axis impulse response as a coefficient. The non-recursive digital filters 74 and 75 use the imaginary part of the time-axis impulse response as a coefficient.

The output of the multiplier 65 which is the real part of the quadrature detection output and the calculation result of the real part of the time axis impulse response, and the output of the multiplier 66 which is the imaginary part of the quadrature detection output and the imaginary part of the time axis impulse response. The difference between the calculation results of is the real part of the complex acyclic digital filter. Further, the output of the multiplier 65, which is the real part of the quadrature detection output, and the calculation result of the imaginary part of the time axis impulse response, and the output of the multiplier 66, which is the imaginary part of the quadrature detection output, and the real part of the time axis impulse response. The sum of the calculation results becomes the imaginary part of the complex acyclic digital filter. Each filter tap coefficient is obtained by sampling the time axis impulse response waveform of the roll-off filter characteristic that is route-distributed with the modulation side at a time interval of 1/4 fs. In the following description, the number of taps is 7 for simplicity, and the non-recursive digital filters 73 and 7 are used.
Set the filter tap coefficient on the output terminal side of 4,75,76 to C
Let R0 and CI0 (0th) and the filter tap coefficients on the input terminal side be CR6 and CI6 (6th).

Since the output of the complex acyclic digital filter outputs data at a period of 1/4 fs as in the case of FIG. 9, the sampling frequency converters 55 and 56 select one sample from four samples and select the symbol rate. The data of fs is output from the demodulation signal output terminals 91 and 92. In VSB modulation, since the signal is placed only on the I axis, only (R0, R4, ...) Is the demodulated signal,
(I0, I4, ...) Are meaningless demodulated signals. However, when the carrier wave reproduction is not completed for the signals obtained at the output terminals 91 and 92, (I0, I4, ...
・) Can also be used for carrier recovery.

The signal sequence obtained at the output terminals 91 and 92 is expressed by (Equation 5).

[0037]

(Equation 5)

[0038]

However, although the above-mentioned configuration is simplified, an arithmetic circuit for multiplying SINωs t and COSωs t is required for modulation, and SIN (- ωs
There is a problem that an arithmetic circuit for multiplying t) and COS (-ωs t) is required.

In view of the above problems, the present invention provides a digital quadrature modulator and a digital quadrature demodulator that do not require an arithmetic circuit for multiplying SINωs t, COSωs t, etc. for modulation and demodulation.

[0040]

According to a first aspect of the present invention, there is provided a digital quadrature modulator comprising: a first non-recursive digital filter of 2N taps (where N is an integer of 2 or more) for inputting a first signal; A (2N-1) tap second non-recursive digital filter for inputting the second signal; and a multiplexing circuit for alternately time-multiplexing the outputs of the first and second non-recursive digital filters. There is. Then, the 2Kth (where K = 0, 1, 1) of (4N-1) real filter tap coefficients designed by quadruple oversampling are used.
, (2N-1)) is used as the first acyclic digital filter, and the (2K + 1) th (where K = 0, 1, ...,
(2N−2)) is assigned to the second acyclic digital filter, and the signs of the filter tap coefficients assigned to the first and second acyclic digital filters are inverted every other number.

A digital quadrature modulator according to claim 2 is
An N-tap (where N is an integer of 2 or more) first non-cyclic digital filter for inputting the first signal, and an N-tap second non-cyclic digital filter for inputting the first signal; An N-tap third acyclic digital filter for inputting the second signal and the second signal (N
-1) a fourth non-cyclic digital filter with taps;
And a multiplexing circuit for sequentially time-multiplexing the outputs of the first, second, third and fourth acyclic digital filters. Then, the 4Kth (where K = 0, 1, ..., (N-1)) of (4N-1) real filter tap coefficients designed by quadruple oversampling are used as the first non-recursive digital signal. The (4K + 2) th (where K = 0, 1, ..., (N-1)) is used as the filter and the (4K + 1) th (where K = is used) as the second acyclic digital filter.
0,1, ..., (N-1)) to the third non-recursive digital filter, where (4K + 3) th (where K = 0,1,
(N-2)) is assigned to the fourth non-recursive digital filter, and two non-recursive digital filters among the first, second, third, and fourth non-recursive digital filters are assigned. The signs of the tap coefficients are all inverted.

A digital quadrature modulator according to claim 3 is
A 2N-tap (where N is an integer of 2 or more) first non-recursive digital filter for inputting a first signal;
The second non-recursive digital filter of (2N-1) taps to which the signal of (1) is input, and the multiplex circuit for alternately time-multiplexing the outputs of the first and second non-recursive digital filters. Then, 2K-th (where K = 0, 1, ..., (2N−) of (4N−1) complex filter tap coefficients designed by 4 × oversampling
1)) to the first acyclic digital filter and the (2K + 1) th (where K = 0, 1, ..., (2
N−2)) imaginary part is assigned to the second acyclic digital filter, respectively, or the 2Kth (4K−1) complex filter tap coefficients (where K =
The imaginary part of 0, 1, ..., (2N-1) is applied to the first acyclic digital filter, and the (2K + 1) th (where K
= 0, 1, ..., (2N−2)) are assigned to the second acyclic digital filter, and the codes of the filter tap coefficients assigned to the first and second acyclic digital filters, respectively. Are reversed every other number.

A digital quadrature modulator according to a fourth aspect is
An N-tap (where N is an integer of 2 or more) first non-cyclic digital filter for inputting the first signal, and an N-tap second non-cyclic digital filter for inputting the first signal; An N-tap third acyclic digital filter for inputting the first signal and the first signal (N
-1) a fourth non-cyclic digital filter with taps;
And a multiplexing circuit for sequentially time-multiplexing the outputs of the first, second, third and fourth acyclic digital filters. Then, the 4K-th (where K = 0, 1, ..., (N-1)) real part of the (4N-1) complex filter tap coefficients designed by quadruple oversampling is set to the first non- The (4K + 2) -th (where K = 0, 1, ..., (N-1)) real part is included in the recursive digital filter, and the (4K + 1) -th (where K = The (4K + 3) th (where K = 0, 1, ... (N-2)) imaginary part is used as the imaginary part of 0, 1, ..., (N-1) in the third acyclic digital filter. It is assigned to each of the fourth acyclic digital filters, or 4Kth of (4N-1) complex filter tap coefficients (where K = 0, 1, ..., (N-1))
The imaginary part of the first non-recursive digital filter is (4
K + 2) th (however, K = 0, 1, ..., (N-1))
The imaginary part of the second non-recursive digital filter to (4
K + 1) th (however, K = 0, 1, ..., (N-1))
The real part of the third non-recursive digital filter to (4
K + 3) th (however, K = 0, 1, ..., (N-2))
And assigning the real part of each to the fourth non-recursive digital filter, and signing the filter tap coefficients of the two non-recursive digital filters of the first, second, third, and fourth non-recursive digital filters. Are all reversed.

The digital quadrature demodulator according to claim 5 is
2 of the input signal discretized by 4 times oversampling
The first of 2N taps (where N is an integer of 2 or more) for inputting the L-th (where L = 0, 1, ..., (2N-1))
, And the (2L + 1) th (where L = 0, 1, ..., (2
N-2)) is input to the second non-recursive digital filter of (2N-1) taps. Then, the 2Kth (4K-1) real filter tap coefficients designed by 4 times oversampling (where K = 0,
, ..., (2N−1)) is used as the first acyclic digital filter, and the (2K + 1) th (where K = 0, 1,
, (2N−2)) is assigned to the second acyclic digital filter, and the signs of the filter tap coefficients assigned to the first and second acyclic digital filters are inverted every other number. There is.

The digital quadrature demodulator according to claim 6 is
And a (2N-1) tap first and second acyclic digital filter for inputting a signal discretized by quadruple oversampling. Then, 2K-th (where K = 0, 1, ..., (2N-1) of (2N-1) (where N is an integer of 2 or more) complex-numbered filter tap coefficients designed by 4 times oversampling. )) To the 2K-th tap of the first acyclic digital filter and the imaginary part to the second acyclic digital filter of 2K.
Each is assigned to the K-th tap, and the (2K + 1) -th (where K = 0, 1, ..., (2N-2)) imaginary part of the (2N−1) complex filter tap coefficients is assigned to the first non- The real part is assigned to the (2K + 1) -th tap of the cyclic digital filter, or the real part is assigned to the (2K + 1) -th tap of the second non-cyclic digital filter, or (2N-1) complex filter tap coefficients are included. Two
The K-th (where K = 0, 1, ..., (2N-1)) imaginary part is used as the 2K-th tap of the first acyclic digital filter, and the real part is used as the second acyclic digital filter. Assigned to the 2Kth taps respectively, (2N-1)
The (2K + 1) th (where K = 0, 1, ..., (2N−2)) real part of the filter tap coefficients of the complex number is set to the (2K + 1) th tap of the first acyclic digital filter, The imaginary part is assigned to the (2K + 1) th tap of the second non-recursive digital filter, and the filter tap coefficients assigned to the first and second non-recursive digital filters are every two signs. They are being reversed one by one.

According to the structure of each of these claims, the operation of multiplying SINωs t, COSωs t, etc. required for orthogonal modulation / demodulation is performed simultaneously with the convolution operation in the non-recursive digital filter. t,
An arithmetic circuit for multiplying COS ω st etc. becomes unnecessary.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment of Digital Quadrature Modulator] Hereinafter, regarding a digital quadrature modulator in an embodiment of the present invention,
This will be described with reference to the drawings. FIG. 1 shows a first embodiment of a digital quadrature modulator for QAM. In FIG. 1, 1 and 2 are sampling frequency converters, 3 and 4 are non-recursive digital filters, 9 is a multiplexing circuit, 11 is a register, 30 and 31 are baseband signal input terminals, and 32 is a modulation signal output terminal. .

The operation is almost the same as that of the digital quadrature modulator shown in FIG. 8, except that the multipliers 19 and 20 and the oscillator 2 shown in FIG.
It is the points where 1 and 22 are deleted and the filter tap coefficients of the non-recursive digital filters 3 and 4. The number of filter tap coefficients of the acyclic digital filters 3 and 4 is 2N and (2N-1), respectively (where N is an integer of 2 or more).
It is. The filter tap coefficient is the 2Kth (4N-1) filter tap coefficient of the (4N-1) filter tap coefficients obtained by sampling the time-axis impulse response waveform of the roll-off filter characteristic distributed to the demodulation side at a time interval of 1 / 4fs. , (2N-1)) is assigned to the acyclic digital filter 3, and the (2K + 1) th (where K = 0, 1, ..., (2N-2)) is acyclic digital filter. Assign to filter 4. However, the sign of the even-numbered filter tap coefficient when viewed from the input side of each of the acyclic digital filters 3 and 4 is inverted.

Further, since one acyclic digital filter having (4N-1) filter tap coefficients is decomposed into two, the gain of each digital filter becomes 1/2. Therefore, the non-recursive digital filters 3, 4
Compensation is performed by doubling each filter tap coefficient of. With the configuration described above, the digital quadrature modulator of the first embodiment can obtain the same modulated signal as that of the conventional example shown in FIGS. 7 and 8. This is clear from the fact that (Equation 2) can be transformed into (Equation 6).

[0050]

(Equation 6)

As described above, the acyclic digital filters 3 and 4 in which the signs of the filter tap coefficients are periodically inverted
SINωs related to QAM modulation
An arithmetic circuit for multiplying t and COSωs t can be eliminated, and the configuration of the digital quadrature modulator can be simplified. The position at which the sign of the filter tap coefficient is inverted and the method of assigning the filter tap coefficient to the non-recursive digital filters 3 and 4 vary depending on how to select the phases of SINωs t and COSωs t, but the essential difference is Absent.

FIG. 2 shows a second embodiment of a digital quadrature modulator for QAM. In FIG. 2, 5, 6, 7,
8 is a non-recursive digital filter, 10 is a multiplexing circuit, 1
1 is a register, 30 and 31 are baseband signal input terminals, and 32 is a modulation signal output terminal. I-axis baseband signals (R0, R1, ...
.) Is input to the acyclic digital filters 5 and 6. The Q-axis baseband signals (I0, I1, ...) Input from the input terminal 31 are input to the non-recursive digital filters 7 and 8.

Non-recursive digital filters 5, 6, 7,
The number of taps of 8 is N, N, N, (N-1), respectively.
(However, N is an integer of 2 or more). The time-axis impulse response waveform of the roll-off filter characteristic that is route-distributed to the demodulation side is sampled at a time interval of 1 / 4fs, and the 4Kth of the (4N-1) filter tap coefficients (where K = 0, 1, , (N-1) is applied to the non-recursive digital filter 5 and the (4K + 1) th (where K =
0, 1, ..., (N-1)) is applied to the acyclic digital filter 7 at the (4K + 2) th (where K = 0, 1, ...,
(N-1)) to the acyclic digital filter 6 and (4
K + 3) th (however, K = 0, 1, ..., (N-2))
Are assigned to the non-recursive digital filter 8. Further, the signs of the filter tap coefficients of the non-recursive digital filter 5 and the non-recursive digital filter 8 are inverted.

Since one acyclic digital filter having (4N-1) filter tap coefficients is decomposed into four, the gain of each digital filter becomes 1/4. Therefore, the non-recursive digital filter 5,
The filter tap coefficients of 6, 7 and 8 are quadrupled to compensate. Since the number of taps of only the non-recursive digital filter 8 is smaller than that of the other non-recursive digital filters by one tap, the register 1 for compensating the delay in the filter 1
Insert 1. The register 11 operates at the clock fs. The non-recursive digital filters 5, 6, 7, 8
Perform processing at the symbol rate fs. In FIG.
Similar to the conventional example, when (4N-1) has 7 taps (N = 2), the filter tap coefficient allocation is entered. From FIG. 2 and (Equation 6), the output of the acyclic digital filter 8 is Y0, and the output of the acyclic digital filter 6 is Y.
1, the output of the non-recursive digital filter 7 coincides with Y2, and the output of the non-recursive digital filter 5 coincides with Y3. Therefore, a modulated signal can be obtained by time-multiplexing the filter outputs in the order of the non-recursive digital filters 8, 6, 7, and 5 in the multiplexing circuit 10 and multiplexing them as a signal having a period of 1/4 fs. Modulation output (Y0, Y1, Y2
...) are non-recursive digital filters 5, 6, 7,
Since the four patterns of (Equation 6) are repeated regardless of the number of taps of 8, the quadrature modulator can be realized with the configuration of FIG. In the above, the configuration does not depend on the number of taps, but it is necessary to change the number of taps of each digital filter 5, 6, 7, 8 according to the number of taps in the conventional example. For example, when N of the conventional digital quadrature modulator is 3, the circuit of FIG. 2 also needs to have a configuration of N = 3.

As described above, the filter tap coefficient of the non-recursive digital filter is divided into four sets, and two of them are divided.
By inverting the sign of the set of filter tap coefficients,
That is, by inverting the sign of the filter tap coefficient of the non-recursive digital filters 5, 6, 7, and 8 among the non-recursive digital filters 5, 6, 7, and 8, multiplication by SINωs t and COSωs t relating to QAM modulation is performed. The circuit can be eliminated and the structure of the digital quadrature modulator can be simplified. Further, in the configuration of FIG. 2, since the non-recursive digital filters 5, 6, 7, and 8 are all processed at the symbol rate fs, it is suitable for realizing a high bit rate digital quadrature modulator.

Depending on how the phases of SINωs t and COSωs t are selected, the non-recursive digital filter whose sign of the filter tap coefficient should be inverted and the filter tap coefficients to the non-recursive digital filters 5, 6, 7, and 8 are selected. Allocation changes, but there is no essential difference. Figure 3 shows VSB
1 shows a first embodiment of a digital quadrature modulator for use in digital broadcasting.
In FIG. 3, 1 is a sampling frequency converter, and 3, 4
Is a non-recursive digital filter, 9 is a multiplexing circuit, 11 is a register, 30 is a baseband signal input terminal, and 32 is a modulation signal output terminal.

The operation is almost the same as in FIG. The difference is VSB modulation, in which the input of the non-recursive digital filter 3 on the I-axis side and the non-recursive digital filter 4 on the Q-axis side is connected to the output of the sampling frequency converter 1 because the baseband signal is only on the I-axis. This is the point that has been fully made. Since the VSB modulated wave has an asymmetric spectrum with respect to the carrier wave, its waveform shaping filter requires a non-recursive digital filter having complex filter tap coefficients. Therefore, the non-recursive digital filter 3 is assigned the real part of the complex coefficient, and the non-recursive digital filter 4 is assigned the imaginary part of the complex coefficient.

However, the method of FIG. 1 of the present invention derived from FIGS. 7 and 8 of the conventional example can be used. The filter tap coefficients of the non-recursive digital filters 3 and 4 are 2N and (2N-1), respectively (where N is an integer of 2 or more). The complex impulse response waveform on the time axis of the roll-off filter characteristic that is route-distributed to the demodulation side is sampled at a time interval of 1 / 4fs and the 2Kth (4N-1) filter tap coefficients (where K = 0 , 1, ..., (2
N−1)) real part is assigned to the acyclic digital filter 3, and the (2K + 1) th (where K = 0, 1,
, (2N-2)) is assigned to the acyclic digital filter 4. Further, the sign of the even-numbered filter tap coefficient when viewed from the input side of each of the acyclic digital filters 3 and 4 is inverted.

Further, since one acyclic digital filter having (4N-1) filter tap coefficients is decomposed into two, the gain of each digital filter becomes 1/2. Therefore, the non-recursive digital filters 3, 4
Compensation is performed by doubling each filter tap coefficient of. With the configuration described above, the digital quadrature modulator of this embodiment has a VSB modulated signal (Y0, Y1, Y2, ...) Using the symbol frequency fs as a carrier.
Can occur.

As described above, by providing the acyclic digital filter in which the sign of the filter tap coefficient is periodically inverted, SINωs t, CO relating to VSB modulation is provided.
An arithmetic circuit for multiplying Sωs t can be eliminated, and the configuration of the digital quadrature modulator can be simplified. The position at which the sign of the filter tap coefficient is inverted and the method of assigning the filter tap coefficient to the non-recursive digital filters 3 and 4 vary depending on how to select the phases of SINωs t and COSωs t, but the essential difference is Absent. Contrary to the above allocation, the complex impulse response waveform on the time axis of the roll-off filter characteristic that is route-distributed to the demodulation side is sampled at a time interval of 1 / 4fs (4N-
1) 2Kth of the filter tap coefficients (where K =
The imaginary part of 0, 1, ..., (2N−1)) is assigned to the acyclic digital filter 3, and the (2K + 1) th (where K = 0, 1, ..., (2N−2)) real part is assigned. It may be assigned to the non-recursive digital filter 4. The configuration in this case is as shown in FIG.

FIG. 4 shows a second embodiment of a digital quadrature modulator for VSB. In FIG. 4, 5, 6, 7,
8 is a non-recursive digital filter, 10 is a multiplexing circuit, 1
1 is a register, 30 is a baseband signal input terminal, 32
Is a modulation signal output terminal. Since VSB modulation is performed as in FIG. 3, the baseband signal is only the I axis, and the input signal of one system is the non-recursive digital filter 5, 6, 7 ,.
8 is commonly input.

Non-recursive digital filters 5, 6, 7,
The number of taps of 8 is N, N, N, (N-1), respectively.
(N is an integer of 2 or more). The complex impulse response waveform on the time axis of the roll-off filter characteristic that is route-distributed to the demodulation side is sampled at a time interval of 1 / 4fs and the 4Kth of the (4N-1) filter tap coefficients (where K = 0 , 1, ..., (N-1)), the real part of the (4K + 1) th (where K = 0, 1, ..., (N-1)) imaginary part is acyclic. Type digital filter 7 has a (4K + 2) th (however,
The real part of K = 0, 1, ..., (N−1) is input to the acyclic digital filter 6 at the (4K + 3) th (where K =
The imaginary part of 0, 1, ..., (N−2)) is assigned to the acyclic digital filter 8.

Since one acyclic digital filter having (4N-1) filter tap coefficients is decomposed into four, the gain of each digital filter becomes 1/4. Therefore, the non-recursive digital filter 5,
The filter tap coefficients of 6, 7 and 8 are quadrupled to compensate. Further, the signs of the filter tap coefficients of the non-recursive digital filters 5 and 8 are inverted. Since only the non-recursive digital filter 8 has a tap number smaller than that of the other non-recursive digital filters by one tap, the register 11 for compensating the delay in the filter is inserted. Register 1
1 operates with the clock fs. The non-recursive digital filters 5, 6, 7, and 8 are all symbol rate fs.
Perform processing.

In FIG. 4, (4M-1) is 7 as in the conventional example.
In the case of taps, the assignment of filter tap coefficients is entered. From the analogy of the relationship between FIG. 2 and (Equation 6), the output of the acyclic digital filter 8 is Y0, the output of the acyclic digital filter 6 is Y1, the output of the acyclic digital filter 7 is Y2, and the acyclic digital filter 7 is It can be seen that the output of filter 5 matches Y3. Therefore, the non-recursive digital filters 8, 6, 7 and 5 are time-multiplexed in the order of the filter outputs by the multiplexing circuit 10, and the cycle is 1/4 fs.
A modulated signal can be obtained by multiplexing as the signal of. Since the modulation output (Y0, Y1, Y2, ...) Repeats four patterns of (Equation 6) regardless of the number of taps of the acyclic digital filter, a quadrature modulator can be realized with the configuration of FIG. .

As described above, the filter tap coefficients of the non-recursive digital filter are divided into four sets, and two of them are divided.
By inverting the sign of the set of filter tap coefficients,
That is, by inverting the signs of the filter tap coefficients of the non-recursive digital filters 5, 6, 7 and 8 among the non-recursive digital filters 5, 6, SINωs t and COSωs t related to VSB modulation are multiplied. The circuit can be deleted, and the configuration of the digital quadrature modulator can be simplified. Further, in the configuration of FIG. 4, all the non-recursive digital filters perform processing at the symbol rate fs, which is suitable for realizing a high bit rate modulator.

Depending on how the phases of SINωs t and COSωs t are selected, the non-recursive digital filter whose sign of the filter tap coefficient should be inverted and the filter tap coefficients for the non-recursive digital filters 5, 6, 7, and 8 are selected. Allocation changes, but there is no essential difference. Contrary to the above allocation, the complex impulse response waveform on the time axis of the roll-off filter characteristic that is route-distributed to the demodulation side is 1 /
The 4Kth of (4N-1) filter tap coefficients sampled at a time interval of 4fs (where K = 0, 1,
The imaginary part of (N-1) is input to the acyclic digital filter 5 at the (4K + 1) th (where K = 0, 1, ...,
The non-recursive digital filter 7 for the real part of (N-1))
, (4K + 2) th (where K = 0, 1, ..., (N
The imaginary part of -1)) to the non-recursive digital filter 6,
(4K + 3) th (however, K = 0, 1, ..., (N−
The real part of 2)) may be assigned to the acyclic digital filter 8.

[Embodiment of Digital Quadrature Demodulator] A digital quadrature demodulator according to an embodiment of the present invention will be described below with reference to the drawings. Figure 5 shows QA
An embodiment of a digital quadrature demodulator for M is shown. FIG.
, 51 and 52 are non-recursive digital filters,
55 and 56 are sampling frequency converters, 57 and 58,
59 and 60 are registers, 90 is a modulation signal input terminal, 9
Reference numerals 1 and 92 are baseband signal output terminals.

The operation is almost the same as that of the digital quadrature demodulator of FIG. 10, except that the multipliers 71 and 72 and the oscillators 69 and 70 of FIG. 10 are removed, and the filter tap coefficient of the acyclic digital filter. . The filter tap coefficients of the non-recursive digital filters 51 and 52 are each 2
There are N and (2N-1) (where N is an integer of 2 or more). The time-axis impulse response waveform of the roll-off filter characteristic that is route-distributed to the modulation side is sampled at a time interval of 1 / 4fs and the 2Kth of (4N-1) filter tap coefficients (where K = 0, 1, …, (2N-
1)) is assigned to the acyclic digital filter 51,
(2K + 1) th (however, K = 0, 1, ..., (2N−
2)) is assigned to the acyclic digital filter 52.

However, the non-recursive digital filter 5
The signs of the even-numbered filter tap coefficients as viewed from the respective input sides of 1, 52 are inverted. Further, since one acyclic digital filter having (4N-1) filter tap coefficients is decomposed into two, the gain of each digital filter becomes 1/2. Therefore, the compensation is performed by doubling each filter tap coefficient of the non-recursive digital filters 51 and 52.

With the configuration described above, the digital quadrature demodulator of this embodiment has the configuration shown in FIGS.
It is possible to obtain the same demodulation signal as that of the conventional example. This is clear from the fact that (Equation 4) can be transformed into (Equation 7).

[0071]

(Equation 7)

As described above, by providing the acyclic digital filter in which the sign of the filter tap coefficient is periodically inverted, the SIN (-ωs for QAM demodulation is provided.
t) and COS (−ωs t) are not required for the arithmetic circuit, and the configuration of the digital quadrature demodulator can be simplified. In addition, SIN (-ω st), COS (-
Depending on how the phase of ω st) is selected, the position at which the sign of the filter tap coefficient is inverted and the non-recursive digital filter 5
The method of assigning the filter tap coefficients to 1,52 changes, but there is no essential difference.

In QAM quadrature demodulation, the filter tap coefficients of the non-recursive digital filter are symmetrical, so that C0 = C6, C2 = C4, C1 = C5 in the example of FIG.
By using the fact that (Equation 7) can be further transformed into (Equation 8).

[0074]

(Equation 8)

That is, by modifying the sign of the addition of the input signal sequence and the sign of the filter tap coefficient, SIN (-ωst) and COS related to QAM demodulation can be obtained.
It is possible to reduce the number of multipliers of the non-recursive digital filter by half while eliminating the need for an arithmetic circuit that multiplies (-ωst). In this case, the configuration of the non-recursive digital filter 51 is as shown in FIG. 16, and the configuration of the non-recursive digital filter 52 is as shown in FIG. In FIG. 16, 141 is an input terminal, 142 is an output terminal, 143 to 145 are registers constituting a one-clock delay circuit, 146, 147 are adders, 148, 149.
Is a multiplier for multiplying constants C0 and C2, and 150 is an adder. In FIG. 17, reference numerals 153 and 154 are registers forming a one-clock delay circuit, 155 is an adder, and 156 and 156.
157 is a multiplier for multiplying the constants -C1 and C3, and 158 is an adder.

FIG. 6 shows an embodiment of a digital quadrature demodulator for VSB. In FIG. 6, 53 and 54 are non-recursive digital filters, 55 and 56 are sampling frequency converters, 90 is a modulation signal input terminal, and 91 and 92 are baseband signal output terminals. The demodulated baseband signal of the VSB modulated signal obtained in the description of FIG. 11 is expressed by (Equation 5), which can be rearranged into (Equation 9).

[0077]

[Equation 9]

A block diagram for realizing (Equation 9) is shown in FIG. That is, a VSB modulated signal (X0, X) having a carrier frequency fs sampled at a period of 1/4 fs
1, X2, ...) are non-recursive digital filters 5
3, 54. Non-recursive digital filter 5
The filter tap coefficients of 3,54 are (4N-1), respectively.
(However, N is an integer of 2 or more). The complex impulse response waveform on the time axis of the roll-off filter characteristic that is route-distributed with the modulation side is sampled at a time interval of 1 / 4fs and 2K of (4N-1) filter tap coefficients.
The second (where K = 0, 1, ..., (2N−1)) real part is the 2Kth tap of the acyclic digital filter 53, and the imaginary part is 2K of the acyclic digital filter 54.
Assigned to the second tap, the (2K + 1) th (However,
The imaginary part of K = 0, 1, ..., (2N−2)) is applied to the (2K + 1) th tap of the acyclic digital filter 53.
The real part is set to (2K +
1) Assign to the 1st tap. Further, the output side of the non-recursive digital filter is tap number 0, and the (4K + 2) th and (4K + 3) th (where K = 0, 1, ..., (N−
1)), the sign of the filter tap coefficient is inverted, and the (4K + 1) th and (4K + 1) th and (4
K + 2) th (however, K = 0, 1, ..., (N-1))
The sign of the filter tap coefficient of is inverted. In addition, (4N
Since one acyclic digital filter having -1) filter tap coefficients is decomposed into two, the gain of each filter is halved. Therefore, compensation is performed by doubling each filter tap coefficient of the non-recursive digital filters 53 and 54.

Since the non-recursive digital filters 53 and 54 perform the operation at a period of 1/4 fs, the sampling frequency converter 5 which selects and outputs one sample from four samples
5 and 56, I-axis demodulation output (R0, R4, ...
.) Is output to the output terminal 91, and the Q axis demodulation output (I0, I4,
...) is output to the output terminal 92. As mentioned above,
By periodically inverting the sign of the filter tap coefficient and providing a non-cyclic digital filter in which the real and imaginary parts of the complex filter are alternately arranged, the VSB
SIN (-ωs t), COS (-ωs t) for demodulation
It is possible to simplify the configuration of the complex filter and the configuration of the digital quadrature demodulator while eliminating the need for an arithmetic circuit for multiplying by.

Note that SIN (-ωst), COS (-ω
The position at which the sign of the filter tap coefficient is inverted and the non-recursive digital filter 5
The method of assigning the filter tap coefficients to 3, 54 changes, but there is no essential difference. Contrary to the above, the complex impulse response waveform on the time axis of the roll-off filter characteristic that is route-distributed to the modulation side is sampled at a time interval of 1 / 4fs and 2K of (4N-1) filter tap coefficients.
The second (where K = 0, 1, ..., (2N-1)) imaginary part is used as the 2Kth tap of the acyclic digital filter 53, and the real part is 2K of the acyclic digital filter 54.
Assigned to the second tap, the (2K + 1) th (However,
The real part of K = 0, 1, ..., (2N−2) is set to the (2K + 1) th tap of the acyclic digital filter 53.
The imaginary part is set to (2K +
It may be assigned to the 1) th tap. The configuration in this case is as shown in FIG.

[0081]

As described above, according to the digital quadrature modulator and the digital quadrature demodulator of the present invention, the sign of the filter tap coefficient of the non-recursive digital filter is periodically inverted, so that the SIN for quadrature modulation / demodulation can be obtained.
An arithmetic circuit for multiplying ωs t, COS ωs t, etc. is not required, which makes it possible to provide a digital quadrature modulator / demodulator having a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram of a QAM digital quadrature modulator according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a QAM digital quadrature modulator according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a VSB digital quadrature modulator according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a VSB digital quadrature modulator according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a QAM digital quadrature demodulator according to the first embodiment of the present invention.

FIG. 6 is a block diagram of a VSB digital quadrature demodulator according to the first embodiment of the present invention.

FIG. 7 is a block diagram of a QAM digital quadrature modulator according to a first conventional example.

FIG. 8 is a block diagram of a QAM digital quadrature modulator according to a second conventional example.

FIG. 9 is a block diagram of a QAM digital quadrature demodulator of a first conventional example.

FIG. 10 is a block diagram of a QAM digital quadrature demodulator of a second conventional example.

FIG. 11 is a block diagram of a conventional VSB digital quadrature demodulator.

12 is a non-recursive digital filter 1 in FIG.
It is a block diagram which shows the concrete structure of 2 and 13.

13 is a non-recursive digital filter 3 in FIG.
FIG. 3 is a block diagram showing a specific configuration of FIG.

14 is a non-recursive digital filter 4 in FIG.
FIG. 3 is a block diagram showing a specific configuration of FIG.

15 is a block diagram showing a configuration of a modified example of the VSB digital quadrature modulator of FIG.

16 is a non-recursive digital filter 5 in FIG.
It is a block diagram which shows the structure of the modified example of 1.

17 is a non-recursive digital filter 5 in FIG.
It is a block diagram which shows the structure of the 2nd modification.

18 is a block diagram showing a configuration of a modified example of the VSB digital quadrature demodulator of FIG. 6. FIG.

[Explanation of symbols]

 1, 2 Sampling frequency converter 3, 4, 5, 6, 7, 8 Non-recursive digital filter 9, 10 Multiplexing circuit 11 Register 30, 31 Baseband signal input terminal 32 Modulation signal output terminal 51, 52, 53, 54 Non-recursive digital filter 55,56 Sampling frequency converter 57,58,59,60 Register 90 Modulation signal input terminal 91,92 Baseband signal output terminal

Claims (6)

[Claims] 1. A 2N-tap (where N is an integer of 2 or more) first acyclic digital filter for inputting a first signal and a (2N-1) -tap first input for a second signal. Two non-recursive digital filters and a multiplex circuit for alternately time-multiplexing the outputs of the first and second non-recursive digital filters, and (4N-1) pieces designed by 4 times oversampling 2Kth of the real number filter tap coefficients (where K =
0, 1, ..., (2N-1)) is added to the first acyclic digital filter, and the (2K + 1) th (where K =
0, 1, ..., (2N−2)) is respectively assigned to the second acyclic digital filter, and the codes of the filter tap coefficients assigned to the first and second acyclic digital filters are A digital quadrature modulator characterized by being inverted every other unit. 2. An N-tap first non-cyclic digital filter for inputting a first signal (where N is an integer of 2 or more), and an N-tap second non-recursive digital filter for inputting the first signal. A cyclic digital filter, an N-tap third non-cyclic digital filter that inputs the second signal, and an (N-1) tap fourth non-cyclic digital filter that inputs the second signal. , A multiplexing circuit for sequentially time-multiplexing the outputs of the first, second, third, and fourth acyclic digital filters, and (4N-1) real number of real numbers designed by 4 times oversampling. 4Kth filter tap coefficient (K =
0, 1, ..., (N-1)) is added to the first acyclic digital filter and the (4K + 2) th (where K = 0,
, ..., (N-1)) are supplied to the second non-recursive digital filter, and the (4K + 1) th (where K = 0, 1,
, (N-1)) to the third non-recursive digital filter (4K + 3) th (where K = 0, 1, ...
(N-2)) is respectively assigned to the fourth non-recursive digital filter, and two non-recursive digital filters of the first, second, third and fourth non-recursive digital filters are assigned. A digital quadrature modulator characterized by inverting all signs of filter tap coefficients. 3. A 2N-tap (where N is an integer equal to or greater than 2) first acyclic digital filter for inputting a first signal, and a (2N-1) tap for inputting the first signal. A second non-recursive digital filter and a multiplexing circuit for alternately multiplexing the outputs of the first and second non-recursive digital filters on the time axis are provided, and designed by 4 times oversampling (4N-1). 2Kth of the complex filter tap coefficients (however, K
, (2N-1)) to the first acyclic digital filter, the (2K + 1) th (where K = 0, 1, ..., (2N-2)) An imaginary part is assigned to each of the second acyclic digital filters, or 2K-th of (4N-1) complex filter tap coefficients (where K = 0, 1, ..., (2N-
The imaginary part of 1)) is added to the first acyclic digital filter, and the (2K + 1) th (where K = 0, 1, ...,
(2N−2)) real numbers are assigned to the second non-recursive digital filter, and the code of the filter tap coefficient assigned to each of the first and second non-recursive digital filters is alternated. A digital quadrature modulator characterized by being inverted. 4. An N-tap (where N is an integer of 2 or more) first non-cyclic digital filter for inputting a first signal, and an N-tap second non-cyclic digital filter for inputting the first signal. A cyclic digital filter, an N-tap third non-cyclic digital filter for inputting the first signal,
The (N-1) tap fourth non-recursive digital filter for inputting the first signal and the outputs of the first, second, third and fourth non-recursive digital filters are sequentially time-axis multiplexed. And 4Kth of (4N-1) complex filter tap coefficients (however, K
, (N-1)), the real part of the (4K + 2) th (where K = 0, 1, ..., (N-1)) is added to the first acyclic digital filter. The real part is the second
, (4K + 1) th (where K = 0, 1, ..., (N-1)) imaginary part is added to the third acyclic digital filter as (4K + 3).
The (thus, K = 0, 1, ... (N-2)) imaginary part is assigned to the fourth acyclic digital filter, or 4K of (4N-1) complex filter tap coefficients. Th (however, K = 0, 1, ..., (N-
The imaginary part of 1)) is added to the first non-recursive digital filter as (4K + 2) th (where K = 0, 1, ...,
The imaginary part of (N-1)) is applied to the second acyclic digital filter, and the (4K + 1) th (where K = 0, 1,
, (N-1)), the (4K + 3) th (where K = 0,
1, ..., (N−2)) are assigned to the fourth acyclic digital filter, and two of the first, second, third, and fourth acyclic digital filters are assigned. A digital quadrature modulator characterized in that all the signs of the filter tap coefficients of the non-recursive digital filter are inverted. 5. The 2L-th (where L = 0, 1, ..., (2
(N-1)) is input to the first non-recursive digital filter of 2N taps (where N is an integer of 2 or more), and the (2L + 1) -th (where L is L) of the discretized input signal.
= 0, 1, ..., (2N-2)) is input (2N-1)
A second acyclic digital filter of taps, and 2K-th of (4N-1) real filter tap coefficients (where K =
0, 1, ..., (2N-1)) is added to the first acyclic digital filter, and the (2K + 1) th (where K =
0, 1, ..., (2N−2)) is assigned to each of the second acyclic digital filters, and the sign of the filter tap coefficient assigned to each of the first and second acyclic digital filters is 1 A digital quadrature demodulator characterized by being inverted every other number. 6. A (4N-1) tap first and second acyclic digital filter for inputting a signal discretized by 4 times oversampling, and designed by 4 times oversampling (4N- 1) (where N is an integer of 2 or more) 2Kth (where K = 0, 1, ..., (2N−) of complex filter tap coefficients
The real part of 1)) is assigned to the 2K-th tap of the first non-recursive digital filter, and the imaginary part is assigned to the 2K-th tap of the second non-cyclic digital filter. (2K + 1) th (where K = 0, 1, ..., (2
N-2)) is assigned to the (2K + 1) th tap of the first non-recursive digital filter, and the real part is assigned to the (2K + 1) th tap of the second non-recursive digital filter. Or the above (4N-
1) The 2K-th (where K = 0, 1, ..., (2N−1)) imaginary part of the complex filter tap coefficients is used as a real number for the 2K-th tap of the first acyclic digital filter. Section to the 2K-th tap of the second non-recursive digital filter, respectively, and (4N-
1) The (2K + 1) th (where K = 0, 1, ..., (2N−2)) real part of the complex filter tap coefficients is (2K +) of the first acyclic digital filter.
An imaginary part is assigned to the 1) -th tap to the (2K + 1) -th tap of the second non-recursive digital filter, respectively, and filter tap coefficients assigned to the first and second non-recursive digital filters, respectively. A digital quadrature demodulator characterized by inverting the code of every two.