JP2001243113A - Storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simply provide a data storage device that can conduct a complete read and write functions for the memory unit, the functions of which take a load off the control programming for the storage device for resetting a memory unit without checking status of the storage part. SOLUTION: The storage device comprises the storage unit 20 that stores data, a power supply unit 30 that feeds power to the memory unit 20, and a control unit 10 that controls the unit 20. The control unit 10 controls the power supply unit 30 to feed power to the memory unit 20 only when controls the unit 20 for storing the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data readable / writable storage device.

[0002]

2. Description of the Related Art In recent years, with the development of high-integration technology of flash memories, large-capacity flash memory cards that can be mounted and removed from a storage device and that can retain rewritten contents even when the power is turned off have become widespread.

In such a flash memory card, when connecting to a microcomputer, hardware and software connection specifications are made compatible with existing large-capacity hard disks, and connection know-how accumulated in the past is used. Instead of making use of it,
As with a normal hard disk, there is also a flash memory card that does not assume removal or mounting when the power of the system body is on.

[0004] Such a flash memory card (hereinafter referred to as a flash memory) is reset only at the rising edge of an output signal of a power supply or the like, and becomes usable. Need to power off and on.

On the other hand, it is possible to incorporate such a flash memory storage device into various devices, store necessary data in the flash memory, take out the flash memory from the storage device, and read and use the data with another personal computer or the like. It is becoming necessary.

In recent years, for the purpose of energy saving, as a tool for managing power consumption at each office or factory, the power consumption of a power system being used is measured, and periodic measurement data is stored in a flash memory. Devices incorporating a microcomputer and a flash memory storage device, such as a power monitor capable of recording data in a computer, have also become widespread.

In such a flash memory storage device of a microcomputer built-in type device, data is read / written from / to a storage device handling a storage medium such as a flash memory which can be taken out and is reset at the rise of an output signal such as a power supply. A conventional storage device in the case (hereinafter referred to as access) will be described below.

FIG. 5 shows a block diagram of a conventional storage device. 100 is a control unit, 200 is a storage unit, 210 is a flash memory as a storage medium, 220 is a flash memory control unit, and 300 is a power supply unit.

In FIG. 6, the storage device having the configuration shown in FIG. 5 accesses the flash memory mounted on the storage unit for the first data, extracts the flash memory from the storage unit, and newly stores the flash memory in the storage unit. 7 shows a processing sequence when the second data is accessed to the flash memory mounted in the storage unit after the mounting.

[0010] Reference numeral 110 in FIG. 6 indicates an ON state or an OFF state of the power supplied from the power supply unit controlled by the control unit to the storage unit. The event of is shown.

First, the control unit turns on the power supply, and the flash memory is reset to be accessible.

Next, the control unit accesses the first data to the flash memory.

After the mounted flash memory is taken out of the storage unit, if a new flash memory is installed in the storage unit, the control unit outputs the progress of the removal and installation from the flash memory control unit. The detected input state detection signal is monitored by input monitoring.

Next, the control unit that detects the mounting of the flash memory controls the power supply unit to turn off and on the power supply to the flash memory, reset the flash memory, and reset the flash memory to access the next flash memory. Prepare.

[0015]

In the storage device described in the background art, the control unit 100 controls the flash memory 210.
It is necessary to monitor the mounting state detection signal output from the flash memory control unit 220 and to constantly grasp the progress and state of the removal and mounting of the flash memory.

If an error occurs in the input of the mounting state detection signal, the process of turning on and off the power supply to the flash memory 210 is not executed, and the flash memory 2 is turned off.
Thus, there is a problem that resetting of the flash memory 10 cannot be performed reliably, and accurate reading and writing of data to the flash memory 210 may not be performed.

The flash memory 210 is stored in the storage unit 200 while a current is flowing through the flash memory 210.
Flash memory 210 when attached to or removed from
If the current exceeds the specified value, it may be destroyed.
It is desirable to turn off the power supply to the flash memory 210 or to electrically disconnect the signal line connected to the flash memory 210 from the control unit side. In order to determine the timing for executing the process, a separate processing unit for interactively inputting instructions from the operator must be provided.

In the above description, when constructing a microcomputer-incorporated device, in addition to simplifying the control processing of the microcomputer for the storage device, the dialog processing is simplified so that the number of operations by the operator can be reduced. This is a problem when it is desired to simplify the control program for the interactive processing.

The present invention solves the above problems,
A storage device capable of accurately resetting a storage unit without detecting a state of the storage unit and reliably reading and writing data to the storage unit with a reduced load on a control program and easily provided. Aim.

[0020]

In order to solve the above-mentioned problems, a first storage device of the present invention comprises: a storage unit for storing data; a power supply unit for supplying power to the storage unit; And a control unit for controlling the unit, the power supply unit,
A configuration is provided in which power is supplied to the storage unit only when the storage unit is controlled.

According to a second storage device of the present invention, in addition to the first storage device, the storage unit comprises a flash memory and a flash memory control unit for controlling the flash memory, and the flash memory has a power The flash memory is reset when the output signal of the supply unit rises, and the flash memory can be taken out of the storage unit while at least power is not supplied from the power supply unit to the flash memory.

In the storage device according to a third aspect of the present invention, in addition to the second storage device, the control unit supplies power to the flash memory and then waits for a previously held waiting time before storing the power in the flash memory. Starts reading and writing data, and when reading and writing cannot be performed normally, has a function of retrying until reading and writing can be performed normally, updating the waiting time based on the waiting time and the retry period, and storing the flash memory. A configuration in which the waiting time is maintained until the unit is taken out of the unit.

[0023]

According to the first storage device of the present invention, data can be stored in the storage unit by supplying power from the power supply unit to the storage unit only when the storage unit is controlled. .

According to the second storage device of the present invention, the storage unit controls the storage unit including the flash memory and the flash memory control unit which are reset at the rise of the output signal of the power supply unit. Only when the power is supplied from the power supply unit to the storage unit, data can be stored in the storage unit and the flash memory can be taken out of the storage unit while power is not supplied from the power supply unit.

According to a third aspect of the present invention, when the control unit supplies power to the flash memory and starts reading or writing data to the flash memory after a lapse of a previously held waiting time, and when reading and writing cannot be performed normally, It is possible to retry until reading and writing can be normally performed, update the waiting time based on the waiting time and the retry period, and hold the waiting time until the flash memory is taken out of the storage unit.

Hereinafter, an embodiment of the present invention will be described.

(Embodiment) FIG. 1 is a block diagram of a storage device showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a processing sequence for a flash memory.

In FIG. 1, reference numeral 10 denotes a control unit,
0 while controlling the flash memory control unit 22 which is a component of the power supply unit 30 and the storage unit 20.
It reads and writes data from and to the flash memory 21 which is a component of the above. Reference numeral 20 denotes a storage unit, which includes a flash memory 21 which is a storage medium for storing data and a flash memory control unit 22 which controls the flash memory 21. Reference numeral 21 denotes a flash memory as a storage medium, which is connected to the control unit 10 via a flash memory control unit 22 and can be taken out of the storage unit 20;
It is reset at the rise of the output signal of the power supplied from the power supply unit 30. A flash memory control unit 22 is connected between the control unit 10 and the flash memory 21 and controls an access control signal line and a data signal line required when the control unit 10 accesses the flash memory 21. In accordance with an instruction of a signal line control signal input from the terminal 10, an electrical connection or disconnection is performed. Further, reference numeral 30 denotes a power supply unit for performing on / off control of power supply to the flash memory 21 in accordance with an instruction of a power control signal input from the control unit 10.

Here, the control unit 10 is a CP such as a microcomputer.
U, the flash memory 21 is a flash memory card or the like, the flash memory control unit 22 is a bidirectional or unidirectional buffer IC capable of high impedance control, and the power supply unit 30 is a DC power supply with on / off control of output. Is achieved.

In the storage device configured as described above, the first data is accessed to the flash memory 21 mounted on the storage unit 20 and the flash memory 2 is accessed.
1 from the storage unit 20 and then the flash memory 21
Alternatively, after another flash memory 21 is mounted on the storage unit 20, the operation of accessing the flash memory mounted on the storage unit 20 for the second time is performed by controlling on / off of the power supply to the flash memory 21. Will be described with reference to FIG. 1 and FIG.

Reference numeral 50 in FIG. 2 indicates an ON state or an OFF state of the power supplied from the power supply unit 30 controlled by the control unit 10 to the flash memory 21. Indicates the control event.

First, as an initial state, the flash memory 2 is transmitted from the control unit 10 through the flash memory control unit 22.
1 (hereinafter referred to as “access to the flash memory 21 from the control unit 10”), the control unit 10 issues a power-off instruction to the power supply unit 30 as a power control signal. In this state, power is not supplied from the power supply unit 30 to the flash memory 21, and an instruction to disconnect the signal line is issued from the control unit 10 to the flash memory control unit 22 as a signal line control signal. The data signal line and the access control signal line connecting the flash memory 21 and the control unit 10 are in a high impedance state and electrically disconnected. Here, the control unit 1 is connected to the data signal line.
The data 0 and the address to be written or read to / from the flash memory 21 are put on the flash memory 21, and the information of the control signal for controlling the timing is put on the access control signal line.

Next, when the first data is accessed by the control unit 10 in the flash memory 21, the control unit 10
Instructs the power supply unit 30 to supply power to the flash memory 21 via a power control signal, and
To the flash memory controller 2
2 instructs the signal line connection via the signal line control signal,
The flash memory 21 and the control unit 10 are electrically connected. At this time, the flash memory 21 is reset at the rising edge of the output signal of the power supply (power supply unit 30) being turned on, so that the access from the control unit 10 can be accepted.

The control unit 10 that has completed necessary access to the flash memory 21 instructs the power supply unit 30 to stop supplying power to the flash memory 21 via a power control signal, and supplies power to the flash memory 21. Is stopped, and a signal line disconnection instruction is issued to the flash memory control unit 22 via a signal line control signal, so that the flash memory 21 and the control unit 10 are electrically disconnected.

Next, while the flash memory 21 is electrically disconnected, the operator can take out the mounted flash memory 21 from the storage unit 20, and likewise remove the flash memory 21 from the storage unit 20. It can be attached to the storage unit 20. During this time, the control unit 10 does not need to perform any processing.

Next, in order to access the second data to the flash memory 21 mounted on the storage unit 20 as described above, it is necessary to access the first data to the flash memory 21 as described above. The same processing is repeated.

That is, when data access to the flash memory 21 is required, the control unit 10 only needs to repeat the simple processing for the power supply unit 30 and the flash memory control unit 22 as described above. Therefore, the control unit 1
0 can be realized with simple control while reducing the load of the program.

The flash memory 21 is stored in the storage unit 20.
When the control unit 10 is not accessing the flash memory 21, the power is not supplied to the flash memory 21, and the access control signal line and the data signal line are also disconnected from the control unit 10. In this state, the flash memory 21 can be taken out or mounted without giving an electrical stress to the flash memory 21.

Moreover, at this time, the control unit 10 can execute the flash memory 21 without detecting the mounting state or progress of the flash memory 21 at all.

In the case of the power monitor, since a high voltage is applied to the measurement data input section on the device main body side, the device is always used during the period other than the access period to the flash memory 21 as in the storage device of the present embodiment. When the main body is not energized, high-voltage noise coming from the measurement data input unit is applied to the flash memory 21 and the flash memory 2
1 can minimize the probability of destroying the data contents, and is excellent in noise resistance.

Further, in the case of the storage device of the present embodiment, since the power supply period to the flash memory 21 is the minimum required, the power consumed by the flash memory 21 is suppressed and the energy saving is excellent.

However, as described above, in the process in which the control unit 10 accesses data to the flash memory 21,
Even if the control unit 10 controls the power supply unit 30 to start supplying power to the flash memory 21, the control unit 10 continues to operate until the flash memory 21 is internally ready.
Cannot substantially write or read data.

For this reason, after starting the power supply to the flash memory 21, the control unit 10 must wait for a certain period of processing and then start accessing the flash memory 21.

Normally, the setup wait time of the flash memory (the time from when power is supplied to the flash memory to when normal data can be read and written) is 1
In the case of 50 msec to 800 msec), it is necessary to set the longest waiting time in consideration of all variations due to differences in manufacturers of the flash memories 21 to be used, variations in individual products, operating temperature conditions, and the like.

However, as described above, when the present storage device is applied to a device such as a power monitor that monitors the power consumption of the power system and periodically records the measured data in the flash memory 21, the storage interval of the measured data is changed. When the distance is long, the control range is very wide, ranging from several hours to about one second when the distance is short.

In this case, in order to shorten the storage interval, the setup waiting time (1
(Around 2 seconds) becomes a bottleneck.
A problem arises in that it is desired to reduce the waiting time of zero.

In order to solve this problem, in the storage device of the present embodiment, after the control unit 10 supplies power to the flash memory 21, the data stored in the flash memory 21 is passed after a waiting time which is held in advance. Reading and writing are started, and when reading and writing are not performed normally, retry is performed until reading and writing can be performed normally, the waiting time is updated based on the waiting time and the retry period, and the flash memory 21 is extracted from the storage unit 20. To be able to hold the waiting time.

FIG. 3 is an explanatory diagram of a processing sequence when the data is accessed to the flash memory 21 by the control unit 10, and FIG. 4 is a control unit 10 corresponding to the processing sequence of FIG.
It is a processing flowchart of.

In FIG. 3, reference numeral 60 denotes an ON state or an OFF state of the power supplied from the power supply unit 30 controlled by the control unit 10 to the storage unit 20. Indicates the control event.

First, an initial value (for example, 100 msec) T _W0 of the setup waiting time of the flash memory 21 previously stored in the control unit 10 is initialized to the waiting time T _W.

When it becomes necessary to access the flash memory 21 with data, the control unit 10 instructs the power supply unit 30 to supply power to the flash memory 21 via a power control signal, and (S1), and waits for processing for a waiting time T _W (S2).

Next, the control unit 10 controls the flash memory 21
Is accessed (S3), and whether or not access was successful
Is checked (S4), and if it cannot be accessed normally,
In this case, the waiting time increment ΔT (for example, 1
00 msec) with waiting time T _WAnd the waiting time T_WUpdate
New (S5).

Next, after waiting for the processing for the waiting time increase ΔT (S6), the access to the flash memory 21 is retried (S3), and it is checked whether or not the access was successful (S4). If access is possible, one data processing is terminated (S7).

In the above step (S4), if the access is not normally performed, the processing from step (S3) to step (S6) is repeated.

The control unit 10 executes the above-described step (S) every time data access to the flash memory 21 occurs.
Steps (S7) to 1) are executed.

In the case of the power monitor, this corresponds to a process of storing measurement data (a series of data such as system voltage, power consumption, and current consumption) at a regular time.

In spite of access to the same flash memory 21, data can be reliably read and written even if the setup wait time of the flash memory 21 becomes long due to a change in conditions such as a temperature change. .

By setting an upper limit value for the waiting time T _W , it is possible to add a function of determining that there is a failure in accessing the flash memory 21 when the waiting time reaches the upper limit value.

The waiting time T _W is the initial value of the setup waiting time of the flash memory 21 when the flash memory 21 recognizes that the flash memory 21 has been removed from or attached to the storage unit 20 through the interactive processing with the operator. T _W0 is reset to the waiting time T _W.

As a result, when the wait time of the newly mounted flash memory is shorter than that of the flash memory 21 used previously, the access can be performed in a shorter time by utilizing the characteristics. Becomes

The flash memory 21 is stored in the storage unit 2
In order to recognize that the flash memory 21 has been pulled out or mounted, there is a method in which the operator inputs the information through interactive processing. In addition, the mounting state of the flash memory 21 is monitored by inputting a mounting state detection signal. When a state in which access processing to the flash memory 21 does not occur for a certain period of time (for example, about three times the storage interval of the measurement data in the case of the power monitor) continues, the flash memory 21 It may be made to recognize that it was extracted from 20.

Further, the process of resetting the initial value T _W0 of the setup waiting time of the flash memory 21 to the waiting time T _W is performed for a fixed period (for example, in the case of the power monitor, about three times the storage interval of the measured data). Alternatively, the processing may be performed when the state in which the access processing to the flash memory 21 does not occur continues.

When the flash memory 21 is extracted, the setup waiting time may be set to the initial value T _W0 .

In the above manner, the flash memory 21 used can be accessed by automatically coping with the differences in the setup wait time of the flash memory 21 used by different manufacturers, the variations of individual products, and the variations in the operating temperature conditions. Regardless of the flash memory to be used, a highly reliable storage device that operates stably irrespective of characteristics can be provided.

Further, it is not necessary to uniformly lengthen the setup waiting time at the time of data access to the flash memory 21, and the data can be accessed with the shortest waiting time in the attached flash memory.

Thus, if the present storage device is applied to the above-described device such as the power monitor, it is possible to realize data measurement and storage processing repeatedly performed at shorter intervals.

In the case where a plurality of data accesses are performed without replacing the flash memory 21, the necessary access wait time for the flash memory 21 can be held during the second and subsequent data accesses. S
The number of retry accesses to the flash memory 21 in 3) is eliminated.

This is because, in the case of the above-described power monitor, since a high voltage is applied to the measurement data input section on the device main body side, the high-voltage noise coming from the measurement data input section causes the control section 10 to flash. During access to the memory 21, the probability of destroying the data contents already stored in the flash memory 21 can be minimized, and the reliability of the storage device can be improved.

Further, it is possible to prevent an inadvertent error from occurring at the time of retry access. Therefore, there is an effect of eliminating a possibility that data may be lost or an erroneous data may be written to the flash memory when an error occurs.

[0070]

As described above, according to the first storage device of the present invention, the control unit supplies power from the power supply unit to the storage unit only when controlling the storage unit. The supply period can be minimized, and a storage device which is excellent in energy saving and in which power consumption in the storage unit is suppressed can be realized.

According to the second storage device of the present invention,
To reset the flash memory with the output signal of the power supply unit and supply power to the flash memory from the power supply unit only when the flash memory is controlled,
A storage device that can accurately reset the flash memory and reliably read and write data to the flash memory without detecting the mounting state of the flash memory. Can be realized. Furthermore, since the device can be kept in a non-conductive state during periods other than the access period to the flash memory, a storage device with excellent noise resistance can be realized. Further, it is not necessary to separately provide a process for applying no electrical stress to the flash memory when the flash memory is mounted on or taken out of the storage unit, and a storage device with a reduced load on the control program can be realized. .

According to the third storage device of the present invention,
In addition to the effects of the second storage device, when the control unit cannot read / write the flash memory normally, the control unit retries until reading / writing becomes normal, and updates the waiting time based on the waiting time and the retry period. In addition to having a wait time until the flash memory is taken out of the storage unit, it can automatically deal with differences in flash memory setup wait time between manufacturers, variations in individual products, changes in operating temperature conditions, etc. A highly reliable storage device which operates stably regardless of the characteristics of the flash memory can be realized. Furthermore, there is no need to lengthen the setup wait time when accessing data to the flash memory, and data can be accessed with the shortest wait time in the flash memory used. By applying the device, it is possible to realize a storage device capable of performing data measurement and storage processing repeatedly performed at shorter intervals.

[Brief description of the drawings]

FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a processing sequence according to the embodiment;

FIG. 3 is an explanatory diagram of a processing sequence of retrying access to the flash memory according to the embodiment;

FIG. 4 is a flowchart of a processing sequence for retrying access to the flash memory according to the embodiment;

FIG. 5 is a block diagram of a conventional storage device.

FIG. 6 is an explanatory diagram of a processing sequence of a conventional storage device.

[Explanation of symbols]

 Reference Signs List 10 control unit 20 storage unit 21 flash memory 22 flash memory control unit 30 power supply unit

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G06F 12/16 310 G06F 1/00 330E 5B065 G06K 17/00 350B (72) Inventor Tomoyuki Yamagata 1006 Kadoma Kadoma, Kadoma, Osaka Address Matsushita Electric Industrial Co., Ltd. F-term (reference)

Claims (3)

[Claims] A storage unit configured to store data; a power supply unit configured to supply power to the storage unit; and a control unit configured to control the storage unit, wherein the power supply unit is controlled by the storage unit. A storage device that supplies power to the storage unit only when the power is supplied. 2. A storage unit comprising a flash memory and a flash memory control unit for controlling the flash memory, wherein the flash memory is reset at a rising edge of an output signal of a power supply unit, and the power supply unit supplies at least the flash memory 2. The storage device according to claim 1, wherein the flash memory can be taken out of the storage unit while no power is supplied to the flash memory. 3. A controller starts supplying data to the flash memory after supplying a power to the flash memory and after elapse of a waiting time held in advance, and if the data cannot be read and written normally, the data can be read and written normally. 3. The storage device according to claim 2, further comprising a function of retrying until the flash memory is updated, and updating the wait time based on the wait time and the retry period, and holding the wait time until the flash memory is removed from a storage unit. 4.