JP2002049536A - Device and method for memory control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for highly reliable memory control which allow the device having a memory mounted to operate normally without malfunctioning when source voltage is interrupted during the writing of data to the memory and later recovers to a specific value. SOLUTION: When a constant-voltage power source Vcc11 drops below a specific voltage while data are being written to an EEPROM 3, a reset circuit 4 outputs a 1st reset signal (RESET1) 12 to a CPU 1. The CPU 1 sends an emergency processing instruction to an EEPROM control circuit 2 and the EEPROM control circuit 2 sends an emergency processing instruction to the EEPROM 3 through a control line 15 to perform emergency processing so that the data writing to the EEPROM 3 is completed normally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, a memory control method, and a storage medium, and more particularly, to an EEPROM write control device, a write control method, and a storage medium in a device having an EEPROM, such as a personal computer or a printer. .

[0002]

2. Description of the Related Art Conventionally, personal computers, printers, and the like are provided with electrically rewritable ROMs, that is, EEPROMs (electrically erasable and programmable).
mmableread only memory) is provided.

[0003] The EEPROM is a non-volatile memory and is used for storing initial setting data of these devices and setting data for each user, since the data does not disappear even when the power is turned off.

[0004]

In the above apparatus,
In general, the timing at which the data is written to the EEPROM is often not understood by the user. Therefore, the user may turn off the power during the writing process.

[0005] For example, if a short-circuit condition (short interruption) of the power supply voltage occurs for a short period of time during writing to the EEPROM, or if the user accidentally turns off the power switch, the data being written may be lost. Is EEPR
In many cases, it is unclear whether the data was written to the correct address of the OM or not.

In these cases, if the data being written is not written to the correct address of the EEPROM, the disconnection state is restored and the power supply voltage returns to a predetermined value. Problems such as runaway and malfunction sometimes occurred.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a nonvolatile memory that can be used even if a voltage drop such as an instantaneous power interruption occurs while data is being written. After that, when the disconnection state is restored and the power supply voltage returns to the predetermined value, the device equipped with the memory control device does not malfunction and a normal write process capable of operating normally can be performed with high reliability. An object of the present invention is to provide a memory control device and a memory control method.

[0008]

According to an embodiment of the present invention, there is provided a memory control device having the following configuration. That is, the power supply voltage supplied to the memory and the memory control means is monitored, and when the voltage drops to the first voltage, a first alarm is output, and
Alarm means for outputting a second alarm when the voltage has dropped to a second voltage lower than the voltage, and instructing means for instructing the memory control means to execute an emergency process to the memory upon receiving the first alarm. And when the memory control means receives the instruction from the instruction means, executes the emergency processing with the memory.

Also, for example, the power supply voltage supplied to the memory and the memory control means is monitored, a first alarm is output when the voltage drops to the first voltage, and when the voltage drops to a second voltage lower than the first voltage. Alarm means for outputting a second alarm, instruction means for instructing the memory control means to execute an emergency process to the memory upon receiving the first alarm, and the memory control means Upon receiving the instruction, a determination unit that determines whether the memory has recognized the emergency process performed with the memory, and that the memory does not recognize the emergency process by the determination unit. When it is determined, there is provided a stopping means for stopping processing performed between the memory control means and the memory.

Further, for example, the emergency processing is one of data reading processing, data writing processing, data erasing, and program rewriting processing.

Also, for example, the processing performed between the memory control means and the memory is one of data reading processing, data writing processing, data erasing, and program rewriting processing. It is characterized by.

Further, for example, the power supply apparatus further comprises a suppression means for suppressing a decrease in the voltage when the supply of the power supply voltage is stopped.

Further, for example, the memory is a nonvolatile memory.

Further, for example, the memory is a serial or parallel EEPROM.

For example, a power supply voltage supplied to a memory and a memory control circuit is monitored, a first alarm is output when the power supply voltage decreases to a first voltage, and the power supply voltage further decreases to a second voltage lower than the first voltage. An output step of outputting a second alarm when the first alarm is received by the instruction circuit.
An instruction step of instructing the memory control circuit to execute an emergency process to the memory; and executing the emergency process with the memory when the memory control circuit receives the instruction from the instruction circuit. And an execution step.

Also, for example, the power supply voltage supplied to the memory and the memory control circuit is monitored, a first alarm is output when the voltage drops to the first voltage, and the power supply voltage further drops to a second voltage lower than the first voltage. An alarming step of outputting a second alarm when the instruction circuit receives the first alarm, an instruction step of instructing the memory control circuit to execute an emergency process to the memory, and the memory control circuit Upon receiving the instruction from the instruction circuit, a determining step of determining whether the memory has recognized the emergency process performed with the memory, and the memory recognizes the emergency process by the determining step. And a stopping step of stopping processing being performed between the memory control circuit and the memory when it is determined that the processing is not performed.

Also, for example, the emergency processing is one of data reading processing, data writing processing, data erasing, and program rewriting processing.

Further, for example, the processing performed between the memory control circuit and the memory is one of data reading processing, data writing processing, data erasing, and program rewriting processing. It is characterized by.

Further, for example, the method further comprises a suppressing step of suppressing the decrease when the supply of the power supply voltage is stopped.

Further, for example, the memory is a nonvolatile memory.

Further, for example, the memory is a serial or parallel EEPROM.

Also, for example, a storage medium storing a memory control program, the memory control program monitors a power supply voltage to be supplied to the memory and the memory control circuit, and when the power supply voltage decreases to a first voltage, An alarming step of outputting a first alarm, and further outputting a second alarm when the voltage drops to a second voltage lower than the first voltage, and when the instruction circuit receives the first alarm, the memory control circuit sends the first alarm to the memory. An instruction step of instructing to execute emergency processing, and an execution step of executing the emergency processing with the memory when the memory control circuit receives the instruction from the instruction circuit. And

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

In the following embodiment, an EEPROM write control device and an EEPROM write control method will be described, but the scope of the present invention is not limited to the described example.

[First Embodiment] [Circuit Configuration of EEPROM Write Control Device] First, a circuit configuration of an EEPROM write control device 50 to which the present invention is applied will be described with reference to FIG.

In FIG. 1, reference numeral 1 denotes a CPU for controlling an EEPROM writing control device 50, 2 denotes a control circuit of the EEPROM, 3 denotes an EEPROM, and 4 denotes a 5V constant voltage power supply Vcc11 supplied from a power supply circuit 5. Monitoring, when the constant voltage power supply Vcc11 drops below a predetermined voltage, a first reset signal (RESET ₁ ) 12 as shown in FIG.
Is output to the CPU 1 and the second reset signal (RESET
₂ ) A reset circuit for outputting 13 to the control circuit 2 of the EEPROM.

Reference numeral 6 denotes a plurality of decoupling capacitors connected to the power supply voltage (Vcc) and GND.

When transmitting to the EEPROM 3, the CPU 1 transmits a command signal to the EEPROM control circuit 2 via the bus and the control line 14. EEPROM control circuit 2
Receives the command signal from the CPU 1,
Command signal to the EEPROM 3 via the. [EE
Configuration of PROM Control Circuit and EEPROM] FIG.
2 is a block diagram showing a configuration and a connection relationship between an EEPROM control circuit 2 and an EEPROM 3 in FIG.

The EEPROM control circuit 2 has a CPU / IF
And a reset circuit 4 comprising a sequencer 22 and a sequencer 22.
Reset signal (RESET ₂ ) 1 output from
3. The system clock signal (S
CLK) 14a and a bus / control signal 14b.

The EEPROM control circuit 2 has an EEPROM
The ROM 3 and the four control lines shown in the figure, that is, a chip select signal (CS) 15a, a synchronization signal (SK) 15b,
Data-in signal (DI) 15c and data-out signal (D
O) 15d.

The EEPROM control circuit 2 is reset by a _second reset signal (RESET ₂ ) 13. Further, the EEPROM control circuit 2 performs communication with the EEPROM 3 specified by the bus / control signal 14b for four times.
Control lines (CS15a, SK15b, DI15c, D
Via O15d).

The EEPROM 3 is, for example, S-29530A manufactured by Seiko Instruments, which is a serial 3-wire EEPROM, and has a capacity of 16 K bits. A specific access method and the like will be described later.

[Voltage Change at Power-Off] Next, the power-supply voltage change at power-off and the output signal of the reset circuit will be described.

FIGS. 3A to 3C show voltage changes of the power supply voltage (Vcc) 11 input to the reset circuit 4 (FIG. 3).
(A)), a voltage change of a _first reset signal (RESET ₁ ) 12 which is an output signal of the reset circuit 4 (FIG. 3)
(B)) and a second reset signal (RESET ₂ ) 1
3 is a diagram showing a voltage change of FIG. 3 (FIG. 3C).

The power supply voltage (Vcc) 11 is, for example, 5
V, the voltage first reset signal (RESET ₁₎ 12 becomes true (L level) is the output signal of the reset circuit 4, for example, 4.7V, the voltage RESET ₂ 13 goes true (L level) , For example, 1.8V.

[0036] In the timing _{T 0} of FIG. 3, the cutting of the power supply occurs, the power supply voltage (Vcc) 12 shown in FIG. 3 (a)
Since the electric charge is stored in the decoupling capacitor 6, the voltage does not drop rapidly to 0 V but gradually decreases as shown in the figure.

[0037] Here, shown in the timing _{T 1} of the FIG. 3 (a), when the power supply voltage (Vcc) 12 is decreased to 4.7V, the first reset signal of the reset circuit 4 (RESET
₁ ) 12 is false (H level) as shown in FIG.
To true (L level).

[0038] Further, shown in the timing _{T 2} of the FIG. 3 (a), when the power supply voltage (Vcc) 12 is decreased to 1.8V, the second reset signal of the reset circuit 4 (RESET
₂ ) 13 is false (H level) as shown in FIG.
To true (L level).

In the present invention, as described above, the power supply voltage (Vcc) 12 is controlled so as to gradually decrease when the power supply is turned off, and the voltage when the power supply voltage (Vcc) 12 decreases is 4.7V.
And the two timings reaching 1.8V are reset circuit 4
Is used for the switch signal.

As a result, the EEPROM control circuit 2
Power supply voltage is suddenly cut off and the power supply voltage (Vcc)
12 falls to 4.7 V, the reset circuit 4 starts operating, and sends a first reset signal (RESE) to the CPU 1.
T ₁ ) 12 is transmitted.

The CPU 1 outputs the first reset signal (R
Upon receiving ESET ₁ ) 12, a predetermined instruction is immediately sent to the EEPROM control circuit 2, and the EEPROM control circuit 2 receiving this instruction completes various read / write processes being performed with the EEPROM 3. ,
Emergency processing at power-off can be completed.

[Operation of EEPROM] Next, the operation of the EEPROM 3 in the present embodiment will be described.

In the EEPROM 3, as will be described later with reference to FIGS.
After the signal 15a is set to "H", the data line (DI) 15c is fetched in synchronization with the rise of the control line (SK) 15b.
3 is input to the EEPROM 3 in the order of a start bit, an operation code, an address, and data.

[List of Emergency Instructions Provided in EEPROM] First, the instructions from the EEPROM control circuit 2 for the emergency processing when the power is turned off will be described with reference to FIG.

FIG. 4 is a list of instructions included in the EEPROM 3, and shows the contents of the start bit, the operation code, the address, and the data in each instruction.

For example, if the EEPROM control circuit 2
The READ instruction for reading the data in the ROM 3 includes a start bit: 1, an operation code: 10, and an address: A9 to
A0 is transmitted from the EEPROM control circuit 2, and in response to the READ command, the EEPROM 3
Returns the data: D15 to D0 to the EEPROM control circuit 2.

Further, the EEPROM control circuit 2 has an EEPROM
The WRITE instruction for rewriting the data of OM3 includes a start bit: 1, an operation code: 01, and an address: A9 in the figure.
This is performed by transmitting data: D15 to D0 to the EEPROM control circuit 2 following to A0.

Also, the EEPROM control circuit 2 has an EEPROM
The ERASE instruction for erasing the data of OM3 includes a start bit: 1, an operation code: 11, an address: A9 to
This is performed by transmitting A0 from the EEPROM control circuit 2.

Further, the EEPROM control circuit 2
The EWEN (program enable) instruction for rewriting the program in the ROM 3 includes a start bit: 1, an operation code: 00, an address: A9: 1, A8: 1, A7 to
This is performed by transmitting A0 from the EEPROM control circuit 2.

Further, the EEPROM control circuit 2
EWD that makes the program of EPROM3 unrewritable
The S (program disable) instruction includes a start bit: 1, an operation code: 00, an address: A9: 0,
A8: 0 is transmitted by transmitting A7 to A0 from the EEPROM control circuit 2.

In this EEPROM, the configuration is 1024 words ×
Since it is 16 bits, the address is, for example, A9 to A
For example, 10 bits of 0 and data are, for example, 1 of D15 to D0.
It shall be 6 bits.

In the case of a READ instruction or the like,
From the EEPROM 3 to the E via the data line (DO) 15d
The data is output to the EPROM control circuit 2 and, in the case of the WRITE instruction, the EEPROM is connected via the data line (DI) 15d.
The data is input from the control circuit 2 to the EEPROM 3.

[From the EEPROM control circuit to the EEPROM
5 to 7 show the EEPROM control circuit 2
FIG. 5 is a timing chart showing communication signals between the WR and the EEPROM 3; FIG.
In the case of an ITE instruction, FIG.
The figure shows the case of an ERASE instruction, EWEN instruction, and EWDS instruction other than the instruction. FIG. 8 is a state transition diagram showing the operation of the sequencer 22 of the EEPROM control circuit 2.

[Outline of Operation of Sequencer at Power-off] First, an outline of operation of the sequencer 22 at power-off will be described with reference to FIG.

First, in step S 0, when the second reset signal (RESET ₂ ) 13 (“H” level) is input, the sequencer 22 starts operating.

Next, the flow shifts to step S1, enters the IDLE state, and waits for a command from the CPU 1.
In step S1, the EEPROM 3 from the CPU 1
When an access command to access is received, the process proceeds to step S2.

In step S2, the state becomes the START state, and the control signal (CS) 15a and the control signal (SK) 15
b, operate the data line (DI) 15c. That is,
The control signal (CS) 15a is set to “H” level, the control signal (SK) 15b outputs a synchronization signal, and the data line (D
I) After the start bit is output from 15c, the state shifts to the OPECODE state in step S3.

In step S3, each operation code corresponding to the instruction from the CPU 1 is output to the data line DI15c, and then the state shifts to the ADDRESS state in step S4. That is, in the case of a READ instruction, “10” is
At the time of the RITE instruction, "01" is read, and READ and WR
In the case of an instruction other than ITE, "11" or "00" is output.

In step S4, each address according to the command from CPU1 is output from data line DI15c, and the state shifts to each state according to the command from CPU1.

That is, the ADDRESS of step S4
If the state is a WRITE instruction, the addresses A9 to A0 are output, and the state shifts to the WRITE state in step S6. In step S6, the data D15 to be written to the EEPROM 3
ＤD0 is output, and then the process goes to the END state in step S7.

If the ADDRESS state in step S4 is a READ instruction, the address A9 to A0 is output, and the flow shifts to the READ state in step S5. In step S5, the data stored in the EEPROM 3 is output to the data line (DO) 15d, and then the process shifts to the END state in step S7.

Also, the ADDRESS state in step S4 is an instruction other than READ and WRITE, for example, ER
In the case of the ASE instruction, addresses A9 to A0 are output, and E
In the case of the WEN instruction, addresses 1, 1, A7 to A0 are output. In the case of the EWDS instruction, the addresses 0, 0, A7 to A7 are output.
A0 is output, and a transition is made directly from the ADDRESS state to the END state (step S7).

In the END state of step S7, the control signal (CS) 15a, the control signal (SK) 15b and the data line (DI) 15c are all false ("L" level),
After the access to the EPROM 3 is completed, step S
Return to the IDLE state of 1.

In the case of a READ instruction, step S7
In the END state, the data read from the EEPROM 3 is reported to the CPU 1 via the bus / control signal 14b.

Next, a detailed operation of each instruction will be described with reference to FIGS.

[READ Instruction] FIG. 5 is a timing chart showing the operation of the sequencer 22 of the EEPROM control circuit 2 at the time of the READ instruction.

First, at a timing T1, the CPU 1
When an address to be read from the controller and a READ instruction are instructed, the sequencer 22 receives the instruction and receives a timing T
2, the state shifts from the IDLE state to the START state, the control line (CS) 15a is set to "H", and the data line (D
I) A start bit "1" is output to 15c, and the control line (SK) 15b rises.

Next, the sequencer 22 operates at the timing T3
At the time, the state shifts to the OPECODE state, and the control line (S
K) Output the opcode ("10") of the READ instruction while synchronizing with 15b.

Next, the sequencer 22 operates at the timing T4
At the ADDRESS state, the control line (S
K) Output the addresses to be accessed (A9 to A0) output from the CPU 1 while synchronizing with 15b.

At timing T5, the EEPROM 3 recognizes the given command at the rising edge of the control line (SK) 15b at the last address A0 (13th of SK15b), and firstly puts "" on the data line (DO) 15d. 0 ”is output and the control line (SK) 15 that is continuously input
Data D15 to D0 are output in synchronization with the rise of b.

Next, the sequencer 22 operates at the timing T6.
Transitions to the READ state, and the data line (DO) 1
The data (D15 to D0) output to 5d is received.

Next, the sequencer 22 operates at timing T7.
Transitions to the END state at
The data read from M3 is reported via the bus / control signal 14b, and the control signal (CS) 15a, the control signal (SK) 15b and the data line (DI) 15c are all false ("L" level). The access to the EEPROM 3 is terminated, and the state returns to the IDLE state.

[WRITE Command] FIG. 6 is a timing chart showing the operation at the time of the WRITE command. The description of the parts common to FIG. 5 is omitted, and only the differences will be described.

The difference between the WRITE instruction in FIG. 6 and the READ instruction in FIG. 5 is that the operation code output as described above is “1”.
0 ", which is different from" 01 "of the WRITE instruction, and that at the timing T6, the state shifts from the ADDRESS state to the WRITE state, and the data designated by the CPU 1 is sequentially output from the data line (DI) 15c.

Further, END at timing T7
In the state, the control signal (CS) 15a and the control signal (SK)
15b and all data lines (DI) 15c are false ("L").
Level), the access to the EEPROM 3 is terminated, and the state returns to the IDLE state (1).

[ERASE, EWEN, EWDS instructions]
FIG. 7 is a timing chart showing an instruction other than the READ instruction and the WRITE instruction, that is, any one of the ERASE instruction, the EWEN instruction, and the EWDS instruction. FIG.
The description of the parts common to the above is omitted, and only the differences will be described.

The difference from FIGS. 5 and 6 is that the output opcode is “00” or “11” as described above,
It is different from “10” of the READ instruction and “01” of the WRITE instruction.
The state directly shifts to the END state without shifting from the S state to the READ state or the WRITE state, and the control signal (CS) 15
a, the SK 15b and the data line (DI) 15c are all false ("L" level) to terminate the access to the EEPROM 3 and return to the IDLE state at timing T7.

[Second Embodiment] Hereinafter, a second embodiment of the present invention will be described in detail.

[Circuit Configuration of EEPROM Writing Control Device] FIG. 9 is a block diagram showing a circuit configuration of an EEPROM writing control device 100 according to the second embodiment.

The basic configuration used in the second embodiment is the same as that of the first embodiment described with reference to FIG. The description will be omitted, and only different points will be described.

[Outline of Sequencer Operation at Power-Down] In FIG. 9, the second embodiment is different from the first embodiment in that an emergency process at power-off is performed in the first embodiment. Then, a first reset signal (RESET ₁ ) 12 which is an output signal of the reset circuit 4 is input to the CPU 1 and the CPU 1 transmits an emergency process at the time of power-off to the EEPROM control circuit 2 so that the power-off at the time of power-off is performed. Emergency processing has begun.

On the other hand, the EEPR according to the second embodiment
In the OM write control device 100, both the first reset signal (RESET ₁ ) 12 and the second reset signal (RESET ₂ ) 13, which are output signals of the reset circuit 4, are simultaneously input to the EEPROM control circuit 102.

Therefore, the EEPROM control circuit 102
Is the output signal of the reset circuit 4 and the first reset signal (R
In response to ESET ₁ ) 12, it becomes possible to more quickly respond to emergency processing when the power is turned off.

Therefore, the EEPROM control circuit 102 has a command recognition timing for identifying the first reset signal (RESET ₁ ) 12 and the second reset signal (RESET ₂ ) 13 which are two output signals from the reset circuit 4. A determination unit 23 is provided.

[Configuration of EEPROM Control Circuit and EEPROM] FIG. 10 shows the EEPROM control circuit 1 in FIG.
FIG. 2 is a block diagram showing a configuration and a connection relationship between the EEPROM 02 and an EEPROM 3.

The EEPROM control circuit 102 has a CPUI
It comprises an F unit 21, a sequencer 122, and an instruction recognition timing discrimination unit 23.

The EEPROM control circuit 102 has two reset signals, ie, the first reset signal output from the reset circuit 4.
, A reset signal (RESET ₁ ) 12 and a second reset signal (RESET ₂ ) 13, a system clock signal (SCLK) 14 a and a bus / control signal 14 b supplied from the CPU 101.

That is, the EEPROM control circuit 102 is reset by the second reset signal (RESET ₂ ) 13, and accesses the EEPROM 3 specified by the bus / control signal 114 b by four control lines (CS 15).
a, SK15b, DI15c, DO15d).

Further, the instruction recognition timing determining section 23
When the first reset signal (RESET ₁ ) 12 is true (“L”)
Level), and the sequencer 122 determines to continue or stop accessing the EEPROM 3 accordingly.

[Overview of Sequencer Operation] FIG.
FIG. 10 is a state transition diagram illustrating an operation of the sequencer 122 according to the embodiment of the present invention. The operation is the same as that in FIG. Therefore, states indicating the same operation are denoted by the same step numbers, description thereof will be omitted, and only differences will be described below.

The difference from FIG. 6 is that the STA in step S12
In the RT state, the OPECODE state in step S13, and the ADDRESS state in step S14, the first reset signal (RESET) for emergency processing at the time of power-off is performed.
₁ ) The processing when 12 is input is added.

The START state in step S12, the OPECODE state in step S13, and the AD state in step S14
In the DRESS state, the power supply voltage indicates a disconnected state.
When the first reset signal (RESET ₁ ) 12 is true (“L”)
Level), the STOP of step S18 is immediately performed.
Transition to the state, and execute the STOP process.

Next, with reference to FIG. 12, a specific description will be given of the processing when the power supply voltage is cut off during the write processing to the memory (ADDRESS state in step S14).

[Process during execution of WRITE instruction: ADDR]
ESS state] FIG. 12 is the ADDRESS state of step S14 in the WRITE instruction execution timing _{T 5,} power is an instantaneous interruption or disconnection, the first reset signal (RESET ₁₎ 12 is true ( "L" level) 6 is a timing chart showing an operation of the EEPROM control circuit 2 when the operation becomes abnormal.

First, the normal operation will be described.

At timing T ₁ , when an address to be written and a WRITE instruction are specified by the CPU 101, the sequencer 122 of the EEPROM control circuit 102
At timing _{T 2,} STA from the IDLE state
Move to the RT state.

When the sequencer 122 enters the START state, the sequencer 122 sets the control line (CS) 15a to "H" and sets the data line DI
A start bit is output to the control line (SK) 15c.
from launching a b, in the timing _{T 3,} OPE
Move to the CODE state.

Next, the sequencer 122 operates as follows:
It becomes the E state, since the output WRITE instruction opcode ( '01') in synchronism with the control line (SK) 15b, at the timing _{T 4,} the process proceeds to ADDRESS state.

Next, the sequencer 122 outputs
In the S state, addresses to be accessed (A9 to A0) output from the CPU 101 are output in synchronization with the control line (SK) 15b.

However, when the EEPROM 3 stores the given W
It recognizes RITE instruction in (control line (SK) rise timing of 15b at the time of the last address A0) before the timing _{T 5,} the first reset signal (RESE
Since T ₁ ) 12 has become true (“L” level), the sequencer 122 shifts to a STOP state in which emergency processing is performed.

When the sequencer 122 enters the STOP state, the control signal (CS) 15a and the control signal (SK) 15b
Then, all the data lines (DI) 15c are set to false (“L” level), and the access to the EEPROM 3 is terminated.
After stops transmission of RITE instructions, at timing _{T 7,} shifts to IDLE state.

As a result, it is possible to prevent an erroneous write to the EEPROM when the WRITE instruction is executed, and to eliminate a malfunction or the like of the device at the time of subsequent restart and improve the reliability of the device. be able to.

Also, WRITE state, READ state, E
In the ND state, it goes without saying that the same operation as that described in the first embodiment is performed.

In the first and second embodiments described above, the EEPROM is described as a serial three-wire type. However, it is needless to say that the present invention is not limited to this. A wire type or a parallel type may be used. Further, the present invention is not limited to the EEPROM, but may be any nonvolatile memory whose contents can be rewritten by a special device or method.

[0105]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), a device including one device (for example, Copy machine, facsimile machine, etc.).

Further, an object of the present invention is to supply a storage medium (or a recording medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or an apparatus, and a computer (a computer) of the system or the apparatus Or a CPU or MPU) reads out and executes the program code stored in the storage medium,
Needless to say, this is achieved.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the operating system (OS) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. Needless to say, the CPU included in the function expansion card or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the above-described flowcharts (shown in FIGS. 8 and 11).

[0111]

As described above, according to the present invention,
If the power supply voltage supplied to the memory controller during data writing to the memory is cut off, such as an instantaneous interruption, and then the disconnected state recovers and the power supply voltage returns to a predetermined value, the above memory and memory controller are installed. Device does not malfunction,
A highly reliable memory control device and memory control method that can operate normally can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an EEPROM write control device according to an embodiment of the present invention.

FIG. 2 shows an EEPROM control circuit and an EEPROM in FIG. 1;
It is a figure showing composition and connection relation of OM.

FIG. 3 is a diagram showing a power supply voltage (Vc) when power is turned off according to the embodiment;
c), output signals RESET ₁ and RES of reset circuit 4
Is a graph showing changes in ET _2.

FIG. 4 is a list of instructions included in the EEPROM of the embodiment.

FIG. 5 is a diagram showing an EEPROM control circuit according to the present embodiment;
6 is a timing chart showing access to an OM.

FIG. 6 illustrates an EEPROM control circuit according to an embodiment of the present invention.
6 is a timing chart showing access to an OM.

FIG. 7 illustrates an EEPROM control circuit according to an embodiment of the present invention.
6 is a timing chart showing access to an OM.

FIG. 8 is a state transition diagram showing a sequencer operation of the EEPROM control circuit.

FIG. 9 is a diagram showing a configuration of an EEPROM writing control device of the present embodiment.

FIG. 10 shows an EEPROM control circuit and an EEPROM in FIG. 9;
FIG. 2 is a diagram illustrating a configuration and connection relationship of a ROM.

FIG. 11 is a state transition diagram showing the operation of the sequencer of the EEPROM control circuit.

FIG. 12 illustrates an EEPROM control circuit according to the present embodiment.
6 is a timing chart showing access to a ROM.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 CPU 2 EEPROM control circuit 3 EEPROM 4 Reset circuit 5 Power supply circuit 6 Decoupling capacitor 11 Constant voltage power supply Vcc 12 Reset signal ₁ 13 Reset signal ₂ 14 Bus and control line 15 Control line 50 EEPROM writing control device

Claims (15)

[Claims] 1. A power supply voltage supplied to a memory and a memory control means is monitored, a first alarm is output when the voltage drops to a first voltage, and a second alarm lower than the first voltage is output.
An alarm unit that outputs a second alarm when the voltage drops to a voltage; and an instruction unit that instructs the memory control unit to execute an emergency process to the memory when the first alarm is received. A memory control device, wherein when the control means receives the instruction from the instruction means, executes the emergency processing with the memory. Monitoring a power supply voltage supplied to the memory and the memory control means, outputting a first alarm when the voltage drops to a first voltage, and outputting a first alarm when the voltage drops to a second voltage lower than the first voltage. (2) alarm means for outputting an alarm; instruction means for instructing the memory control means to execute emergency processing to the memory upon receiving the first alarm; and the memory control means Upon receiving the instruction, a determination unit that determines whether the memory has recognized the emergency process to be performed with the memory; and a determination that the memory does not recognize the emergency process by the determination unit. A memory control unit, comprising: a memory control unit that stops processing performed between the memory control unit and the memory when the memory control unit performs the process. 3. The method according to claim 1, wherein the emergency processing is one of data reading processing, data writing processing, data erasing, and program rewriting processing. Memory controller. 4. A process performed between the memory control means and the memory is one of a data read process, a data write process, a data erase process, and a program rewrite process. 3. The memory control device according to claim 2, wherein: 5. The memory control device according to claim 1, further comprising a suppression unit that suppresses a decrease in the voltage when the supply of the power supply voltage is stopped. 6. The memory control device according to claim 1, wherein the memory is a nonvolatile memory. 7. The memory control device according to claim 1, wherein the memory is a serial or parallel EEPROM. 8. A power supply voltage supplied to a memory and a memory control circuit is monitored, a first alarm is output when the power supply voltage drops to a first voltage, and the power supply voltage further drops to a second voltage lower than the first voltage. An output step of occasionally outputting a second alarm; an instruction step of instructing the memory control circuit to execute emergency processing on the memory when the instruction circuit receives the first alarm; Executing the emergency processing with the memory upon receiving the instruction from the instruction circuit. 9. A power supply voltage supplied to the memory and the memory control circuit is monitored, a first alarm is output when the voltage drops to a first voltage, and a second alarm lower than the first voltage is output.
An alarming step of outputting a second alarm when the voltage drops to a voltage; an instruction step of instructing the memory control circuit to execute an emergency process to the memory when the instruction circuit receives the first alarm; When the control circuit receives the instruction from the instruction circuit, a determining step of determining whether the memory has recognized the emergency process performed with the memory; and A memory control method, comprising: when it is determined that the processing is not recognized, stopping the processing being performed between the memory control circuit and the memory. 10. The method according to claim 8, wherein the emergency processing is one of data reading processing, data writing processing, data erasing, and program rewriting processing. Memory control method. 11. The process performed between the memory control circuit and the memory is one of a data read process, a data write process, a data erase process, and a program rewrite process. The memory control method according to claim 9, wherein: 12. The memory control method according to claim 8, further comprising a suppression step of suppressing the decrease when the supply of the power supply voltage is stopped. 13. The memory according to claim 8, wherein the memory is a nonvolatile memory.
The memory control method according to the paragraph. 14. The memory according to claim 8, wherein said memory is a serial or parallel EEPROM.
The memory control method according to claim 13. 15. A storage medium storing a memory control program, wherein the memory control program monitors a power supply voltage supplied to a memory and a memory control circuit, and when the power supply voltage decreases to a first voltage, the first memory control program monitors a first voltage. An alarming step of outputting an alarm and outputting a second alarm when the voltage drops to a second voltage lower than the first voltage, and when the instruction circuit receives the first alarm, the memory control circuit sends an emergency signal to the memory. An instruction step of instructing to execute processing, and an execution step of executing the emergency processing with the memory when the memory control circuit receives the instruction from the instruction circuit. Storage medium storing a memory control program to be executed.