JP2943867B1 - Sequence controller - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To improve reliability of sequence control information of an electrically rewritable nonvolatile memory circuit by providing a write control circuit. SOLUTION: A power control circuit section 4 detects a memory write command transmitted from a host control device and outputs a write command identification signal 31, and a memory control circuit section 3 outputs a write control signal 30 when a memory write command is detected. Output. The sequence control circuit unit 5 outputs the write inhibit signal 32 at the start of the sequence control, and releases the write inhibit signal 32 when receiving the memory write command. After receiving the write command identification signal 31 from the power supply control unit 4, the write control circuit 6 outputs a write inhibit signal 32 from the sequence control circuit unit 3.
Is released and the rewrite execution signal 35 is output to the electrically rewritable nonvolatile memory circuit 2 only when the write control signal 30 from the memory control circuit unit 3 is input.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence controller, and more particularly to a sequence controller employing a microprogram system.

[0002]

2. Description of the Related Art Conventionally, a sequence control device has been constituted by a very complicated hardware circuit using a lot of logic circuit elements to control various complicated sequences. A microprogram type sequence control device which is provided in a circuit and performs various controls according to the sequence control information has been used (for example, Japanese Patent Application Laid-Open No. 4-8843).
No. 4 gazette).

However, in a conventional sequence control device,
It is very difficult to replace the control memory circuit when changing the sequence control information. For this reason, the sequence control information is stored in the electrically rewritable nonvolatile memory circuit, and the sequence control information is transferred from the low-speed electrically rewritable nonvolatile memory circuit to the high-speed volatile memory circuit at the time of start-up. When information is changed, a method of rewriting the sequence control information of the electrically rewritable nonvolatile memory circuit is adopted.

[0004]

The above-described conventional sequence control apparatus has a problem that the sequence control information of the electrically rewritable nonvolatile memory circuit is easily changed due to a malfunction. The reason is that the sequence control information is rewritably stored in the electrically rewritable nonvolatile memory circuit.

An object of the present invention is to provide an electrically rewritable nonvolatile memory circuit by providing a write control circuit for preventing sequence control information of the electrically rewritable nonvolatile memory circuit from being changed due to malfunction or the like. To provide a sequence control device that improves the reliability of the sequence control information.

[0006]

According to the present invention, there is provided a sequence control apparatus comprising: an electrically rewritable nonvolatile memory circuit; a memory circuit for a sequence control circuit; and an electrically rewritable nonvolatile memory circuit when power is turned on. A memory control circuit that transfers the sequence control information to the sequence control circuit unit memory circuit and writes the sequence control information to the electrically rewritable nonvolatile memory circuit in response to a memory write command from a higher-level device; A sequence control device that controls a sequence operation based on sequence control information of the memory circuit for the sequence control circuit unit, wherein the sequence control information of the electrically rewritable nonvolatile memory circuit is rewritten. The write inhibit signal from the sequence control circuit It is divided, with a write control circuit for outputting a rewriting execution signal to the electrically rewritable type non-volatile memory circuit only when the write control signal from the memory control circuit section is input.

A sequence control device according to the present invention is a sequence control device employing a microprogram system, wherein the electrically rewritable nonvolatile memory circuit for holding sequence control information and the electrically rewritable nonvolatile memory circuit when power is turned on. A memory circuit for a sequence control circuit unit to which the sequence control information read from the non-volatile memory circuit is written, a memory write command transmitted from a higher-level control device, and a write command identification signal output to output the memory write command; A power supply control circuit section via a memory address and new sequence control information transmitted subsequently, and transfer of sequence control information from the electrically rewritable nonvolatile memory circuit to the sequence control circuit section memory circuit, and Electrically rewritable nonvolatile memory circuit A memory control circuit for writing and reading the contents of an arbitrary address of the memory circuit for the sequence control circuit, and outputting a write control signal when the memory write command is detected; and The next control means is determined according to the sequence control information read from the memory circuit for the sequence control circuit unit and the control state signal read from the lower controlled unit, and a control instruction is issued to the lower controlled unit via a control instruction signal. And a sequence control circuit unit that outputs a write inhibit signal at the start of sequence control and releases the write inhibit signal when a memory write instruction is received, and after receiving a write instruction identification signal from the power supply control circuit unit, The write inhibit signal from the control circuit is released,
A write control circuit that outputs a rewrite execution signal to the electrically rewritable nonvolatile memory circuit only when a write control signal is input from the memory control circuit unit.

According to the sequence control device of the present invention, when the sequence control information of the electrically rewritable nonvolatile memory circuit is changed, a write control signal from the memory control circuit and a write inhibit signal from the sequence control circuit are changed. Is received by the write control circuit. The write control circuit issues a rewrite execution signal to the electrically rewritable nonvolatile memory circuit only when the write inhibit signal from the sequence control circuit is released and a write control signal is input from the memory control circuit. Is output.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of a sequence control device according to one embodiment of the present invention. The sequence control device according to the present embodiment includes a sequence control circuit section memory circuit (execution memory) 1, an electrically rewritable nonvolatile memory circuit (storage memory) 2,
The memory control circuit unit 3, the power supply control circuit unit 4, the sequence control circuit unit 5, and the write control circuit 6 constitute the main part.

The memory circuit 1 for the sequence control circuit section includes:
The memory control circuit unit 3 is connected by an execution memory address signal 11, an execution memory data signal 12, and an execution memory control signal 13.

Electrically rewritable nonvolatile memory circuit 2
Are connected to the memory control circuit unit 3 by a storage memory address signal 14, a storage memory data signal 15, and a storage memory control signal 16.

The power supply control circuit section 4 is connected to a higher-level control device (not shown) by a serial data input signal 36, a serial data input control signal 37, a serial data output signal 38, and a serial data output control signal 39. Completion signal 2
1, the control data input signal 22, the control data input control signal 23, the control data output signal 24, and the control data output control signal 25 are connected to the memory control circuit unit 3 and the write command identification signal 31 is connected to the write control circuit 6. ing.

The sequence control circuit section 5 is connected to a lower controlled section (not shown) by a control instruction signal 33 and a control state signal 34, and stores a memory address signal 27, a memory data signal 28, a memory control signal 29, and a control start signal. It is connected to the memory control circuit section 3 by an instruction signal 26 and connected to the write control circuit 6 by a write inhibit signal 32.

The write control circuit 6 has a write control signal 30
Is connected to the memory control circuit unit 3, is connected to the power supply control circuit unit 4 by a write command identification signal 31, and is connected to the sequence control circuit unit 5 by a write inhibit signal 32. The write control circuit 6 is connected to the electrically rewritable nonvolatile memory circuit 2 by a rewrite execution signal 35.

FIG. 2 is a circuit block diagram showing a more detailed configuration of the memory control circuit unit 3. Memory control circuit 3
Are a control data input / output control circuit 301, an instruction determination execution control circuit 302, and a memory address signal switching circuit 30
3, a memory data signal switching circuit 304, and a memory control signal switching circuit 305.

The control data input / output control circuit 301 includes a control data input signal 22, a control data input control signal 23, a control data output signal 24, and a control data output control signal 2.
5 is connected to the power supply control circuit unit 4. Also,
The control data input / output control circuit 301 is connected to the instruction determination execution control circuit 302 by a control signal 311.

The instruction discrimination execution control circuit 302 is connected to the power supply control circuit section 4 by the power-on completion signal 21, is connected to the sequence control circuit section 5 by the control start instruction signal 26, and stores the memory address signal 14 for storage, It is connected to the electrically rewritable nonvolatile memory circuit 2 by a memory data signal 15 and a storage memory control signal 16. The instruction discrimination execution control circuit 302 outputs the memory address signal 14 for storage and the memory data signal 1 for storage.
5 and an execution memory control signal 312 are connected to a memory address signal switching circuit 303, a memory data signal switching circuit 304, and a memory control signal switching circuit 305, respectively. Signal switching circuit 304 and memory control signal switching circuit 3
05 and connected to the write control circuit 6 by a write control signal 30.

The memory address signal switching circuit 303
It is connected to the sequence control circuit section memory circuit 1 by an execution memory address signal 11, and is connected to the sequence control circuit section 5 by a memory address signal 27.

The memory data signal switching circuit 304 is connected to the sequence control circuit memory 1 by the execution memory data signal 12 and to the sequence control circuit 5 by the memory data signal 28.

The memory control signal switching circuit 305 is connected to the sequence control circuit memory 1 by the execution memory control signal 13, and is connected to the sequence control circuit 5 by the memory control signal 29.

FIG. 3 is a timing chart showing the operation of the sequence control device according to the present embodiment.

Next, the operation of the sequence control device according to the present embodiment thus configured will be described with reference to FIGS.

First, the normal operation will be described.

During normal operation, in the memory control circuit unit 3, the instruction discrimination execution control circuit 302
By detecting that the power-on completion signal 21 has been enabled ("L"), it is determined that power-on has been completed, and the signal switching signal 313 is enabled.

When the signal switching signal 313 is enabled, the memory address signal switching circuit 303 outputs the memory address signal 14 for storage and the memory address signal 11 for execution.
And connect.

The memory data signal switching circuit 304
Connects the storage memory data signal 15 and the execution memory data signal 12.

Further, a memory control signal switching circuit 305
Connects the execution memory control signal 312 and the execution memory control signal 13.

Next, the instruction discrimination execution control circuit 302 sets the address “0” in the storage memory address signal 14 and controls the sequence of the electrically rewritable nonvolatile memory circuit 2 by the storage memory control signal 16. The information is read out via the storage memory data signal 15. At this time, the execution memory address signal 11 is also changed from the storage memory address signal 14 to the memory address signal switching circuit 30.
3, the address “0” is set.

Subsequently, the instruction determination execution control circuit 302
The data read out from the electrically rewritable nonvolatile memory circuit 2 via the storage memory data signal 15 is output to the execution memory data signal 12 via the memory data signal switching circuit 304, and is output by the execution memory control signal 312. Writing is performed to the sequence control circuit section memory circuit 1 via the memory control signal switching circuit 305 and the execution memory control signal 13.

Thereafter, the instruction discrimination execution control circuit 302 repeats the same operation by incrementing the address by "1", and repeats until the last address of the memory address.

After all the sequence control information of the electrically rewritable nonvolatile memory circuit 2 has been written into the sequence control circuit section memory circuit 1 by this series of operations, the instruction determination execution control circuit 302 issues a signal switching signal. 3
13 is disabled ("H").

When the signal switching signal 313 is disabled, the memory address signal switching circuit 303 connects the memory address signal 27 to the memory address signal 11 for execution.

The memory data signal switching circuit 304
Are the memory data signal 28 and the execution memory data signal 1
2 is connected.

Further, a memory control signal switching circuit 305
Connects the memory control signal 29 and the execution memory control signal 13.

Next, the instruction determination execution control circuit 302 enables the control start instruction signal 26.

When the control start instruction signal 26 is enabled, the sequence control circuit 5
7 and the memory control signal 29, the next control means is determined according to the sequence control information read from the memory circuit 1 for the sequence control circuit unit and the contents of the control state signal 34 read from the lower controlled unit (not shown). The control instruction is given to the lower controlled part via the control instruction signal 33.

At this time, at the beginning of the sequence control information of the memory circuit 1 for the sequence control
2 is written in advance, the sequence control circuit unit 5 disables the write inhibit signal 32 when starting the sequence control.
Even when the write control signal 30 is enabled, the write control circuit 6 protects the electrically rewritable nonvolatile memory circuit 2 from being written to because the rewrite execution signal 35 is not enabled. (Figure 3
(See broken lines in (b) and (d).)

Next, an operation when the sequence control information of the electrically rewritable nonvolatile memory circuit 2 is rewritten from the host controller will be described.

As described above, after the sequence control information of the electrically rewritable nonvolatile memory circuit 2 is transferred to the memory circuit 1 for the sequence control circuit section, the storage memory address signal 14, the storage memory data Since the signal 15 and the execution memory control signal 312 are separated from the execution memory address signal 11, the execution memory data signal 12, and the execution memory control signal 13, respectively, the electrically rewritable nonvolatile memory circuit 2 , Which is substantially unused. In this state, even if the sequence control information of the electrically rewritable nonvolatile memory circuit 2 is rewritten, the operation of the sequence control device is not hindered. Therefore, at this time, the sequence control information of the electrically rewritable nonvolatile memory circuit 2 is rewritten.

A memory write command is issued from the host controller to the serial data input signal 36 and the serial data input control signal 37.
The power supply control circuit unit 4 detects this, and enables the write command identification signal 31 (see FIG. 3A).

Next, the power supply control circuit unit 4 transmits a memory write command to the memory control circuit unit 3 via the control data input signal 22 and the control data input control signal 23.

The memory control circuit 3 transmits a memory write command to the sequence control circuit 5 via the memory data signal 28.

Upon receiving the memory write command, the sequence control circuit section 5 disables the write inhibit signal 32 to enable writing to the electrically rewritable nonvolatile memory circuit 2 (FIG. 3B). reference).

Next, the sequence control circuit section 5 transmits to the memory control circuit section 3 via the memory address signal 27 that the rewriting of the electrically rewritable nonvolatile memory circuit 2 has been permitted.

The memory circuit controller 3 changes the internal state to a memory rewrite executable state, and enables the write control signal 30 (see FIG. 3C).

The write control circuit 6 receives the write control signal 3
0, write command identification signal 31 and write inhibit signal 32
It is confirmed that rewriting of the electrically rewritable nonvolatile memory circuit 2 is permitted by these three signals, and the rewriting execution signal 35 is enabled (see FIG. 3D).

As a result, the electrically rewritable nonvolatile memory circuit 2 enters a memory rewriting executable state.
The memory control circuit unit 3 writes sequence control information into the electrically rewritable nonvolatile memory circuit 2.

More specifically, the control data input / output control circuit 301 of the memory control circuit unit 3 transmits the received information to the control signal 3
11 to the instruction determination execution control circuit 302, the instruction determination execution control circuit 302 determines information obtained following the memory write instruction as a rewrite address and outputs it to the storage memory address signal 14, and further subsequently The obtained information is determined as new sequence control information and is output to the storage memory data signal 15.

Electrically rewritable nonvolatile memory circuit 2
When the rewriting of the sequence control information is completed, the memory control circuit unit 3 notifies the sequence control circuit unit 5 via the memory data signal 28 of the completion of the rewriting.

When the sequence control circuit section 5 receives the rewrite completion notice, it enables the write inhibit signal 32 to disable the writing to the electrically rewritable nonvolatile memory circuit 2 (see FIG. 3B). ).

The write control circuit 6 includes a write inhibit signal 32
Is recognized, the rewrite execution signal 35 is disabled, and writing to the electrically rewritable nonvolatile memory circuit 2 is prohibited (see FIG. 3D).

After that, the memory control circuit 3 disables the write control signal 30 (see FIG. 3C).

The sequence control circuit unit 5 notifies the memory control circuit unit 3 of the end of rewriting via the memory address signal 27.

The memory control circuit unit 3 notifies the power supply control circuit unit 4 of the end of writing via the control data output signal 24.

Upon receiving the write completion notification, the power supply control circuit unit 4 recognizes the end of writing to the electrically rewritable nonvolatile memory circuit 2 and disables the write command identification signal 31.

By the above operation, the sequence control information of the electrically rewritable nonvolatile memory circuit 2 is rewritten.

[0058]

The effect of the present invention is that a microprogram method is adopted for the sequence control circuit section, and an electrically rewritable nonvolatile memory circuit (memory for storage) and a sequence control circuit section as memories for storing sequence control information. Memory circuit (execution memory) and two memories,
In a sequence control device in which sequence control information of an electrically rewritable nonvolatile memory circuit can be written from a higher-level control device, change of sequence control information of an electrically rewritable nonvolatile memory circuit due to malfunction of a memory control circuit unit And the reliability of the sequence control information can be improved. The reason is that, when rewriting the sequence control information of the electrically rewritable nonvolatile memory circuit, the write inhibit signal from the sequence control circuit is released and the write control signal from the memory control circuit is input. This is because a write control circuit that outputs a rewrite execution signal to the electrically rewritable nonvolatile memory circuit only when necessary is added.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a sequence control device according to one embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a more detailed configuration of a memory control circuit unit in FIG.

FIG. 3 is a timing chart showing an operation of the sequence control device according to the present embodiment.

[Explanation of symbols]

 Reference Signs List 1 memory circuit for sequence control circuit section 2 electrically rewritable nonvolatile memory circuit 3 memory control circuit section 4 power supply control circuit section 5 sequence control circuit section 6 write control circuit 11 execution memory address signal 12 execution memory data signal 13 Execution memory control signal 14 Storage memory address signal 15 Storage memory data signal 16 Storage memory control signal 21 Power-on completion signal 22 Control data input signal 23 Control data input control signal 24 Control data output signal 25 Control data output control signal 26 Control start instruction signal 27 Memory address signal 28 Memory data signal 29 Memory control signal 30 Write control signal 31 Write command identification signal 32 Write inhibit signal 33 Control instruction signal 34 Control status signal 35 Rewrite execution signal 36 Serial data input signal 3 Serial data input control signal 38 Serial data output signal 39 Serial data output control signal 301 Control data input / output control circuit 302 Instruction discrimination execution control circuit 303 Memory address signal switching circuit 304 Memory data signal switching circuit 305 Memory control signal switching circuit 311 Control signal 312 Execution memory control signal 313 Signal switching signal

Claims (6)

(57) [Claims] An electrically rewritable nonvolatile memory circuit, a memory circuit for a sequence control circuit unit, and a sequence control circuit unit which stores sequence control information of the electrically rewritable nonvolatile memory circuit when power is turned on. A memory control circuit for transferring sequence control information to the electrically rewritable nonvolatile memory circuit in response to a memory write command from a higher-level device; and a sequence control information for the sequence control circuit unit memory circuit. A sequence control device that controls a sequence operation based on the sequence control circuit, when rewriting the sequence control information of the electrically rewritable nonvolatile memory circuit, inhibits writing from the sequence control circuit unit. The signal is released, and the write control from the memory control circuit unit is performed. A sequence control device, comprising: a write control circuit that outputs a rewrite execution signal to the electrically rewritable nonvolatile memory circuit only when a signal is input. 2. A sequence control device adopting a microprogram method, comprising: an electrically rewritable nonvolatile memory circuit for holding sequence control information; and a memory read out from the electrically rewritable nonvolatile memory circuit when power is turned on. A memory circuit for a sequence control circuit unit to which the sequence control information is written, a memory write command transmitted from a higher-level control device, a write command identification signal output, and a memory address transmitted subsequent to the memory write command. Power supply control circuit section via a new sequence control information, transfer of sequence control information from the electrically rewritable nonvolatile memory circuit to the memory circuit for the sequence control circuit section, and the electrically rewritable nonvolatile memory Circuit and the memory circuit for the sequence control circuit section. A memory control circuit for writing and reading the contents of an arbitrary address and outputting a write control signal when the memory write command is detected, and a memory circuit for the sequence control circuit via the memory control circuit. The next control means is determined according to the read sequence control information and the control state signal read from the lower controlled part, and the control instruction is given to the lower controlled part via the control instruction signal, and at the time of starting the sequence control. A sequence control circuit for outputting a write inhibit signal and releasing the write inhibit signal when a memory write instruction is received; and a write inhibit signal from the sequence control circuit after receiving a write instruction identification signal from the power control circuit. Is released, and the electric control is performed only when a write control signal is input from the memory control circuit unit. Sequence control apparatus characterized by comprising a write control circuit for outputting a rewriting execution signal to the rewritable type non-volatile memory circuit. 3. The sequence control information is written at the beginning of the sequence control information, and the write control signal is enabled when the sequence control circuit unit starts the sequence control. 3. The sequence control device according to claim 1, wherein the write control circuit does not enable the rewrite execution signal even when the circuit unit enables the write control signal. 4. The memory control circuit unit transfers sequence control information stored in the electrically rewritable nonvolatile memory circuit to the sequence control circuit unit memory circuit when power is turned on. An address signal, a data signal, and a read control signal of the memory circuit for the sequence control circuit are connected to a memory address signal, a memory data signal, and a memory read signal of the sequence control circuit, respectively, and the sequence control circuit is instructed to start control. 3. The sequence control device according to claim 1, wherein 5. A memory address signal switching circuit for switching between connecting a memory address signal for execution to a memory address signal for storage or a memory address signal, and storing the memory data signal for execution. Data signal switching circuit for switching between connection to the memory data signal for use and memory data signal, and memory control for switching between connection of the execution memory control signal to the storage memory control signal and connection to the memory control signal A signal switching circuit, a control data input / output control circuit for controlling input / output of control data, and the memory address signal switching circuit, the memory data signal switching circuit, and the control circuit based on a control signal from the control data input / output control circuit. Instruction discrimination execution control circuit for switching the signal connection of the memory control signal switching circuit 3. The sequence control device according to claim 1, comprising a road. 6. When the command discrimination execution control circuit determines that the information input from the control data input / output control circuit via a control signal is a memory write command, the command determination execution control circuit obtains the information following the memory write command. The information obtained is determined to be a rewrite address and output to a storage memory address signal, and the subsequently obtained information is determined to be new sequence control information and output to a storage memory data signal, and the write control signal is output. The sequence control device according to claim 5.