JPH10320991A - Flash memory writing device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flash memory writing device and a method therefor which are low in cost and can be applied to various types of flash memories. SOLUTION: At the time of the renewal (erasing/writing) of a flash memory 12, the content (loader: flash memory erasing/writing program) of an external ROM 2 are transferred to a RAM 14 while the external ROM 2 is connected to a target system 1. When the loader is practiced by a CPU 11 on the RAM 14, the content of the flash memory 12 is renewed while the output signal of a port connected to the flash memory 12 and the chip selection terminal of the external ROM 2 is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to rewriting of a flash memory on a target system, and particularly has a feature in rewriting of a flash memory executed using a ROM external to the target system.

[0002]

2. Description of the Related Art Conventionally, a flash memory rewriting circuit described in Japanese Patent Application Laid-Open No. Hei 5-233478 is known.

FIG. 5 shows a configuration of a conventional flash memory writing system, where 1 is a target system,
3 is a host system, 12 is a flash memory,
14 is a RAM, 11 is a CPU that controls the entire target system, 17 is an external communication I / F that communicates with the host system 3, and 18 is a loader RO that stores a program for executing erasing / writing of the flash memory.
M and 31 are ROM data storage devices for holding data to be written to the flash memory 12, and 4 is a communication medium that is a medium for executing communication between the target system 1 and the host system 3.

Referring to FIG. 5, a method of erasing / writing data to / from the flash memory 12 will be described. (1) The target system is initialized by reset. (2) Determine whether to update the contents of the flash memory 12 (execute the loader). (3) When the loader is not executed, a normal program is executed. When executing the loader, execute the following routine. (4) The type of the flash memory 12 is identified. Specifically, a type identification command is issued to the flash memory 12 (data for outputting the type is written to a predetermined address) to identify the type. (5) From the type of the flash memory 12 determined in (4), branch to the address of the loader program (loader ROM 18) corresponding to the type. (6) The contents of the flash memory 12 are erased. (7) The contents of the ROM data storage device 31 are transferred to the RAM 14 via the host system 3 and the external communication I / F 17. (8) Write the contents of the RAM 14 to the flash memory 12. (9) At this time, data is written to all addresses to be written in the flash memory 12, and at the same time, the contents are read and compared with the original data (contents of the RAM 14) (verify processing) to find a match. If the writing is completed. When the capacity of data to be written to the flash memory 12 is larger than the capacity of the RAM 14, the above (7)
The contents of the flash memory 12 can be updated by repeatedly executing the processing of (8).

[0005] By the above operation, the flash memory 12
Can be erased and the contents of the ROM data storage device 31 can be written to the flash memory 12.

[0006]

In a conventional target system equipped with a flash memory, a loader ROM including a program for executing rewriting of the flash memory is indispensable. For this reason, a loader ROM that is not required for the operation of the target system is required for the target system, and there is a problem that the scale and cost of the target system increase.

[0007]

In order to solve the above-mentioned problems, a flash memory writing apparatus and method according to the present invention provide a loader program for executing data to be written to a flash memory and erasing and writing to the flash memory. A memory for storing the flash memory and a RAM for storing a loader program supplied from the memory corresponding to the flash memory; and a first chip for activating the memory. A port circuit for selectively outputting a select signal and a second chip select signal for activating the flash memory; and a chip select switch circuit for setting a control state of the first and second chip select signals. C that controls the target system U is by controlling the chip select signal, in which the data of the memory unit to and writes into the flash memory.

According to the present invention, the loader ROM is not required on the target system, so that the target system can be realized at low cost.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flash memory writing apparatus according to claim 1 of the present invention has a memory section for holding data to be written to a flash memory, a loader program for executing erasing and writing to the flash memory, and a target system. A target system unit that stores a flash memory and a RAM that stores a loader program supplied from the memory unit corresponding to the flash memory, a first chip select signal that activates the memory unit, and the flash memory. A port circuit for selectively outputting a second chip select signal to be activated, and a chip select switch circuit for setting a control state of the first and second chip select signals;
The CPU that controls the target system unit controls the chip select signal to write data in the memory unit to the flash memory. Since the target system does not require a loader ROM, the target system does not require a loader ROM. The size and cost of the system can be reduced.

According to a second aspect of the present invention, there is provided a flash memory writing method comprising: a memory section for holding data to be written to the flash memory; a loader program for executing erasing and writing to the flash memory; and a target system section. The target system unit stores a flash memory and a loader program supplied from the memory unit corresponding to the flash memory.
M, a port circuit for selectively outputting a first chip select signal for activating the memory section and a second chip select signal for activating the flash memory, and a first and second chip select signals. A chip select switch circuit for setting a control state; controlling the chip select switch circuit to activate the memory unit by a first chip select signal to turn on a power supply of a target system unit; A predetermined loader program corresponding to the memory is transferred to the RAM of the target system unit, the first chip select signal is enabled, and the second chip select signal is disabled, and the flash data of the memory unit is controlled by the target system unit. CPU reads the signal and then turns off the first chip select signal. And enabling the second chip select signal to write the read flash data into the flash memory, and controlling the first and second chip select signals to transfer the flash data in the memory unit to the flash memory. The size and cost of the target system can be reduced.

(Embodiment 1) An embodiment of the present invention described in claim 1 of the present invention will be described below with reference to FIGS.

In FIG. 1, 1 is a target system,
11, a CPU for controlling the entire target system;
Is a flash memory, 13 is a port circuit including a port control register for controlling the output of a 2-bit port and a port data register for storing the contents of the 2-bit port, 14 is a RAM, 15 is a pull-up resistor or a pull-down resistor. CS switch for switching, 16 is a data bus connected to the CPU 11, 21 is an address bus of the CPU 11,
151 is an internal CS signal line output from the port circuit 13 and connected to the chip select terminal of the flash memory 12;
2 is an external RO existing outside the target system 1
M and 22 are external CS signal lines output from the port circuit 13 and controlling the chip select terminal of the external ROM 2, and 23 is an external CS signal line 2 existing outside the target system 1.
2 is an external pull-down resistor.

FIG. 2 is a detailed explanatory diagram of the CS switch 15. A switch SW, a pull-up resistor RU, and a pull-down resistor RD exist in the CS switch 15.
W is for switching the use of the external ROM 2 and the external RO
When using M2, the internal CS signal line 151 is pulled up.
Connected to the resistor RU, and connected to the Pull Down resistor RD in the case of normal operation in which the target system 1 operates without using the external ROM 2.

FIG. 3 is a detailed explanatory diagram of the port circuit 13. The logic of the driver used in the port circuit 13 is such that the input signal of the driver is IN, the control signal is C,
When the output signal is OUT and the control signal C = 0 (LOW level), the output signal OUT has high impedance. When the control signal C = 1 (HIGH level), the output signal OUT = the through state of the input signal IN. .

Port control register (PCR [1: 0])
161 and the port data register (PDR [1:
0]) 162 is connected to the lower 2 bits of the data bus 16 so that the CPU 11 can write data to these registers.

When the power is turned on, the contents of the port control register 161 are initialized to 00, and the internal CS signal line 151 and the external CS signal line 22 enter a high impedance state.
Also, the first bit PCR [1] /
It is assumed that PDR [1] controls the external CS signal line 22 and the least significant bit PCR [0] / PDR [0] controls the internal CS signal line 151. When the external CS signal line 22 and the internal CS signal line 151 are at the LOW level, the flash memory 12 and the external ROM 2 become valid (the chip select terminal is set to LOW Act).
ive).

Next, a writing method of the flash memory 12 will be described with reference to FIG. First,
A loader program for executing flash memory writing and write data (flash data) are created and written to the external ROM 2.

In step (1), an external pull-down resistor 23 is connected to the target system 1 in order to connect the target system 1 to the external ROM 2 in which the loader program and flash data are written.
Connected at this time are the address bus 21, the data bus 16, the signal line of the external CS signal line 22, and the power / ground (not shown in FIG. 1). As a connection method, a method of providing a test port on the target system 1 and connecting a probe thereto, a method of using a connector, or the like can be considered. In some cases, a buffer is interposed for the connection signal in accordance with the drive capability of the signal line. In any case, it is only necessary that the above signals are logically connected.

In step (2), the CS switch 1
5 is switched to the setting when the external ROM 2 is used (connected to the Pull Up resistor RU).

In step (3), the power of the target system 1 is turned on. Since the chip select terminal of the external ROM 2 is at the LOW level and the chip select terminal of the flash memory 12 is at the HIGH level, the CPU 11 reads and executes the contents of the external ROM 2 after the power is turned on. Thereafter, flash data is written to the flash memory 12 in accordance with the write program in the external ROM 2.

That is, in steps (1) to (3), the external ROM 2 is enabled and the loader program corresponding to the flash memory 12 is stored in the external RO.
M2 to the RAM 14 and erase the contents of the flash memory 12 according to the loader program.
The flash data from the OM2 is stored in the flash memory 12
Write to.

In step (4), the power of the target system 1 is turned off. That is, when the transfer of the flash data in the external ROM 2 (from the external ROM 2 to the flash memory 12) is all completed, the power is turned off.

In step (5), the target system 1 is disconnected from the external ROM 2 to disconnect the target system 1 from the external ROM 2.

In step (6), the CS switch 1
5 is connected to the Pull Down resistor RD for normal use.

In step (7), the target system 1 performs a normal operation. That is, in the target system 1, the CPU 11
And performs normal operation.

Next, the external ROM 2 in the above step (3)
The writing of the internal data will be described in detail.

The contents of the flash memory 12 are erased, the data in the external ROM 2 is read, and the data is written to an appropriate address of the flash memory 12. At this time, the flash memory 12 and the external Data is transferred while controlling the CS signal of the ROM 2. (A) PCR [1: 0] = '00' (or PDR [1: 0] = '01', PCR [1:
0] = '11'). That is, the external ROM 2 is valid, the flash memory 12 is invalid, and the external ROM 2
(Flash data) is read into the CPU 11. (B) Set PDR [1: 0] = '10' and PCR [1: 0] = '11'. That is, the external ROM 2 is disabled, the flash memory 12 is enabled, and the CPU 11 writes the flash data into the flash memory 12.

That is, the contents of the flash memory 12 are erased by enabling the flash memory 12 and then the external R
OM2 is enabled (then, the flash memory is disabled), the CPU 11 reads data from the external ROM 2, and the flash memory 12 is enabled (then, the external ROM is disabled).
(OM2 is invalid) By writing data to the flash memory 12 and repeating the above operations (a) and (b),
Perform predetermined data transfer.

By repeating the required number of data while controlling the port circuit 13 as described above, the contents of the flash memory 12 can be erased, and the flash data in the external ROM 2 can be written to the flash memory 12.

[0030]

As described above, according to the flash memory writing apparatus and method of the present invention, a loader ROM is not required in the target system, and the size and cost of the target system can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a flash memory writing device according to an embodiment of the present invention.

FIG. 2 is a detailed explanatory diagram of a CS switch (15) of the flash memory writing device according to the embodiment of the present invention.

FIG. 3 is a detailed explanatory diagram of a port circuit (13) of the flash memory writing device according to the embodiment of the present invention.

FIG. 4 is a flowchart of a flash memory writing method according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional flash memory writing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Target system 2 External ROM 11 CPU 12 Flash memory 13 Port circuit 14 RAM 15 CS switch circuit 16 Data bus

Claims (2)

[Claims] 1. A flash memory comprising: a memory section for storing data to be written to a flash memory; a loader program for executing erasing and writing to the flash memory; and a target system section, wherein the target system section corresponds to the flash memory and the flash memory. RAM for storing a loader program supplied from the memory unit
A port circuit for selectively outputting a first chip select signal for activating the memory unit and a second chip select signal for activating the flash memory; and control of the first and second chip select signals A flash memory writing device having a chip select switch circuit for setting a state, wherein a CPU controlling the target system unit controls the chip select signal to write data in the memory unit to the flash memory . 2. A flash memory comprising: a memory section for holding data to be written to a flash memory; a loader program for erasing and writing to the flash memory; and a target system section, wherein the target system section corresponds to the flash memory and the flash memory. RAM for storing a loader program supplied from the memory unit
A port circuit for selectively outputting a first chip select signal for activating the memory unit and a second chip select signal for activating the flash memory; and control of the first and second chip select signals A chip select switch circuit for setting a state; controlling the chip select switch circuit to activate the memory unit by a first chip select signal to turn on a power supply of a target system unit; Is transferred to the RAM of the target system unit, and the first chip select signal is enabled and the second chip select signal is disabled, and the flash data of the memory unit is controlled by the target system unit. CPU reads, then the first
Invalidate the chip select signal, enable the second chip select signal, write the read flash data into the flash memory, and control the first and second chip select signals to store the flash data in the memory unit in the flash memory. Flash memory writing method.